TWI427755B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI427755B
TWI427755B TW097129987A TW97129987A TWI427755B TW I427755 B TWI427755 B TW I427755B TW 097129987 A TW097129987 A TW 097129987A TW 97129987 A TW97129987 A TW 97129987A TW I427755 B TWI427755 B TW I427755B
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Taiwan
Prior art keywords
semiconductor
insulating film
semiconductor device
layer
metal layer
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TW097129987A
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English (en)
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TW200913216A (en
Inventor
Hiroyasu Jobetto
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Tera Probe Inc
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Publication of TW200913216A publication Critical patent/TW200913216A/zh
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Publication of TWI427755B publication Critical patent/TWI427755B/zh

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法。
日本特開2000－223518號公報所記載之習知半導體裝置，具有設於矽基板下之複數個外部連接用的柱狀電極。習知之此種半導體裝置係在半導體構成體之平面的面積區域內設置外部連接用電極(Fan－in)的構成，所以，外部連接用電極之配置數量增多，在配置間距比規定尺寸、例如0.5 μm還小之情況，會無法應用。
作為能應用於外部連接用電極之配置數量多的情況且達到小型化者，在日本特開2005－216935號公報中揭示有一種半導體裝置，係將被稱為CSP(chip size package)之半導體構成體設置於平面尺寸比該半導體構成體還大之底板上，並將此底板之大致全區域作為半導體構成體之外部連接用電極的配置區域(Fan－out)。
然而，在上述習知半導體裝置中，因為採用底板，所以，會有裝置整體厚度變厚的問題。
在此，本發明之目的在於，提供一種半導體裝置及其製造方法，在外部連接用電極之配置區域比半導體構成體的平面尺寸還大之構成中，能達成薄型化。
本發明之半導體裝置，其具備半導體構成體(2)，其具有半導體基板(4)及設於該半導體基板下之複數個外部連接用電極(13)；及下層絕緣體(1)，係設於該半導體構成體下及其周圍。於該下層絕緣膜上設置覆被該半導體構成體之周圍的封裝膜(28)，於該下層絕緣膜下具備設置成與該半導體構成體之外部連接用電極連接的下層配線(22)。在上述構成中，下層絕緣膜係除去底部構件後所殘留者。
另外，本發明之半導體裝置之製造方法，其具備：於底板(31)上形成下層絕緣體(1)之步驟；於該下層絕緣體上固定複數個半導體構成體(2)之步驟，其中該半導體構成體(2)具有半導體基板(4)及設於該半導體基板下之複數個外部連接用電極(13)；及於該下層絕緣體上形成覆被該半導體構成體之周圍的封裝膜(28)之步驟。在形成該封裝膜之後，將該底板除去。接著，於該下層絕緣膜下形成與該半導體構成體之外部連接用電極連接的下層配線(22)，並將在該半導體構成體間之該下層絕緣膜及該封裝膜切斷而獲得多個半導體裝置。
根據本發明，因在該半導體構成體之下方及設於其周圍之下層絕緣膜的下方，設置與半導體構成體之外部連接用電極連接的下層配線，且不具備底板，所以，在外部連接用電極之配置區域比半導體構成體的平面尺寸還大之半導 體裝置中，能達成厚度之薄型化。
 (第1實施形態)
第1圖顯示本發明之第1實施形態的半導體裝置之剖視圖。此半導體裝置具備由環氧系樹脂、聚醯亞胺系樹脂、玻璃布基材環氧樹脂等所構成之平面方形的下層絕緣膜1。在下層絕緣膜1之上面中央部介由由環氧系樹脂等所構成之黏著層3搭載有半導體構成體2。此情況時，下層絕緣膜1之平面尺寸係比半導體構成體2之平面尺寸還大。
半導體構成體2具備平面方形之矽基板(半導體基板)4。在矽基板4之下面4a設置規定功能之積體電路(未圖示)，設置在下面周邊部由鋁系金屬等所構成之複數個連接墊5係與積體電路連接。在除連接墊5之中央部以外的矽基板4下面，設置由氧化矽等所構成之絕緣膜6，連接墊5之中央部係透過設於絕緣膜6之開口部7而露出。
在絕緣膜6下面設置由聚醯亞胺系樹脂等所構成之保護膜8。在對應於絕緣膜6之開口部7的部分之保護膜8設有開口部9。在保護膜8之下面設置配線10。配線10成為設於保護膜8下面之由銅所構成的襯底金屬層11、及設於襯底金屬層11下面之由銅所構成的上部金屬層12的2層構造。配線10之一端部係透過絕緣膜6及保護膜8之開口部7,9而連接於連接墊5。
在配線10之連接墊部下面設置由銅所構成之柱狀電極 (外部連接用電極)13。在包含配線10之保護膜8下面，以下面與柱狀電極13之下面成為同一面的方式，設置由環氧系樹脂等所構成之封裝用樹脂膜14。半導體構成體2係介由由環氧系樹脂等所構成之黏著層3而將其柱狀電極13及封裝用樹脂膜14的下面黏著於下層絕緣膜1之上面中央部，藉以搭載於下層絕緣膜1之上面中央部。
在對應於半導體構成體2之柱狀電極13的下面中央部之部分的下層絕緣膜1及黏著層3設置開口部21。在下層絕緣膜1之下面設置下層配線22。下層配線22成為設於下層絕緣膜1下面之由銅所構成的襯底金屬層23、及設於襯底金屬層23下面之由銅所構成的上部金屬層24的2層構造。下層配線22之一端部係透過下層絕緣膜1及黏著層3之開口部21連接於半導體構成體2之柱狀電極13。
在包含下層配線22之下層絕緣膜1下面，設置由抗焊劑等所構成之下層頂塗膜25。在對應於下層配線22之連接墊部的部分之下層頂塗膜25設置開口部26。在下層頂塗膜25之開口部26內及其下方，設置與下層配線22之連接墊部連接的焊球27。在包含半導體構成體2之下層絶緣膜1之上面，設置由環氧系樹脂等所構成的封止膜28。
接著，說明此半導體裝置之製造方法的一例。首先如第2圖所示，準備在由銅箔所構成之底板31上面形成下層絕緣膜1者，此下層絕緣膜1係由環氧系樹脂、聚醯亞胺系樹脂、玻璃布基材環氧樹脂等所構成。在此情況時，此準備好之部件的尺寸，成為可形成複數個第1圖所示之半導 體裝置完成品的尺寸。另外，在第2圖中，元件符號32所示區域係對應於個片化用之切斷線的區域。
另外，準備半導體構成體2。此半導體構成體2係在晶圓狀態之矽基板4下形成積體電路(未圖示)、由鋁系金屬等所構成之連接墊5、由氧化矽等所構成之絕緣膜6、由聚醯亞胺系樹脂等所構成之保護膜8、配線10(由銅所構成的襯底金屬層11、及由銅所構成的上部金屬層12)、由銅所構成之柱狀電極13、及由環氧系樹脂等所構成之封裝用樹脂膜14後，藉由切割予以個片化而可獲得。
接著，在下層絕緣膜1上面之半導體構成體搭載區域，藉著由環氧系樹脂等所構成之黏著層3，黏著半導體構成體2之柱狀電極13及封裝用樹脂膜14的下面，藉以搭載半導體構成體2。在此情況時，在下層絕緣膜1上面之半導體構成體搭載區域，採用印刷法或分配器等預先供給所謂NCP(Non－Conductive Paste)之黏著材，或是預先供給所謂NCF(Non－Conductive Film)之黏著片，並藉由加熱加壓而將半導體構成體2固定於下層絕緣膜1上。在此，NCP及NCF均係覆晶安裝用之樹脂，尤其是被定義為預先供給於下層絕緣膜1，並與柱狀電極之連接一起硬化的樹脂。
再者，如第3圖所示，藉由遞模法等之模塑法，在包含半導體構成體2之下層絕緣膜1上面形成由環氧系樹脂等所構成之封裝膜28。又，封裝膜28亦可由網版印刷法或旋轉塗布法等形成。接著，當藉由蝕刻除去底板31時，如第 4圖所示，下層絕緣膜1之下面被露出。在此狀態下，即使除去底板31，但藉由封裝膜28及下層絕緣膜1之存在，仍可確保足夠之強度。
接著，如第5圖所示，在對應於半導體構成體2之柱狀電極13的下面中央部之部分的下層絕緣膜1及黏著層3，藉由雷射光束之照射的雷射加工形成開口部21。接著，如第6圖所示，在下層絕緣膜1之下面整體，藉由銅之無電解電鍍形成襯底金屬層23，其中下層絕緣膜1包含透過下層絕緣膜1及黏著層3之開口部21而露出的半導體構成體2之柱狀電極13的下面。
接著，藉由進行以襯底金屬層23作為電鍍電流通路之銅的電解電鍍，在襯底金屬層23之下面整體形成上部金屬層24。接著，當藉由光微影法對上部金屬層24及襯底金屬層23進行圖案加工時，如第7圖所示，在下層絕緣膜1之下面形成由襯底金屬層23及上部金屬層24所構成之2層構造的下層配線22。
接著，如第8圖所示，在包含下層配線22之下層絕緣膜1的下面，藉由網版印刷法或旋轉塗布法等，形成由抗焊劑等所構成之下層頂塗膜25。接著，在對應於下層配線22之連接墊部的部分之下層頂塗膜25，藉由雷射照射之雷射加工形成開口部26。
接著，在下層頂塗膜25之開口部26內及其下方，形成與下層配線22之連接墊部連接的焊球27。接著，如第9 圖所示，在相互鄰接之半導體構成體2之間，沿切斷線32切斷封裝膜28、下層絕緣膜1及下層頂塗膜25，即可獲得複數個第1圖所示之半導體裝置。
在如此所獲得之半導體裝置中，因設在半導體構成體2之下方及於其周圍之下層絕緣膜1的下方，設有與下層配線22連接之半導體構成體2的柱狀電極13，所以，可將焊球(外部連接用電極)27之配置區域作成比半導體構成體2的平面尺寸還大(Fan－out)，而且，不具備底板31，所以，能達成薄型化。又，底板31亦可係由鋁等之其他金屬所形成。
在第6圖所示之步驟中，在形成襯底金屬層23之後，亦可進行如第10圖所示的步驟。亦即，在襯底金屬層23之下面圖案加工形成抗鍍膜33。在此情況時，在對應於上部金屬層24形成區域之部分的抗鍍膜33，形成有開口部34。
接著，藉由進行以襯底金屬層23作為電鍍電流通路之銅的電解電鍍，在抗鍍膜33之開口部34內的襯底金屬層23之下面，形成上部金屬層24。接著，將抗鍍膜33剝離，然後以上部金屬層24作為遮罩，蝕刻除去襯底金屬層23的不需要部分，如第7圖所示，僅在上部金屬層24殘留襯底金屬層23。
(第2實施形態)
第11圖顯示本發明之第2實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示之半導體裝置的差 異點在於：將下層配線22作成為由銅所構成的第1襯底金屬層23a、由銅所構成的第2襯底金屬層23b及由銅所構成的上部金屬層24的3層構造。在此情況時，在對應於半導體構成體2之柱狀電極13的下面中央部之部分的下層絕緣膜1、絕緣層3及第1襯底金屬層23a設置開口部21。
接著，說明此半導體裝置之製造方法的一例。首先如第12圖所示，準備在由銅箔構成之底板31上面形成保護金屬層35、第1襯底金屬層23a及下層絕緣膜1者，其中，保護金屬層35係由無電解鍍鎳所構成，第1襯底金屬層23a係由無電解鍍銅所構成，下層絕緣膜1係由環氧系樹脂、聚醯亞胺系樹脂、玻璃布基材環氧樹脂等所構成。
在此情況時亦是，此準備完之部件的尺寸，成為可形成複數個第11圖所示之半導體裝置完成品的尺寸。另外，在第12圖中，元件符號32所示區域係對應於個片化用之切斷線的區域。在此，第1襯底金屬層23a之上面23a1，為了能提高與形成於其上面之由含樹脂之材料所構成的下層絕緣膜1的密接性，藉由施以表面粗糙化處理，而被表面粗糙化。此點係與上述第1實施形態的情況存在較大之差異。在此，作為表面粗糙化處理之一例，可列舉將第1襯底金屬層23a之上面浸泡於適宜之蝕刻液中的方法，但並不限定於此方法。
接著，在下層絕緣膜1上面之半導體構成體搭載區域，介由由環氧系樹脂等所構成之黏著層3，黏著半導體構成 體2之柱狀電極13及封裝用樹脂膜14的下面，藉以搭載半導體構成體2。在此情況時亦是，對下層絕緣膜1上面之半導體構成體搭載區域，預先供給所謂NCP(Non－Conductive Paste)之黏著材、或是所謂NCF(Non－Conductive Film)之黏著片，並藉由加熱加壓而將半導體構成體2固定於下層絕緣膜1上。
再者，如第13圖所示，藉由網版印刷法、旋轉塗布法、遞模法等，在包含半導體構成體2之下層絕緣膜1上面形成由環氧系樹脂等所構成之封裝膜28。接著，當藉由蝕刻連續地除去底板31及保護金屬層35時，如第14圖所示，第1襯底金屬層23a之下面被露出。
此情況時，由鎳所構成之保護金屬層35，係在藉由蝕刻除去由銅所構成之底板31時，用以保護而不致使同樣由銅所構成之第1襯底金屬層23a亦被除去。在此狀態之下，即使除去底板31及保護金屬層35，藉由封裝膜28、下層絕緣膜1及第1襯底金屬層23a之存在，仍可確保足夠之強度。
接著，如第15圖所示，在對應於半導體構成體2之柱狀電極13的下面中央部之部分的第1襯底金屬層23a、下層絕緣膜1及黏著層3，藉由雷射光束之照射的雷射加工形成開口部21。接著，如第16圖所示，在第1襯底金屬層23a之下面整體，藉由銅之無電解電鍍形成第2襯底金屬層23b，其中第1襯底金屬層23a係包含透過第1襯底金屬層 23a、下層絕緣膜1及黏著層3之開口部21而露出的半導體構成體2之柱狀電極13的下面。
接著，藉由進行以第1,第2襯底金屬層23a,23b作為電鍍電流通路之銅的電解電鍍，在第2襯底金屬層23b之下面整體形成上部金屬層24。接著，當藉由光微影法對上部金屬層24及第1,第2襯底金屬層23a,23b進行圖案加工時，如第17圖所示，在下層絕緣膜1之下面形成由第1,第2襯底金屬層23a,23b及上部金屬層24所構成之3層構造的下層配線22。以下，經過與上述第1實施形態之情況相同的步驟，即可獲得複數個第11圖所示之半導體裝置。
(第3實施形態)
第18圖顯示本發明之第3實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示之半導體裝置的差異點在於：在半導體構成體2之周圍的下層絕緣膜1的上面預先形成上層配線41，上層配線41係由無電解鍍銅所構成之襯底金屬層42及由電解鍍銅所構成之上部金屬層43的2層構造。亦即，上層配線41係，例如，如第2圖所示，在形成於底板31上面之下層絕緣膜1的上面，在搭載半導體構成體2之前所形成。
另外，例如，在第5圖所示步驟中，在對下層絕緣膜1及黏著層3形成開口部21的同時，在對應於上層配線41之連接墊部的部分之下層絕緣膜1形成開口部44。下層配線22之一部分係透過此開口部44而與上層配線41之連接 墊部連接。
(第4實施形態)
第19圖顯示本發明之第4實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示之半導體裝置較大差異在於：將下層配線作成2層配線構造。亦即，設於第1下層絕緣膜1A下面之第1下層配線22A的一端部，係透過設於第1下層絕緣膜1A及黏著層3之開口部21A，而與半導體構成體2之柱狀電極13連接。在包含第1下層配線22A之第1下層絕緣膜1A的下面，設置由與第1下層絕緣膜1A相同之材料所構成的第2下層絕緣膜1B。
設於第2下層絕緣膜1B下面之第2下層配線22B的一端部，係透過設於第2下層絕緣膜1B之開口部21B，而與第1下層配線22A之連接墊部連接。在包含第2下層配線22B之第2下層絕緣膜1B的下面，設置下層頂塗膜25。在下層頂塗膜25之開口部26內及其下方設置焊球27，且使其與第2下層配線22B之連接墊部連接。又，下層配線亦可為3層以上之配線構造。
(第5實施形態)
第20圖顯示本發明之第5實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示之半導體裝置的較大差異在於：在半導體構成體2周圍之下層絕緣膜1的上面，介由黏著層52黏著由電阻或電容器等所構成之晶片零件51。在此情況時，2根之下層配線22之各一端部，係透 過形成於下層絕緣膜1及黏著層52之開口部53而與晶片零件51之兩電極54連接。
(第6實施形態)
第21圖顯示本發明之第6實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第18圖所示之半導體裝置的較大差異在於：在設於半導體構成體2周圍之下層絕緣膜1上面的上層配線41之上面，搭載晶片零件51。在此情況時，晶片零件51之兩電極54係透過焊料55而連接於上層配線41。
(第7實施形態)
第22圖顯示本發明之第7實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示之半導體裝置的較大差異在於：半導體構成體2不具備封裝用樹脂膜14。因此，在此情況時，包含半導體構成體2之配線10及柱狀電極13的保護膜8之下面，係透過黏著層3而連接於下層絕緣膜1之上面中央部。下層配線22之一端部，係透過下層絕緣膜1及黏著層3之開口部21，而連接於半導體構成體2之柱狀電極13。
(第8實施形態)
第23圖顯示本發明之第8實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第22圖所示之半導體裝置的較大差異在於：半導體構成體2還不具備柱狀電極13。因此，在此情況時，包含半導體構成體2之配線10的保護膜8之下面，係透過黏著層3而連接於下層絕緣膜1之上面中央 部。下層配線22之一端部，係透過下層絕緣膜1及黏著層3之開口部21，而連接於半導體構成體2之配線10的連接墊部(外部連接用電極)。
(第9實施形態)
第24圖顯示本發明之第9實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第23圖所示之半導體裝置的較大差異在於：在包含半導體構成體2之配線10的保護膜8之下面，設置由聚醯亞胺系樹脂、環氧樹脂等之絕緣材料所構成的靜電防止用保護膜61。因此，在此情況時，半導體構成體2之保護膜61的下面，係介由黏著層3而黏著於下層絕緣膜1之上面中央部。下層配線22之一端部，係透過下層絕緣膜1、黏著層3及保護膜61之開口部21，而連接於半導體構成體2之配線10的連接墊部。
但是，在將半導體構成體2搭載於下層絕緣膜1上之前，在保護膜61上未形成開口部21。不具有開口部21之保護膜61，其本身係在從形成於晶圓狀態之矽基板4下的時間點起至半導體構成體2被搭載於下層絕緣膜1上之時間點為止的期間，用以保護形成於矽基板4下之積體電路使不受靜電的影響者。
1‧‧‧下層絕緣膜
2‧‧‧半導體構成體
3‧‧‧黏著層
4‧‧‧矽基板
5‧‧‧連接墊
6‧‧‧絕緣膜
8‧‧‧保護膜
10‧‧‧下層配線
13‧‧‧柱狀電極
14‧‧‧封裝用樹脂膜
22‧‧‧下層配線
25‧‧‧下層頂塗膜
27‧‧‧焊球
28‧‧‧封裝膜
31‧‧‧底板
32‧‧‧切斷線
35‧‧‧保護金屬層
第1圖為本發明之第1實施形態的半導體裝置之剖視圖。
第2圖為在第1圖所示半導體裝置之製造方法的一例中，最初之步驟的剖視圖。
第3圖為接續第2圖之的剖視圖。
第4圖為接續第3圖之的剖視圖。
第5圖為接續第4圖之的剖視圖。
第6圖為接續第5圖之的剖視圖。
第7圖為接續第6圖之的剖視圖。
第8圖為接續第7圖之的剖視圖。
第9圖為接續第8圖之的剖視圖。
第10圖為在第1圖所示半導體裝置之製造方法的另一例中，說明規定步驟用的剖視圖。
第11圖為本發明之第2實施形態的半導體裝置之剖視圖。
第12圖為在第11圖所示半導體裝置之製造方法的一例中，最初之步驟的剖視圖。
第13圖為接續第12圖之的剖視圖。
第14圖為接續第13圖之的剖視圖。
第15圖為接續第14圖之的剖視圖。
第16圖為接續第15圖之的剖視圖。
第17圖為接續第16圖之的剖視圖。
第18圖為本發明之第3實施形態的半導體裝置之剖視圖。
第19圖為本發明之第4實施形態的半導體裝置之剖視圖。
第20圖為本發明之第5實施形態的半導體裝置之剖視圖。
第21圖為本發明之第6實施形態的半導體裝置之剖視 圖。
第22圖為本發明之第7實施形態的半導體裝置之剖視圖。
第23圖為本發明之第8實施形態的半導體裝置之剖視圖。
第24圖為本發明之第9實施形態的半導體裝置之剖視圖。
1‧‧‧層絕緣膜
2‧‧‧半導體構成體
3‧‧‧黏著層
28‧‧‧封裝膜
31‧‧‧底板
32‧‧‧切斷線

Claims (21)

  1. 一種半導體裝置，其特徵為具備：半導體構成體(2)，其具有半導體基板(4)及設於該半導體基板下之複數個外部連接用電極(13)；下層絕緣體(1)，係設於該半導體構成體下及其周圍；封裝膜(28)，係設於該下層絕緣膜上，且覆被該半導體構成體之周圍；及下層配線(22)，係設於該下層絕緣膜下，且連接於該半導體構成體之外部連接用電極，其中，該下層配線係包含第1金屬層(23a)、第2金屬層(23b)及第3金屬層(24)。
  2. 如申請專利範圍第1項之半導體裝置，其中該半導體構成體係藉由黏著層(3)而黏著於於該下層絕緣膜上。
  3. 如申請專利範圍第1項之半導體裝置，其中在該下層配線下及該下層絕緣膜下設置下層頂塗膜(25)，該下層頂塗膜(25)係在與該下層配線之接墊部對應的部分具有開口部(26)。
  4. 如申請專利範圍第3項之半導體裝置，其中在該下層頂塗膜之開口部內及其下方設有與該下層配線之接墊部連接的焊球(27)。
  5. 如申請專利範圍第1項之半導體裝置，其中該封裝膜係被覆該半導體構成體之該半導體基板的上面。
  6. 如申請專利範圍第1項之半導體裝置，其中該下層配線 具有多層構造。
  7. 如申請專利範圍第1項之半導體裝置，其中在該半導體構成體周圍之該下層絕緣膜的上面，設有與該下層配線連接之上層配線(41)。
  8. 如申請專利範圍第7項之半導體裝置，其中在該上層配線上設置晶片零件(51)。
  9. 如申請專利範圍第1項之半導體裝置，其中在該下層絕緣膜上設有與該下層配線連接之晶片零件。
  10. 如申請專利範圍第9項之半導體裝置，其中該晶片零件係透過黏著層而黏著於該下層絕緣膜上。
  11. 如申請專利範圍第1項之半導體裝置，其中該半導體構成體具有封裝用樹脂膜(14)，設於該半導體基板下之該外部連接用電極間。
  12. 如申請專利範圍第1項之半導體裝置，其中該半導體構成體具有黏著層(3)，設於該半導體基板下之該外部連接用電極間。
  13. 一種半導體裝置之製造方法，其特徵為具備：於底板(31)上形成下層絕緣體(1)之步驟；於該下層絕緣體上固定複數個半導體構成體(2)之步驟，其中該半導體構成體(2)具有半導體基板(4)及設於該半導體基板下之複數個外部連接用電極(13)；於該下層絕緣體上形成覆被該半導體構成體之周圍的封裝膜(28)之步驟； 除去該底板之步驟；於該下層絕緣膜下形成與該半導體構成體之外部連接用電極連接的下層配線(22)之步驟；及將在該半導體構成體間之該下層絕緣膜及該封裝膜切斷而獲得多個半導體裝置之步驟，其中在該下層絕緣體上固定該半導體構成體之步驟，包括預先將黏著材(3)或接著片供給至該下層絕緣體上，並於該下層絕緣膜上加熱加壓該半導體構成體之步驟。
  14. 如申請專利範圍第13項之半導體裝置之製造方法，其中在形成該下層配線之前，具有在與該半導體構成體之外部連接用電極對應的部分之該下層絕緣膜及該黏著層上形成開口部(21)之步驟。
  15. 如申請專利範圍第13項之半導體裝置之製造方法，其中在由金屬構成之該底板上形成保護金屬層(35)及第1襯底金屬層(23a)，該下層絕緣膜(1)係形成於該第1襯底金屬層上，而除去該底板之步驟包括除去該保護金屬層的步驟。
  16. 如申請專利範圍第15項之半導體裝置之製造方法，其中在形成該下層絕緣膜之前，對該第1襯底金屬層之上面(23a1)施以表面粗糙化處理，藉由包含樹脂之材料形成該下層絕緣膜。
  17. 如申請專利範圍第16項之半導體裝置之製造方法，其中在除去該底板及該保護金屬層之後，具有在與該半導體 構成體之外部連接用電極對應的部分之該第1襯底金屬層、該下層絕緣膜及該黏著層上形成開口部(21)之步驟。
  18. 如申請專利範圍第17項之半導體裝置之製造方法，其中形成該下層配線之步驟，包括在該第1襯底金屬層上形成第2襯底金屬層(23b)，在該第2襯底金屬層上藉由電解電鍍形成上部金屬層(24)之步驟，該下層配線係第1，第2襯底金屬層(23a,23b)及該上部金屬層(24)之3層構造。
  19. 如申請專利範圍第18項之半導體裝置之製造方法，其中該底板、該第1，第2襯底金屬層及該上部金屬層係由銅所構成，該保護金屬層係由鎳所構成。
  20. 如申請專利範圍第13項之半導體裝置之製造方法，其中在該底板上形成該下層絕緣膜之後，具有在該下層絕緣膜上且在該半導體構成體搭載區域的周圍形成上層配線(41)之步驟，並在該下層絕緣膜下形成與該上層配線連接之下層配線。
  21. 如申請專利範圍第13項之半導體裝置之製造方法，其中該封裝膜(28)之形成係藉由模塑法所形成。
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KR101084924B1 (ko) 2011-11-17
CN101548378B (zh) 2012-05-02
US20090039510A1 (en) 2009-02-12
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