CN101548378A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101548378A
CN101548378A CNA200880000828XA CN200880000828A CN101548378A CN 101548378 A CN101548378 A CN 101548378A CN A200880000828X A CNA200880000828X A CN A200880000828XA CN 200880000828 A CN200880000828 A CN 200880000828A CN 101548378 A CN101548378 A CN 101548378A
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dielectric film
semiconductor structure
wiring route
semiconductor
semiconductor device
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CN101548378B (zh
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定别当裕康
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Abstract

一种半导体器件，包括由半导体衬底(4)和多个设置于所述半导体衬底下方的外部连接电极构成的半导体结构(2)。下绝缘膜(1)设置于所述半导体结构的下方和外侧。密封膜(28)设置于所述下绝缘膜上以覆盖所述半导体结构的外围。多个下布线线路(22)设置于所述下绝缘膜下方并分别连接至所述半导体结构的所述外部连接电极。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
日本专利申请公开公布No.2000-223518中描述的一种传统半导体器件具有多个设置于硅衬底下方的外部连接柱状电极。这种传统半导体器件具有在半导体结构(扇入)的平面分布区域中设置外部连接电极的构造，因此布置有大量的外部连接电极，使得其在布置间距小于预定大小(例如，大约0.5μm)时不能应用。
日本专利申请公开公布No.2005-216935中已经公开了一种半导体器件，该半导体器件可用于所布置的外部连接电极的数量很大的情况并且其尺寸减小，其中被称为芯片尺寸封装(CSP)的半导体结构设置在平面尺寸大于所述半导体结构的平面尺寸的基板上，并且该基板的全部区域基本充当用于布置所述半导体结构(扇出)的外部连接电极的区域。
如上所述的传统半导体器件使用基板，因此具有整个器件的厚度增加的问题。
发明内容
因此，本发明的目的是当用于布置外部连接电极的区域大于半导体结构的平面尺寸时提供一种能够减小厚度的半导体器件及其制造方法。
根据本发明的一方面的半导体器件包括：半导体结构，具有半导体衬底和多个设置于所述半导体衬底下方的外部连接电极；以及下绝缘膜，设置于所述半导体结构下方和周围。覆盖所述半导体结构的外围的密封膜设置在所述下绝缘膜上，并且连接至所述半导体结构的外部连接电极的下布线线路设置在所述下绝缘膜下方。所述下绝缘膜是去除了基板构件后的剩余部分。
根据本发明的另一方面的半导体器件制造方法包括：提供具有下绝缘膜的基底衬底；将多个半导体结构固定在所述下绝缘膜上，每一个所述半导体结构包括半导体衬底和多个设置于所述半导体衬底下方的外部连接电极；在所述下绝缘膜上形成覆盖所述半导体结构的外围的密封膜。在已经形成所述密封膜后，去除所述基板。然后，在所述下绝缘膜下方形成下布线线路，从而将该布线线路连接至所述半导体结构的外部连接电极，并且切割所述半导体结构之间的所述下绝缘膜和所述密封膜，以获得多个半导体器件。
根据本发明，所述下布线线路设置于所述下绝缘膜下方，使得该下布线线路连接至所述半导体结构的所述外部连接电极，并且不设置基板，从而使得半导体器件的厚度减小，其中所述下绝缘膜设置于所述半导体结构下方和周围，所述半导体器件中用于布置外部连接电极的区域大于半导体结构的平面尺寸。
附图说明
图1是作为本发明第一实施例的半导体器件的截面图；
图2是图1所示的半导体器件的制造方法的一个范例中的初始步骤的截面图；
图3是图2之后的步骤的截面图；
图4是图3之后的步骤的截面图；
图5是图4之后的步骤的截面图；
图6是图5之后的步骤的截面图；
图7是图6之后的步骤的截面图；
图8是图7之后的步骤的截面图；
图9是图8之后的步骤的截面图；
图10是示出以解释图1所示的半导体器件的制造方法的另一范例中的预定步骤的截面图；
图11是作为本发明第二实施例的半导体器件的截面图；
图12是图11所示的半导体器件的制造方法的一个范例中的初始步骤的截面图；
图13是图12之后的步骤的截面图；
图14是图13之后的步骤的截面图；
图15是图14之后的步骤的截面图；
图16是图15之后的步骤的截面图；
图17是图16之后的步骤的截面图；
图18是作为本发明第三实施例的半导体器件的截面图；
图19是作为本发明第四实施例的半导体器件的截面图；
图20是作为本发明第五实施例的半导体器件的截面图；
图21是作为本发明第六实施例的半导体器件的截面图；
图22是作为本发明第七实施例的半导体器件的截面图；
图23是作为本发明第八实施例的半导体器件的截面图；
图24是作为本发明第九实施例的半导体器件的截面图。
具体实施方式
(第一实施例)
图1示出了作为本发明第一实施例的半导体器件的截面图。该半导体器件包括由例如环氧树脂、聚酰亚胺树脂或具有玻璃布基底材料的环氧树脂制成的平面正方形下绝缘膜1。平面正方形半导体结构2通过由例如环氧树脂制成的粘结层3安装在或固定附着到所述下绝缘膜1的上表面的大体上的中心或中心区域。在这种情况下，所述下绝缘膜1的平面尺寸大于所述半导体结构2的平面尺寸。
半导体结构2包括平面正方形硅衬底(半导体衬底)4。具有预定功能的集成电路(未示出)设置于硅衬底4的下表面4a上。在该下表面4a的外围部分上，设置有多个由例如铝基金属制成的连接焊盘5，使得这些连接焊盘电连接至所述集成电路。由例如二氧化硅制成的绝缘膜6设置于所述硅衬底4的下表面以及除了连接焊盘5的中央之外的连接焊盘5上，所述连接焊盘5通过设置于绝缘膜6中的开口7暴露出来。
由例如聚酰亚胺树脂制成的保护膜8设置于绝缘膜6的下表面上。在保护膜8中与绝缘膜6的开口7对应的部分设置开口9。布线线路10设置于保护膜8的下表面上。每个布线线路10具有由基础金属层(foundationmetal layer)11和上金属层12构成的双层结构，所述基础金属层11由铜制成并设置于保护膜8的下表面上，所述上金属层12由铜制成并设置于所述基础金属层11的下表面上。布线线路10的一个末端通过绝缘膜6中的开口7和保护膜8中的开口9电连接至连接焊盘5。
由铜制成的柱状电极(外部连接电极)13设置于所述布线线路10的另一端或连接焊盘部分。以包围柱状电极13的方式将由例如环氧树脂制成的密封树脂膜或层14设置在保护膜8和布线线路10的下表面上。密封树脂膜14的下表面与柱状电极13的下表面齐平。半导体结构2的柱状电极13和密封树脂膜14的下表面通过由例如环氧树脂制成的粘结层3粘着地芯结合在下绝缘膜1的上表面的中央区域，从而将半导体结构2安装到下绝缘膜1的上表面的中央。
在下绝缘膜1和粘结层3的与半导体结构2的柱状电极13的下表面的中央对应的部分中设置多个开口21。下布线线路22设置于下绝缘膜1的下表面上。每个下布线线路22具有由基础金属层23和上金属层24构成的双层结构，所述基础金属层23由铜制成并设置于下绝缘膜1的下表面上，所述上金属层24由铜制成并且设置于基础金属层23的下表面上。下布线线路22的一端通过下绝缘膜1和柱状电极13中的开口21电连接至半导体结构2的柱状电极13。
由例如阻焊剂制成的下覆盖膜25设置于下布线线路22的下表面和下绝缘膜1的下表面上。在下覆盖膜25中与下布线线路22的另一端或连接焊盘部分对应的部分形成开口26。焊球27设置于下覆盖膜25的开口部分26中及其下方，使得该焊球电连接且机械连接至下布线线路22的连接焊盘部分。由例如环氧树脂制成的密封膜28或层设置于半导体结构2的上表面以及下绝缘膜1的上表面上，以包围所述半导体结构2。
接下来，将描述一个制造该半导体器件的方法的范例。首先，如图2所示，制备一单元，其中在由铜箔制成的基板(基底衬底)31的上表面上形成下绝缘膜1，所述下绝缘膜1由例如环氧树脂、聚酰亚胺树脂或具有玻璃布基底材料的环氧树脂制成。在这种情况下，确定所制备的这一单元的尺寸，从而能够形成多个图1所示的最终的半导体器件。此外，在图2中，以参考标记32表示的区域是与用于分成多个部分(pieces)的切割线相对应的区域。
此外，制备半导体结构2。为了获得该半导体结构2，在晶圆状态的硅衬底4下方形成集成电路(未示出)、由例如铝基金属制成连接焊盘5、由例如二氧化硅制成的绝缘膜6、由例如环氧树脂制成的保护膜8、布线线路10(由铜制成的基础金属层11和由铜制成的上金属层12)、由铜制成的柱状电极13以及由例如环氧树脂制成的密封树脂膜14，然后通过划片将这些分成多个部分。
然后，半导体结构2的柱状电极13和密封树脂膜14的下表面通过由例如环氧树脂制成的粘结层粘着地结合在下绝缘膜1的上表面上的半导体结构安装区域，从而将半导体结构2安装到其上。在这种情况下，利用例如印刷法或分配器预先为下绝缘膜1的上表面上的半导体结构安装区域提供被称为非导电膏(NCP)的胶粘剂，或提供被称为非导电性膜(NCF)的粘结片，并通过热压结合将半导体结构2固定地连接至下绝缘膜1。这里，NCP和NCF两者都是用于倒装芯片安装的树脂，并且特别限定为预先提供给下绝缘膜1并与柱状电极的连接一起固化的树脂。
然后，如图3所示，通过诸如传递模制的模制法，在包括半导体结构2的下绝缘膜1的上表面上形成由例如环氧树脂制成的密封膜28。另外，可以通过例如丝网印刷法或旋转涂布法形成密封膜28。然后，如图4所示，通过刻蚀去除基板31，从而将绝缘膜1的下表面暴露出来。在这种情况下，尽管去除了基板31，但是由于密封膜28和下绝缘膜1的存在，因而能够保证足够的强度。
然后，如图5所示，通过基于激光束应用的激光处理在下绝缘膜1和粘结层3的与半导体结构2的柱状电极13的下表面的中央相对应的部分中形成开口21。然后，如图6所示，通过在下绝缘膜1的整个下表面(包括通过下绝缘膜1和粘结层3中的开口21暴露出来的半导体结构2的柱状电极13的下表面)上进行无电镀铜来形成基础金属层23。
然后，通过使用基础金属层23作为镀覆电流路径来进行电解镀覆铜，从而在基础金属层23的整个下表面上形成上金属层24。然后，如图7所示，通过光刻法对上金属层24和基础金属层23进行构图，从而在下绝缘膜1的下表面上形成下布线线路22，所述下布线线路22具有由基础金属层23和上金属层24构成的双层结构。
然后，如图8所示，通过例如丝网印刷法或旋转涂布法，在包括下布线线路22的下绝缘膜1的下表面上形成由例如阻焊剂制成的下覆盖膜25。然后，通过基于激光束应用的激光处理，在下覆盖膜25的与下布线线路22的连接焊盘部分相对应的部分中形成开口26。
然后，在下覆盖膜25的开口26中及其下方形成焊球27，使得该焊球连接至下布线线路22的连接焊盘部分。然后，如图9所示，沿着相邻半导体结构2之间的切割线32切割密封膜28、下绝缘膜1以及下覆盖膜25，从而获得多个如图1所示的半导体器件。
在这样获得的半导体器件中，由于下布线线路22设置于半导体结构2的下方和半导体结构2周围设置的下绝缘膜1的下方，使得该下布线线路连接至半导体结构2的柱状电极13，因此用于布置焊球(外部连接电极)27的区域大于半导体结构2(扇出)的平面尺寸，并且不设置基板31，从而能够减小厚度。另外，可以通过诸如铝的其他金属来形成基板31。另一方面，在已经形成了基础金属层23之后图6所示的步骤可以如图10所示。也就是说，在基础金属层23的下表面上构图/形成抗镀覆膜33。在这种情况下，在抗镀覆膜33的与形成上金属层24的区域对应的部分中形成开口34。
然后，使用基础金属层23作为镀覆电流路径，进行电解镀覆铜，从而在抗镀覆膜33的开口34中的基础金属层23的下表面上形成上金属层24。然后，分离抗镀覆膜33，使用上金属层24作为掩模刻蚀并去除基础金属层23的不必要部分，使得基础金属层23仅保留在上金属层24上，如图7所示。
(第二实施例)
图11示出了作为本发明第二实施例的半导体器件的截面图。该半导体器件与图1所示的半导体器件的不同之处在于：下布线线路22具有由第一基础金属层23a、第二基础金属层23b以及上金属层24构成的三层结构，所述第一基础金属层23a、第二基础金属层23b以及上金属层24都由铜制成。开口21设置于下绝缘膜1、粘结层或绝缘层3以及第一基础金属层23a的与半导体结构2的柱状电极13的下表面的中央相对应的部分中。第二基础金属层23b通过开口21连接至柱状电极13。
接下来，将描述该半导体器件的制造方法的一个范例。首先，如图12所示，制备基底衬底，其中在由铜箔(金属层)制成的基板3上形成由无电镀镍制成的保护金属层35以及由无电镀铜制成的第一基础金属层23a。在所述基底衬底的上表面上形成下绝缘膜1，所述下绝缘膜1由例如环氧树脂、聚酰亚胺树脂或具有玻璃布基底材料的环氧树脂制成。
同样在这种情况下，确定所制备的这一单元的尺寸，从而能够形成多个如图11所示的最终的半导体器件。此外，在图12中，参考标记32表示的区域是与用于分成多个部分的切割线相对应的区域。这里，为了与下绝缘膜1具有更紧密的接触，第一基础金属层23a的上表面23a1是通过表面粗糙化而变得粗糙的表面，所述下绝缘膜1由含有树脂的材料制成且形成在该上表面上。这是明显不同于如上所述的第一实施例的特征。这里，所述表面粗糙化的一个范例包括将第一基础金属层23a的上表面浸入适当的刻蚀溶液中，但是不限于该方法。
然后，将半导体结构2的柱状电极13和密封膜14的下表面通过粘结层3粘着地结合在下绝缘膜1的上表面上的半导体结构安装区域，从而将半导体结构2安装到其上，其中所述粘结层3由例如环氧树脂制成。同样在这种情况下，预先向下绝缘膜1的上表面上的半导体结构安装区域提供被称为非导电性膏(NCP)的胶粘剂，或被称为非导电性膜(NCF)的粘结片，并且通过热压结合将半导体结构2固定地连接至下绝缘膜1。
然后，如图13所述，通过例如丝网印刷法、旋转涂布法或传递模制法，在包括半导体结构2的下绝缘膜1的上表面上形成由例如环氧树脂制成的密封膜28。然后，通过刻蚀依次去除基板31和保护金属层35，从而如图14所示将第一基础金属层23a的下表面暴露出来。
在这种情况下，当通过刻蚀去除由铜制成的基板31时，由镍制成的保护金属层35保护第一基础金属层23a不被刻蚀，所述第一基础金属层23a同样由铜制成。此外，在这种情况下，尽管去除了基板31和保护金属层35，由于密封膜28、下绝缘膜1以及第一基础金属层23a的存在，因此能够保证足够的强度。
然后，如图15所示，通过基于激光束应用的激光处理，在第一基础金属层23a、下绝缘膜1和粘结层3的与半导体结构2的柱状电极13的下表面的中央相对应的部分中形成开口21。然后，如图16所示，通过在第一基础金属层23a的整个下表面(包括通过下绝缘膜1和粘结层3中的开口21暴露出来的半导体结构2的柱状电极13的下表面)上进行无电镀铜来形成第二基础金属层23b。
然后，通过使用第一和第二基础金属层23a、23b作为镀覆电流路径来进行电解镀覆铜，从而在第二基础金属层23b的整个下表面之上形成上金属层24。然后，如图7所示，通过光刻法对上金属层24以及第一和第二基础金属层23a和23b进行构图，从而在下绝缘膜1的下表面上形成下布线线路22，所述下布线线路22具有由第一和第二基础金属层23a、23b以及上金属层24构成的三层结构。随后，在与如上所述的第一实施例的步骤类似的步骤之后，得到多个如图11所示的半导体器件。
(第三实施例)
图18示出了作为本发明第三实施例的半导体器件的截面图。该半导体器件与图1所示的半导体器件的很大不同之处在于：预先在下绝缘膜1的上表面上围绕半导体结构2形成上布线线路41，所述上布线线路41具有由通过无电镀铜制成的基础金属层42和通过电解镀铜制成的上金属层43构成的双层结构；并且每个上布线线路41连接至不同的下布线线路22。也就是说，例如，如图2所示，在半导体结构2安装到绝缘膜1的上表面上之前形成上布线线路41，所述下绝缘膜1形成在基板31的上表面上。
然后，例如，在如图5所示的步骤中，在下绝缘膜1和粘结层3中形成开口21的同时，在下绝缘膜1的与上布线线路41的连接焊盘部分相对应的部分中形成开口44。下布线线路22的一部分通过开口44连接至上布线线路41的连接焊盘部分。
(第四实施例)
图19是作为本发明第四实施例的半导体器件的截面图。该半导体器件与图1所示的半导体器件的很大不同之处在于：下布线线路具有双层结构。也就是说，第一下布线线路22A的一端通过开口21A连接至半导体结构2的柱状电极13，其中所述第一下布线线路22A设置于第一下绝缘膜1A的下表面上，所述第一开口21A设置于第一下绝缘膜1A和粘结层3中。与第一下绝缘膜1A由相同材料制成的第二下绝缘膜1B设置于第一下布线线路22A的下表面上和第一下绝缘膜1A的下表面上。
第二下布线线路22B的一端通过开口21B连接至第一下布线线路22A的另一端或连接焊盘部分，其中所述第二下布线线路22B设置于第二下绝缘膜1B的下表面上，所述开口21B设置于第二下绝缘膜1B中。下覆盖膜25设置于第二下布线线路22B的下表面上以及第二下绝缘膜1B的下表面上。焊球27设置于下覆盖膜25的开口26中及其下方，使得该焊球连接至第二下布线线路22B的连接焊盘部分。另外，下布线线路可以具有三层或更多层的布线结构。
(第五实施例)
图20示出了作为本发明第五实施例的半导体结构的截面图。该半导体器件与图1所示的半导体器件的很大不同之处在于：包括电阻器、电容器等的芯片部件51通过粘结层52粘着地结合至半导体结构2周围的下绝缘膜1的上表面。在这种情况下，两个或一对下布线线路(连接至柱状电极的下布线线路以及不直接连接至柱状电极的新下布线线路)22中的每一个的一端通过开口53连接至芯片部件51的两个电极54，所述开口53形成在下绝缘膜1和粘结层52中。
(第六实施例)
图21示出了作为本发明第六实施例的半导体器件的截面图。该半导体器件与图18所示的半导体器件的很大不同之处在于：上布线线路41设置于半导体结构2周围的下绝缘膜1的上表面上，而芯片部件51安装在该布线线路的上表面上。芯片部件51的两个电极54通过焊料连接至上布线线路41。在该配置中，下布线线路22被分成连接柱状电极13的部分和设有焊球27的部分(连接焊盘部分)，并且这些部分通过芯片部件51互相电连接。
(第七实施例)
图22示出了作为本发明第七实施例的半导体器件的截面图。该半导体器件与图1所示的半导体器件的不同之处在于：半导体结构2没有设置任何密封膜14。因此，在这种情况下，半导体结构2的布线线路10的下表面、柱状电极13的下表面以及保护膜8的下表面通过电绝缘粘结层3粘着地结合至下绝缘膜1的上表面的中央。结果，布线线路10和柱状电极13覆盖有粘结层3。下布线线路22的一端通过下绝缘膜1和粘结层3中的开口21连接至半导体结构2的柱状电极13。
(第八实施例)
图23示出了作为本发明第八实施例的半导体器件的截面图。该半导体器件与图22所示的半导体器件的不同之处在于：半导体结构2没有设置任何柱状电极13。因此，与图22的器件一样，半导体结构2的布线线路10的下表面和保护膜8的下表面通过粘结层3粘着地结合至下绝缘膜1的上表面的中央。每个布线线路22的一端或内侧端通过下绝缘膜1和粘结层3中的开口21电连接至半导体结构2的布线线路10的连接焊盘部分(外部连接电极)。
(第九实施例)
图24示出了作为本发明第九实施例的半导体器件的截面图。该半导体器件与图23所示的半导体器件的不同之处在于：半导体结构2具有抗静电保护膜或层61，所述抗静电保护膜或层61由诸如聚酰亚胺树脂或环氧树脂的绝缘材料制成并设置于半导体结构2的布线线路10的下表面以及保护膜8的下表面上。保护膜61的下表面通过粘结层3粘着地结合至下绝缘膜1的上表面的中央。此外，各下布线线路22的一端通过下绝缘膜1、粘结层3以及保护膜61中的开口21电连接至半导体结构2的布线线路10的连接焊盘部分。
在半导体结构2安装到下绝缘膜1上之前在保护膜61中不形成开口21。因而，没有开口21的保护膜61保护形成在硅衬底4下面的集成电路，使其从在晶圆状态下在硅衬底4下面已经形成保护膜61的点到半导体结构2被安装到下绝缘膜1上的点的过程中免受静电。
本领域的技术人员将很容易地想到其他优点和变型。因此，本发明的较宽的方面不限于本文所示出和描述的特定细节和代表性实施例。因此，在不脱离所附权利要求及其等价物所限定的总体发明构思的精神或范围的情况下可以做出各种修改。

Claims (23)

1、一种半导体器件，包括：
半导体结构(2)，包括半导体衬底(4)和多个设置于所述半导体衬底下方的外部连接电极(13)；
下绝缘膜(1)，设置于所述半导体结构的下方和外侧；
密封膜(28)，设置于所述下绝缘膜上，以覆盖所述半导体结构的外围；以及
多个下布线线路(22)，设置于所述下绝缘膜下方且分别连接至所述半导体结构的所述外部连接电极。
2、根据权利要求1所述的半导体器件，其中所述半导体结构通过粘结层(3)结合在所述下绝缘膜的中央区域上。
3、根据权利要求1所述的半导体器件，还包括下覆盖膜(25)，所述下覆盖膜(25)设置于所述下布线线路的下方和所述下绝缘膜的下方，并且所述下覆盖膜(25)在与所述下布线线路的连接焊盘部分相对应的部分中具有开口(26)。
4、根据权利要求3所述的半导体器件，还包括多个设置于所述下覆盖膜的所述开口中及其下方的焊球(27)，使得所述焊球分别电连接至所述下布线线路的所述连接焊盘部分。
5、根据权利要求1所述的半导体器件，其中所述密封膜(28)覆盖所述半导体结构的所述半导体衬底的上表面。
6、根据权利要求1所述的半导体器件，其中所述下布线线路中的每一个具有多层结构。
7、根据权利要求1所述的半导体器件，还包括至少一个上布线线路(41)，所述上布线线路(41)设置于所述半导体结构周围的所述下绝缘膜(1)的上表面上，使得所述上布线线路连接至所述下布线线路。
8、根据权利要求7所述的半导体器件，还包括设置于所述上布线线路上的芯片部件(51)。
9、根据权利要求1所述的半导体器件，还包括至少一个芯片部件，所述芯片部件设置于所述下绝缘膜(1)上，使得所述芯片部件连接至所述下布线线路。
10、根据权利要求9所述的半导体器件，其中所述芯片部件通过粘结层粘着地结合在所述下绝缘膜上。
11、根据权利要求1至10中的任意一项所述的半导体器件，其中所述半导体结构(2)包括密封膜(14)，该密封膜(14)设置在所述半导体衬底下方的所述外部连接电极(13)周围。
12、根据权利要求1至10中的任意一项所述的半导体器件，其中所述半导体结构(2)包括粘结层(3)，该粘结层(3)设置在所述半导体衬底下方的所述外部连接电极周围。
13、一种半导体器件制造方法，包括下列步骤：
提供具有基板(13)和下绝缘膜(1)的基底衬底；
在所述下绝缘膜上固定多个半导体结构(2)，所述半导体结构(2)中的每一个包括半导体衬底(4)和多个设置于所述半导体衬底下方的外部连接电极(13)；
在所述下绝缘膜上形成覆盖所述半导体结构的外围的密封膜(28)；
从所述下绝缘膜(1)上去除所述基板；
在所述下绝缘膜下方形成多个下布线线路(22)，使得所述下布线线路中的每一个连接至每一个所述半导体结构的每一个所述外部连接电极；以及
切割在所述半导体结构之间的所述下绝缘膜和所述密封膜，以获得多个半导体器件。
14、根据权利要求13所述的半导体器件制造方法，其中在所述下绝缘膜上固定所述多个半导体结构的所述步骤包括如下子步骤：将粘结层(3)预先提供到所述下绝缘膜上，以及将所述半导体结构热压到所述下绝缘膜上。
15、根据权利要求13所述的半导体器件制造方法，其中在所述下绝缘膜上固定所述半导体结构的所述步骤包括如下子步骤：将粘结片预先提供到所述下绝缘膜上，以及将所述半导体结构热压到所述下绝缘膜上。
16、根据权利要求13所述的半导体器件制造方法，还包括如下步骤：在形成所述下布线线路之前，在所述下绝缘膜和粘结层的与所述半导体结构的所述外部连接电极相对应的部分中形成开口(21)，其中所述粘结层用于将所述半导体结构(2)固定在所述下绝缘膜上。
17、根据权利要求13所述的半导体器件制造方法，其中所述基底衬底包括金属层、保护金属层(35)以及第一基础金属层(23a)，并且所述下绝缘膜(1)形成在所述第一基础金属层上，并且
去除所述基板的所述步骤包括去除除了所述第一基础金属层之外的任意层的步骤。
18、根据权利要求17所述的半导体器件制造方法，其中在形成所述下绝缘膜之前，对所述第一基础金属层的上表面(23a1)进行粗糙化，并通过含有树脂的材料形成所述下绝缘膜。
19、根据权利要求18所述的半导体器件制造方法，还包括如下步骤：在去除除了所述基底衬底的所述第一基础金属层之外的任意层之后，在所述第一基础金属层、所述下绝缘膜以及粘结层的与所述半导体结构的所述外部连接电极相对应的部分中形成开口(21)，其中所述粘结层用于将所述半导体结构(2)固定在所述下绝缘膜上。
20、根据权利要求19所述的半导体器件制造方法，其中形成所述多个下布线线路(22)的所述步骤包括在所述第一基础金属层中的每一层上形成第二基础金属层(23b)并通过电解镀覆在所述第二基础金属层上形成上金属层(24)的子步骤；并且所述下布线线路(22)中的每一个具有包括第一和第二基础金属层(23a，23b)以及所述上金属层(24)的三层结构。
21、根据权利要求20所述的半导体器件制造方法，其中所述金属层、所述第一和第二基础金属层以及所述上金属层由铜制成，而所述保护金属层由镍制成。
22、根据权利要求13所述的半导体器件制造方法，其中提供所述基底衬底的所述步骤包括在所述下绝缘膜上的半导体结构安装区域周围形成上布线线路(41)的步骤，并且
在所述下绝缘膜下方形成所述多个下布线线路的所述步骤包括将所述下布线线路连接至所述上布线线路的步骤。
23、根据权利要求13所述的半导体器件制造方法，其中通过模制法来形成所述密封膜(28)。
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CN103579081A (zh) * 2012-07-18 2014-02-12 万国半导体(开曼)股份有限公司 带有芯片尺寸衬底的扇出型半导体器件及制备方法
CN103579081B (zh) * 2012-07-18 2016-03-02 万国半导体(开曼)股份有限公司 带有芯片尺寸衬底的扇出型半导体器件及制备方法
CN105655305A (zh) * 2014-12-01 2016-06-08 英飞凌科技股份有限公司 半导体封装及其制备方法

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KR101084924B1 (ko) 2011-11-17
WO2009020241A1 (en) 2009-02-12
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TWI427755B (zh) 2014-02-21

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