TWI234259B - Method for making an electric circuit device - Google Patents

Method for making an electric circuit device Download PDF

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Publication number
TWI234259B
TWI234259B TW092122326A TW92122326A TWI234259B TW I234259 B TWI234259 B TW I234259B TW 092122326 A TW092122326 A TW 092122326A TW 92122326 A TW92122326 A TW 92122326A TW I234259 B TWI234259 B TW I234259B
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TW
Taiwan
Prior art keywords
conductive
conductive film
layer
manufacturing
aforementioned
Prior art date
Application number
TW092122326A
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English (en)
Other versions
TW200408098A (en
Inventor
Yusuke Igarashi
Noriaki Sakamoto
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
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Filing date
Publication date
Application filed by Sanyo Electric Co, Kanto Sanyo Semiconductors Co filed Critical Sanyo Electric Co
Publication of TW200408098A publication Critical patent/TW200408098A/zh
Application granted granted Critical
Publication of TWI234259B publication Critical patent/TWI234259B/zh

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Description

1234259 坎、發明說明 【發明所屬之技術領域】 本發明係關於一種雷政胜$ >… „ , 电路裝置之製造方法，尤有關於在蝕 刻之製程中，採用隔著作A 在蝕 有邗為阻“（barrier)層之第3導 胰而疊層2片導電膜，之且 、 /、有夕層配線構造之薄型的電路 裝置之製造方法。 ]包路 【先前技術】 近年來’ 1C封裝已進展到捩 〜一 敬則妹用在攜帶機器及小型盥高 岔度構裝機器上，且盆構# ^ ^ ^ y /、门 ^ π /、構裝概念與以往的1C封裝有極大的 不同。在習知之半導體获罢 士 4< p 置之技術上，以絕緣樹脂基板為 例’有採用屬於撓性基板（η 汉、：flexible sheet)之聚亞醯胺 (polyimide )樹脂基板之半導 千V肢政置（例如請參照專利文 獻1 )。 第19圖至第21圖得接用接从甘』 α知才木用撓性基板50作為内插板 (interposer)基板者。另 r在各圖上方所示之圖式係為 平面圖，在下：所示之圖式係為Μ線之剖面圖。 ^百先’在乐19圖所示之撓性基板50上方，己備好以 , σ之銅、冶圖案51。此銅箱圖案5]係由於 所構邊之千導體兀件為電晶體、IC，而使該圖宰有所不同， 但一般而言係形成有銲塾（b〇nd]ngpad)5iA、島（isiand) 5 1B。此外，兀件符號52係為用以從撓性基板5〇之背面 取出電極之開口部，外露出前述mi圖案51。 接下木，此撓性基板50係輸送至黏晶機（die bonder)，且如第2〇圖所示構裝半導體元件η。之後，此 1234259 撓性基板50係輸送至銲 f承娀Q wire bonder)，且藉由今屬 細線54電性連接銲墊5盥 一 田 〆、牛寺月五兀件53之墊部（pad)o .取後’如第21圖（A)所示，在撓性基板 設置封裝樹脂55加以密封。在此，係進行轉注塑形 (transfer 1T10ld)俾使覆蓋 53以及金屬細線54。 導體元件 之俊士口乐2 1圖（B )所示，藉由設置桿錫及輝球等 之連接機構5 6，且诵過程战η, 且通過如錫回流（reflow)爐，隔著開口 部52形成與銲墊51A熔著 狀1干錫5 ό。而且在撓性基 板50中由於半導體元件53形成為矩陣狀，故如第2〇圖所 不被切割分離成一個一個。 係為於撓性基板 此撓性基板5 0， 此外如第2 1圖（c )所示之剖面圖 5〇之兩面形成51Α與51D作為電極者 般係兩面圖案化後再由廠商供給。 (專利文獻） 第2圖） 曰本特開2 0 0 〇 - 1 3 3 6 7 8號公報（第5頁 (發明欲解決之問題） 才木用上述撓性基板50之半導體裝置由於未使用習知 :金屬框，故具有能夠以極小型來實現薄型之封裝構造之 ，點，不過實際上卻僅以設置於撓性基板5G表面之、層銅 =木51來進灯配線。此係由於接性基板極為柔軟，故在 導電膜之圖案形成前後會發生歪扭，且會使所疊層之層間 之位置偏離增大’而產生不適用於多層配線構造上之問 題〇 ]4952 6 1234259 由於欲實現多層配線構造則需有用以抑制基板之歪扭 之支撐強度，故需要將撓性基板50充分增厚到約2⑼从 m ’然此與薄型化目的卻背道而馳。 係於前述之製造裝置，例如在黏晶 (wire bonder)、轉注塑形（transfer 再者，在製造方法中， 機（die bonder )、銲線機 mold )裝置、回流料，輸送撓性基板5()而安裝在稱為 基座（stage )或平台（table )之部分。 “但是構成撓性基板50之基底之絕緣樹脂之厚度，如將 其薄化至50#m左右，使得形成在表面之銅箔圖案Μ之 厚度亦薄化至9至35…寺，將如第22圖所示產生翹曲 而造成輸送性極度惡化，而I，亦具有難以安裝在前述之 基座或平台之缺點。此係由於絕緣樹脂本身非常薄，因而 產^曲’且由於㈣圖案51與絕緣樹脂間之熱膨服係數 差兴而產生的龜曲所致。 此外，開口部52之部分係在塑模（则】d )之際由上 方加壓’故會產生使銲墊51A之周邊朝上翹曲之作用力 也將造成銲墊51A之連接性的惡化。 、^ ^，構成撓性基板50之樹脂材料本身不具彈性， :、、、θ。尤、傳導性混入填充物（⑴心）時則會變硬。在 狀態下如以銲線機進行焊接時，則會在料部分產生裂 卜纟轉/主塑形之際，亦會在模具抵接之部分產 袈痕幻月况係如第22圖所示當在翹曲時更為顯著。 以上所說明之撓性基板50雖係為未在背 P但如^…所示，亦有在撓性基^之背3 1234259 :::極51D之情況。此時，由於電極仙與前述製造農 合古产’或與此製造裝置間之輸送機構之輪送面抵接，故 傷狀態下構成電極，故亦會；:=力由：在具有此損 曰令U為在之後加熱而造成在電 身產生裂痕或是在對主機板進行焊接連接時造成 易谇接性（solderability)降低之問題。 此外’當在撓性基板50之背面設置電極HD時，會 在轉注塑形之際產峰益、、表纺 曰 …、法人基座進行面接觸之問題。此 日守，S撓性基板5 〇如前述所+说丄 a sm ^ &所不知由堅硬的材料形成時，則 由方；电極5 1 D會成為支點， 犀，妫八佔植α 电極51D之周圍為向下方加 土 冒使說性基板50產生裂痕之問題。 本發明人係為解決此種 而將較薄的第i導電膜时厂 权出隔著第3導電膜 層板的解決方案。 、兒膜予以豐層之疊 [發明内容】 本發明之第1特徵為具備： 電膜隔著第3導電膜而疊層之 · 1導電膜與第2導 第]導電膜蝕刻成所期望之圖；：:反之製程；藉由將前述 之製程；利用前述第！導二：形成第1導電配線層 甩θ匕綠層作炎、命 導電膜予以選擇性地去除之萝。·為〜罩而將前述第3 之絕緣基板疊層在第4遂带=王，為將附著有第1絕緣層 、笔月吴而使俞、+、μ 去除前述第3導電膜而露出之第=】絕緣層將藉由 1導電配線層以及篦， 、兔勝表面部、前述第 叹弟J導電膜端面予以受一 將前述第4導電膜蝕 復盖之製程；藉由 U成所期望之圖安、， 口木，以形成第2導電 1234259 配線層之製程；形成多 智連接機構以將前述第 層與前述第2導電配 弟1導電配線 乂尽卞以電性連接掣· 緣層覆蓋前述第2導電配線層 ' 二以第2絕 緣層予以部分去除，以、Ee 、 ’错：财述第2絕 从廷擇性地使前述第2導泰 出而形成露出部之製裎 守电配線層露 也p ’將+導體元件固接在兪、+、 緣層上再將前述半導俨_从t 則述第2絕 月a 70件與前述第2導電配绵息 性連接之製程；以封I抖日t s φ 、、表層予以電 灰Μ月曰層覆蓋前述半導體 程；去除前述第2導電膜 ， 件之製 个包肤以使珂述第3導電膜 之製程；以及在前述第3導 °出於背面 製程。 …錢之預期處形成外部電極之 本發明之第2特徵為：藉由蝕刻到前述第 “ 以微細地形成前述導電配線層。 兔膜， 本發明之第3特徵為：採用僅將前述第 2 丄十 Ϊ 、i^>·、> 4 姓刻之溶液。 本發明之第4特徵為：使用含有氯化銅㈣〜讣】㈣幻或 氯化鐵（ferric chloride)之溶液作為實施前述蝕刻之前述溶 液。
本發明之第5特徵為··藉由電解剝離方式以去除前述 第3導電膜。 I 本發明之第6特徵為：以採用僅蝕釗前述第3導電膜 之溶液之蝕刻來去除前述第3導電膜。 本發明之第7特徵為：前述溶液係為碘系之溶液。 本设明之弟8特徵為：對前述第2導電' 卜之59 絮本發明之第9特徵為、 、1導電膜更厚。 …2導電膜係形成較前述 胪本發明之第10特徵為.、， 句、熱硬化性科 、、·前述絕緣層作达上 匕性树月曰.或感 ‘為熱可塑性樹 本發明之第11 _ 4樹脂。 it ^ 1 & 徵 A . *電膜係糸以如& 今·前述第1導泰… 、、加為以銅為主材料 午兔朕以及前述第2 以銀為主材料夕人 金屬，而前述筮2、皆 柯枓之金屬。 A罘3導電膜則係 本發明之第12特徵 — 由電鎮將前述第3 ^膜邀^前2導電膜為基底，藉 製造前述疊層板。 、A所述第1導電膜予以疊層，來 本發明之第13特徵、，… 成。 ’·珂述豎層板係以壓延接合形 本發明之第丨4特徵為 _ 膜部分與半導體元件以外：箣述硌出且錢覆之第1導電 本發明之第1 5特徵、之电子構件予以電性連接。 (press vacuum)或真空層^刖述絕緣基板係藉由真空壓製 本發明之第16特二聖（VaCUUm】aminate)而形成。 以部分去除。 $為·藉由雷射加工將前述絕緣層予 本發明之第]7特n * 以部分去除。 4 ’’’、:藉由微影製程將前述絕緣層予 本發明之第I 8特料* 攻為··採用前述第2導電居柞炎 之電鍍，在將前述第〗^ 3作為电極 %緣層部分去除之貫通孔卜，、 覆方式堆疊以銅為主之 上 以鍍 义孟屬，且將前述第]導帝dm 前述第2導電配線層予、 今H V电配線層與 卞从連接。 ]() 31^52 1234259 【實施方式】 茲麥照第1圖至第 造方法。 圖以說明本發明之電路裝置之製 本發明的電$ U < 準備第1導電膜與第2導:法，係由下列製程構成： 層板之製程；蕤i 黾膜隔著第3導電膜而疊層之晶 衣彺，错由將前述第 且智之宜 案，以形成第丨導帝 ，电膜蝕刻成所期望之圖 線層作為遮罩而將=程；利用前述第1導電配 程；為將附著有第u ¥電M予以選擇性地去除之製 而使前述第1絕緣：二之絕緣基板疊層在第4導電膜， 第2道+ 、㈢字錯由去除前述第3導+ 0从 弟2導電膜表面部、前、十、糾、弟巧電月吴而露出之 端面予以覆蓋之制 义弟1導電配線層以及第3導電膜 望之圖案，以形：“：由將前述第4導電膜钱刻成所期 機構以將前述第i .首¥電配線層之製程，·形成多層連接 電性連接之製裎；\電配線層與前述第2導電配線層予以 之製程，·藉由將十^ 2絕緣層覆蓋前述第2導電配線層 地使前述第2導弟2絕緣層予以部分去除’以選擇性 導體元件固接在：配：層露出而形成露出部之製程；將半 前述第2導電配^迷弟2絕緣層上再將前述半導體元件與 覆蓋前述半導體灵層予以電性連接之製程’·以封裝樹脂層 述第3導電膜程；去除前述第2導電膜以使前 之預期處形成“Γ奇面之製程；以及在前述第3導電膜 說明。 D電極之製程。以下茲就上述各製程進行 本發日月之I , I枉，如第]圖所示，係在於準備較薄 1234259 之第1導電膜11與較厚之箓 _ V電膜12隔著第3導#瞪 而豎層之疊層板1 〇之製程。 今电月莫 β層板10之表面，係實皙 η 貝上於全區域形成第1導命t 11，且隔著第3導電膜13，在北 v兒朕 乐2 $黾膜12者。此外，第 一 ^成 19 ^ 昂1導電膜11以及第2導带日“ 12係以Cu為主材料，或 V电胰 # # — 知之導線架之材料構成者兔 較锃。弟1導電膜i丨、第2 者為 ^ v冤馭1 2以及第3導雷肢，0 係可猎由鍍覆法、蒸著法或 包胰b p, 、乂鍍法而形成，或亦可以是為 貼精由壓延法或鍍覆法而形 疋黏 胺1 1 孟屬謂。另外’以第1導
包腰Π以及第2導電膜12而^ V χπ X , 5 ，亦可以是 Al、Fe、Fe Νι、么知之導線架材等。/ 第3導電膜13之材料，在# a 2 ^ /、铋用在去除第1導電膜11 从及弟2導電膜12之際，不合 刻之枯4:1 L L ㈢破使用於該際之蝕刻液所蝕 到之材枓。此外，由於在第3道 挪 箄所馗士 ’兔膜1 3背面係形成由銲錫 寻所構成之外部電極24，故 干物 痺予以# + 才衣外部電極24之附著性亦 ;用2慮。具體而言，以第3導電模W而言係可 木金、銀、纪（palladium)所構成之導電材料。 =導電膜之厚度係形成較薄俾形成微細的圖案，其 子又马5至3 5 // m程度。第2導泰门 ^^陪a V兔圖案係形成較尽俾以機 竹八支撐整體，其厚度為70至2 〇〇 分。篦。道十 1 . . , υ〇“ m程度。弟J導電膜 J ，丁、比餘刻第1導電膜11以及第 .1 ? ^ ^ ^ m 捽 2導電膜12之際作用成 田層’其厚度為1至ΙΟ/im程度。 5“本發明之特徵係在於將第2導電膜]2形成為較第] 于讀]I更厚。帛]導電膜之厚度係應考慮形成為5至
:]49Y 12 山 4259 J 5 // πι程片 ㈣叫。=盡可能的薄化而能形成精細圖安（f· …弟2導電膜12之厚度則以70δ, (w 土 ，以使其具有支掉強度為重點。 。〜m程度為 板W之平將第2導電膜]2形成較厚，即可好田声 再者，由且可提升之後製程之作業性。 e 於弟2導電膜12係經過夂 厚的第2導電膜12由於在之播/衣程而損傷。但 :屬於完成品之電路裝置上殘留傷：製程去除，故可防止 坦性邊將封裝樹脂硬化，故 由於可邊維持 :，且可使形成在疊層板1〇f面之夕亦得以平 置。是龄，2 卜4电極亦可平坦地配 極，防止&接構I基板上之電極與疊層板10背面之電 防止銲錫不良。 月®之包 /、人祕就上述之疊声4 明。疊層I。係可藉由;；二具體製造方法進行說 造。 1方式之豐層或是壓延接合來製 n二由嶋製造疊層板10時，首先應準備第2導電膜 來疊 ¥ ^ 12之^設置電極，藉由電銀法 導曰朕。之後再同樣藉由電鍍法，來疊層第1 第3導電膜上。在藉由壓延製造疊層板時，則藉 導帝^機（r。1161")等施以熱與壓力來將備用為板狀之第1 _ :1、第2導電膜12以及第3導電膜13予以接合。 於浐t 4明之弟2製程’如第2圖以及第3圖所示，係在 配：弟1導電膜11蝕刻成所期望之圖案，以形成第1導電 配線層]]A之製*。 ‘]導电版】1上以所期望之圖案之光阻PR覆蓋， 坨34259 以9由化料刻而將形成銲塾及配線之導電g己崎； M形成。士从# ,, $电配線層〗】Α予 t ;弟I導電膜11係為以Cu為主材粗去 刻液係以採用氯化鐵或氯化銅即可。雖”：：者， 電膜u， ΡΊ雖知秸由蝕刻第】導 導-膣 “ 3 ¥電膜I3亦接觸蝕刻液，但由於第3 3導 之材料不會被氯化鐵以及氯化銅所叫故在第 、電膜13之表面姓刻將停止。由此，由於第二… 之厚度形成為……度，故第…二广電膜11 形成為U 〒役敌弟1 ^电配線層11Α可 随PR^/mj"下之精細圖案。此外，如第3圖所示，光 ^在形成第i導電配線層11A之後被去除。 製程t發:二特徵係在於:在將第1導電膜U予以姓刻之 刻之第i Λ弟3導電膜13使靖止。在本製程中被姓 八本 11主要係以Cu所形成，以將Cu予以π =之_液而言，繼氣化鐵或氯化銅。相對於此。， 膜Η由於係由不會被氯化鐵或氯化銅餘刻之導電 从/斤形成，故姓刻會在第3導電膜13之表面停止。以 卑J導電膜1 3之材料而言係可採用金、銀以及免。 電配=二Π程如第4圖所示，係在於採用第1導 層11A作為遮罩而將第3導電膜13予以去除。 導」木用由w製程中所形成之第1導電膜]1所構成之第i 予：Γ二層11A作為遮罩’而將第3導電膜13選擇性地 广將第3導電膜13選擇性地予以^余之方法而 電：]:之用r::而方法。…方法係為採用僅去除第3導 到離而僅/ 刻之方法。第2個方法係藉由電解 隹而僅去除第3導電膜Π,之方法。 Η 1234259 么么δ兒明错由第1 ^ •膜13之方丰 彳法之蝕刻方式以部分去除第3導 3導電膜η “ ^ 吏用之蝕刻液係採用會對於第 、 Χ且不會對第1導電配線層1 1Α以&第2 導電膜12蝕刻者。々以山 Μ以及弟2 導電膜U係為以Cu為°主^ 1導電配線層UAW及第2 係為Ag膜之時，則夢由使二：料形成，且第3導電膜13 、曰使用夂、糸之钱刻液即可僅去3 導電膜13。雖然藉由崎3導電膜η,使第2去導？膜 12與碘系之蝕刻洛桩縐/ 弟2 ν电Μ 12不會被f之： 例如由Μ成之第2導電膜 2導電膜乙表=T。因此’在…刻將在第 在此製程之後再 =去止除在此，第2圖之…，亦可 么么说明藉由第9古 田弟2方法之電解剝離，來僅去除第3導電 滕1J之方法。首务，〆么 + Τ'使包含金屬離子之溶液與第3導電 胲1 3接觸。然後在溶液一带 1 0 f i ή6 ^ , 方δ又置正的琶極，並在疊層板 、、黾極而使直流電流流動。 藉由電解法所形成…相…動错此方式，即可以與 +成鍍设胲相反之原理，僅將第3導電膜13 予以舌除。名，卜卜％ & m #。道命· 之/谷液係為於鍍覆處理之際用以構 成笫電膜 導電膜"予以剝離4者。因此，以此方法可僅將第3 弟5圖’本發明之第4製程係在於將附著有第 、吧、·.象層15之絕緣基板9予以疊層在第4導電膜 ， 俾使第1絕綾屏Ί 4；受## 、. ^ a 彳旻盍弟1導電配線層11A以及第3導 電膜1 3。 *
從蒼^弟5圖，第3導電膜]3、第1導電配線層n A 1234259 以及部分露出之第2導電膜12表面係由第1絕緣層1 5所 覆蓋。具體而言，被部分去除之第3導電膜1 3之側面以及 第1導電配線層11A之上面以及側面（端面）為由第1絕 緣層15所覆蓋。此外，部分露出之第2導電膜12之表面 亦由第1絕緣層1 5所覆蓋。藉由本製程之絕緣基板9之覆 蓋，係可藉由真空壓製或層壓之方法來實施。真空壓製係 為將絕緣基板9予以重疊在疊層板1 0而以真空方式予以壓 #製之方法，其可一次處理複數片之疊層板1 〇。而藉由層壓 之方法，則係為採用壓延機來使絕緣基板9疊層之方法。 在藉由層壓之方法上，雖然二次硬化（after cure )之製程 係以批次處理在其他製程中進行，但卻具有可精密控制厚 度之優點。此外，亦可以上述方法而僅將第1絕緣層15 予以形成之後，藉由無電解鍍覆以及電鍍來形成第4導電 膜14。 本發明之第5製程係在於如第6圖以及第7圖所示， 馨藉由將第4導電膜1 4蝕刻成所期望之圖案以形成第2導電 配線層14A。 茲參照第6圖，其係藉由蝕刻製程將第4導電膜14 予以部分去除，來形成第2導電配線層14 A。由於第4導 電膜]4係形成較薄，蝕刻在第1絕緣層停止，故可微細地 形成第2導電配線層1 4 A。在此，第4導電膜1 4之厚度係 形成為5至3 5 " ηι程度，故第2導電配線層1 4 A可形成為 5 Ο μ m以下之精細圖案。 其次，參照第7圖，其係藉由形成貫通孔16，將第1 1234259 導電配線層1 1A予以邱八十t 於各 4分露出。形成此貫通孔16之部分， “在形成第2導電配時思 導恭t 、泉層14A之時，同時藉由蝕刻將第4 等％月吴14予以去除。山 ”由於第2導電配線層14A係以Cu為 岁“^者，故㈣液採用氯化鐵或氯化銅來進行化學钱 貝通孔16之開°禋雖係由於光微影之解像度而產生變 化，但在此係為5〇至1〇f) j由 艾 〇〇 β m程度。此外，在此蝕刻之際， 弟2導電膜4係以接 f生之基板寺復盍而免於被蝕刻液蝕 ^ °但是如果第2導雷 -^ ^ 胰4本身為相§厚，而在蝕刻後亦 、准持平坦性之膜厚時，則g卩栋躺黏m w 士 μ 才則即使釉稍被蝕刻亦無妨。另外， 弟2導電配線層1 4 Α而士 nV -r、，a 而5亦可以疋A1、Fe、Fe-Ni、公 知的導線架材等。 成'广接下來，在去除光阻之後，將第2導電配線層14A作 ::罩’藉由雷射將貫通孔丨6正下方之第"邑緣層”予 二除，且使第1導電配線層UA之表面露出在貫通孔Μ 、“卜以雷射而言係以二氧化碳雷射為較佳。此外，在 以每射將絕緣樹脂基發夕你 …毛之後如在開口部之底部留有殘渣 寸則以南廷酸碳酸納（permanean i p g y , # , 、P anganiCac】ds〇da)或過硫酸 ^(㈣—請㈣物㈠等予以濕式㈣，將此殘造去 I示〇 另外’在本製程中當第2導電配線層i 4 A厚度在】〇 以下時’則在以光阻將貫通孔16以外予以覆蓋之後， 即可以二氧化碳雷射將第2導電配線層！4A以及第]絕緣 層^ —次進行處理而形成貫通孔16。此時，需預先進行 使第2導龟配線層]4 A之表面粗化之黑化處理製程。 1234259 本發明之第6製程如第 / 接機構1 7，並電性連 厅不’係在於形成多層ϋ 線層14Α。 * 1導電配線層ηΑ與第2導電配 於包含貫通孔丨6之第〗1 + 作為多層連接機構！ 7之 導电配線層1 1A整面，形成 以進行第2導電配線層14：；1膜/該多層連接機構17為用 連接。此鍵覆膜係可以血電電配線層-之電性 此，係藉由採用第2導電膜“覆與電鑛之兩方形成，在 覆膜到第2導電配線層」作為電極之電鍍，來形成鍍 態。此時，係以抗钱劑加以保=上面辛連接成平坦的狀 導電膜12以及鍍覆電彳 又使鍍覆不要附著在第2 入观復包極取出部以匕 夹具圍起表面鍍覆部之邻 β面。此抗蝕劑在以 貫通孔由二：Ϊ具鐘覆上並不需要。據此， φ 形成多層連接機構1 7。此外，奸 復膜在此雖係採用CU，作亦可 1 1一刀 了抓用 Au、Ag、Pd 等。/ 本發明之第7製程如第9圖所示，係在 層18覆蓋第2導電配線層14八。 弟、巴、*象 月匕其，參照第9圖’第2絕緣層18之覆蓋，係'可藉由將樹 基板t以真空壓製或層壓之方法來進行，或亦可藉由印 (rollcoater) (DipCoater) it 方法上 行塗佈液狀樹脂。真空壓製係為重疊由熱硬化性樹脂所構 成之預浸材料基板（prepreg 而可以真空壓製之方法，一 次將複數片之疊層板1〇進行處理。藉由層壓之方法係採用 滾筒將疊層板10 —片一片她接著熱硬化性樹脂基板◦在此 二次硬化（after cure )之製程雖係藉由批次處理 18 1234259 在其他製程中谁 點。此’但具有可高精密度地控制厚度之優 :科脂係以各方法塗佈之後進行乾燥處理。 除第如第1〇圖所示，係在於藉由物 而形成露”。擇性地使第2導電配線層14Α露注 絲寥知、第1 〇圖’為了與定 之半導妒_从 和皇々、弟2絕緣層1 8 J： 干蜍植兀件19進行電性連 分去除以使第將弟”巴緣層18予以新 弟- ¥电配線層1 4 Α露出。所f山 — 配線層HA係為構成銲墊 。出之弟2導電 感光性之材粗⑼ δ弟2絕緣層U為由 ^ 材科所構成時，可藉公知之微f彡|y ~ 緣“予以部分地去除。此外，亦可，：：:二弟2絕 層1 8予以邱八# 土人 9由田射將弟2絕緣 佳。此外1=除了雷射而言係以二氧化碳雷射為較 部之底部留有殘渔時，則以高鏟酸碳酸二之如在開口 以W將此殘渣去除。4鋼或過硫酸胺等予 上广欠，在露出成為銲墊之第2導電配線層 上形成鑛覆層21。鐘覆層21之形成係 二之表面 覆法或電鐘法來使金或銀附著之方式進:錯=電解鑛 以無電解鐘覆法來形膜。 在本發明中係 本發明之第9製程如帛！}圖所 件19固接在第2絕緣層上，而電性連導體元 與第2導電配線層]4A。 丨生連接切體元件19 半導體元件]9俜在娌s ΰ此能丁 點…。 稞曰曰片狀恶下以絕緣性黏著樹脂 在弟2絕緣層]8上。半導體元件Μ與該下方之第2 ]9 2 1234259 ’故第 由配線 導電配線層】4A係以第2絕緣層18作電性絕緣 導電配線層MA在半導體元件19之下古介π — 7心卜方亦可自 貫現多層配線構造。 %他蛩部係μ砰碎 在屬於第2導電配線層14Α之—部分之銲墊…連接 19亦可以面朝下（faced〇Wn)方式來構裝。此哼導體-件 導體70件19之各電極墊部表面設置銲球及凸塊（/於+ 在疊層板1G之表面則在與銲球位置相對應、了）， 由筮？道帝；ϊΚυΛώθ · 刀，设置* ¥电配線層14Α所構成之銲墊同樣之電極。 此外，半導體元件
纽對方;才木用打線接合之時的疊層板1〇之優點進行 明一般而言在進行Au、線之打線接合之際，係加敎至;
f I此時’當第2導電膜12較薄時，則疊層板^ 、過曲’在此狀態下如隔著銲墊對疊層板10加壓，則疊； 板10會產生損傷之可能性。但是，如果將第2導電膜12 本身形成較厚，即可解決此等問題。 、 本毛明之第1 〇製程如第丨2圖所示，係在於以封裝樹 脂層22覆蓋半導體元件19。 、且層板1 0係設定在塑模裝置而進行樹脂塑模。以塑模 ^ ° 可以疋轉/主塑形射出成形、塗佈、浸潰等。但 是，如考慮量產*時，貝以轉注塑形、#出成形較為適合。 在本製程中’疊層板10雖需平坦地抵接至模穴之下模 =，但較厚的第2導電m可發揮此作用。而且在從模 狀士出之後亦由第2導電膜1 2維持封裝之平坦性直到封 、ί知層]j之收縮先全終了。換言之，至本製程前的疊層 l234259 i〇之機械性支樓之作用係由 十本發明之第U製程如第13圖所干二12擔任。 "取】2去除而使苐3導電膜】3露出在背:在於將弟㈠ 不採用遮罩而對於第2導電膜 去除。此蝕刻可以Θ ^ 仃蝕刻以使其全面 蝕幻了以疋採用氯化鐵或 第2導電膜12人％山 "銅之化學蝕刻，使 艇！2全面地去除。第2 便 除，即可使第3導電膜13 ώ 7 胰12猎由此全面去 于甩勝1 ·3由弟i絕緣肩 所示，由於第3導電膜丨 曰 路出。如上述 U之溶液_之材 皮…2導電膜 不會被姓刻。 成故在本製程中第3導電膜13 本發明之特徵在於：在藉 之製程中，以第3導電膜W 除弟2導電膜12 以…… 兩阻擋層，使由絕緣層17 及弟3 V电膜1 3所構成之背面 i酋^> 干一地形成。由於第2 V笔膜12係藉由蝕刻全面地 笼 故在蝕刻之最終階段， …電膜13亦與姓刻液接觸。如上述所示，第3 1 3係由不會被對cu所構成之第 ^ 稱成之弟2導電膜12進行蝕刻之氯 千鐵以及氯化銅所姓刻之材料構成。因此，叙刻在第3導 黾膜之下面即停止，故篦3道年时 & 故弟^ V電膜13將發揮作為蝕刻之阻 指層之作用。另外，在本製程之後，係藉由封裝樹脂層22 而以機械式支撐全體。 本發明之第· 12製程如第14圖至第“圖，係在於在第 3導電膜13之所期望處形成外部電極24。 此衿田在Ag之遷移（migration )被視為問題之環 境下使用之際’進行以絕緣基板9覆蓋之前，偏將第3 2] 明259 導電膜13選擇蝕刻而加 第”電膜㈣露出形成外;首先參照第14圖， 溶劑溶解的環氧樹脂# u 24之部分，再對於以 (〇verc〇at)樹脂23覆蓋大/ : 13 :,亚以外覆層 為由感光性材料所構成：二'分。當前述外覆層樹脂23 公知之微影製程來將/外部電極24之部分係可以 除。其次，參照第15圏，辟由:，23予以部分地去 锡膏（solder cream) 曰由#于踢之迴流（㈣倾）或銲 成外部電極24。 ’’以在此露出部分同時形 最後，參照第】6圖， 成為多數的矩陣狀 \ ⑥電路裝置係在疊層板1 〇形 23切割再將該等 夂封切脂層22以及外覆層樹脂 刀綠风各個電路裝置。 在本製程中，由於# 成外部電極24之γ、路在背面之第3導電膜成為形 外部電極24情況；3覆：’故只有在第3導電膜13為 外’藉由不將Cu Α 一喝*重新形成鍍覆層之製程。此 樹脂23切割，即:切割而僅將封裝樹脂層22以及外覆層 割之切割機n分離成各個電路裝置，故可減少進行切 茲參照第17 m _ 具體化的電路裝：次明藉由本發明之製造方法之更為 導電配線層1 4 A ]百先’以貫線所示之圖案係為第2 】1A。第：導㊉’以虛線所示之圖案係為第1導電配線層 半導體元=線層1 4 A係、使銲墊設置在周邊俾使包圍 部之半導體^^分係2段配置方式以對應具有多塾 9。由弟2導電配線層]4A所構成之鋅塾 1234259 係以銲線20與半導體元件1 9所對應之命。 從銲墊使精細圖案之第2導電配線層丨4 a f墊部連接，且 體元件19之下方，再以黑色圓圈所示之八夕多數延伸至半導 來連接第1導電配線層11 A。此外，第丨、^連接機構17
亦可形成精細圖#，且可形成更多的外導兒配線層11 A ..,. °卩電極24。 依據此種構造，即使具有2〇〇以卜批 聲部之本道w - 件，亦能利用第2導電配線層1 4 A之鈐4 ’脰兀 ^ m ^ ,, , μ、、、田圖案而藉多声西己 、、泉構造延伸到已精細圖案化之所期望之〜、 夕層配 11Α，並可由設置在第3導電膜13之外:二¥電配線層 對於外部電路之連接。 私極24來進行 兹參照第1 8圖以說明本發明之另 Φ η^ ^ ^悲之具體化之 兔路裒置1Α。在此，電路裝置1Α係形士、名 導帝而居 少成以虛線所示第2 =电配、.泉層14Α，且在第2導電配線層ΐ4Α上構裝 =兀件19、晶片構件25以及裸電晶體26。以 2言，係可全面採用電阻、電容器、二極體、 動構件與主動構件。此外，所内建之構件相互間係隔= 導電配線層11A或銲線20而電性連接。再者， 體元件19相對應之部位李 一干^ 知形成有第1導電配線層11A， 而可由設置在第3導電膜13 電路之連接。 夕…極“進灯對於外部 [發明之效果] 依據本發明，係在蔣都& ^ 、 ... 在知形成較薄的第1導電膜1]進行巍 d以形成第1導電配線声彳
禮]】A之t程中，藉由設置第3遵 電膜]3作為阻擋層， ^ J 、預疋之深度來使姓刻停止。因 23 1234259 此，藉由將第1導電膜11形成較薄，即具有可將第1導電 配線層1 1 A予以微細形成之優點。再者，由於隔著第1絕 緣層15而使第2導電配線層14 A亦微細形成，故可實現 多層配線。 再且，在藉由從背面之蝕刻來將第2導電膜1 2予以全 面去除之製程中，由於第3導電膜1 3發揮作為阻擋層之作 用，故具有可將絕緣層1 5以及由該層所露出之第3導電膜 •所構成之背面予以平坦地形成之優點。由此，可將屬於完 成品之電路裝置之背面之平坦性提高，故可提高其品質。 【圖式之簡單說明】 第1圖係說明本發明之電路裝置之製造方法之剖面 第2圖係說明本發明之電路裝置象製造方法之剖面 圖。 第3圖係說明本發明之電路裝置之製造方法之剖面 鲁圖。 第4圖係說明本發明之電路裝置之製造方法之剖面 圖。 第5圖係說明本發明之電路裝置之製造方法之剖面 圖。 第6圖係說明本發明之電路裝置之製造方法之剖面 圖。 第7圖係說明本發明之電路裝置之製造方法之剖面 圖。 1234259 第8圖係說明本發明之電路裝置之製造方法之剖面 第9圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 0圖係說明本發明之電路裝置之製造方法之剖面 圖。 第11圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 2圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 3圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 4圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 5圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 6圖係說明本發明之電路裝置之製造方法之剖面 圖。 第1 7圖係說明依據本發明所製造之電路裝置之平面 圖。 第1 8圖係說明依據本發明所製造之電路裝置之平面 圖。 第]9圖係說明習知之半導體裝置之製造方法之圖。 第20圖係說明習知之半導體裝置之製造方法之圖。 1234259 第2 1圖（A )至（C )係說明習知之半導體裝置之製 造方法之圖。 第22圖係說明習知之撓性基板之圖。
9 絕緣基板 10 疊層膜 11 第1導電膜 11A 第1導電配線層 12 第2導電膜 13 第3導電膜 14 第4導電膜 14A 第2導電配線層 15 第1絕緣層 16 貫通孔 17 多層連接機構 18 第2絕緣層 19、53 半導體元件 20 銲線 21 鐘覆層 22 封裝樹脂層 23 外覆層樹脂 24 外部電極 25 晶片構件 26 裸電晶體 50 撓性基板 5 1 銅箔圖案 51 A 銲墊 51B 島 51D 電極 52 開口部 54 金屬細線 55 封裝樹脂 56 連接機構 26 3]4952

Claims (1)

  1. !234259 拾、申請專利範圍： h —種電路裝置之製造方法，其中為具備： 準備第1導電膜與第2墓# t + 層之最…制妒 ¥一著第3導電膜而疊 曰層板之製程； 且 稭由將前述第1導電膜蝕刻 成第1導電配線層之製程；成所一圖案，以形 利用前述第1導電配岣厗 導^ 2 配線層作為遮罩而將前述第3 ¥兒Μ予以選擇性地去除之製程； 罘3 為將附著有第1絕緣層 膜，而使—f篦1 π终昆 、，、'彖基板疊層在第4導電 吏則述弟1、、、巴、.彖層將藉由乂 露出之第2導電膜表面部、除…3導電膜而 3導電膜端面予以覆蓋之製:返弟1導電配線層以及第 藉由將前述第4導雷胺^ W、、 成膂 應：名虫刻成所期望之同安 成弟2導電配線層之製程； Λ差之圖案，以形 形成多層連接機構以蔣1 — 述第2導電配線層予以電生、=弟1導電配線層與前 # 生運接之製程； 以弟2絕緣層覆蓋前述 藉由將前述第2絕緣^ W配線層之製程； 層予以部公本 使w述第2導電配線層 *，以選擇性地 ^ , 。而形成露出部之· 將半導體元件固接在前<衣私， 主it· 丨迷弟2絕緣厚μ +導體元件與前述第2導+帕# 象層上再將前述 程； ％配線層予以電性連接之製 以封裝樹脂層覆蓋前逑半- 方除前述第2.導電朦 衣， 、以使丽述第3導電 $犋路出於屯 314952 27 1234259 面之製程；以及 在前述第3導電滕 s 預期處形出& 程。 成外部電極之壤 2·如申請專利範圍第1項 ^ 只之電路聿晉 藉由蝕刻到前述第3導# ^ 、夏之製造方、本 * ^电畴，以 成，其 配 線層。 ㈤地形成前述導 3·如申請專利範圍第1項之電路裝置制 採用僅將前述第1導電膜+、1 之製造方法，复， 、丁以餘刻 -、 .如申請專利範圍第3項之| 。 兒路裝置之勢！ 使用含有氯化銅或氯化鐵 、&方法，其t 珂述溶液。 焉知月|J述蝕刻 5·如申請專利範圍第1項之雷 t 电路裝置之制、止‘ 6 :φ 由電解剝離方式以去除前述第3導：；方m ‘如申請專利範圍第丨項之 ：广 >以採用僅蝕刻前述第3導、之衣造方法，其中 7述第3導電膜。 讀之溶液之蝕刻來去㈣ 女申蜻專利範圍筮 # 弟6項之電路梦署、 IJ圮溶液係為 、 衣造方法，其中 8·如申1南 ，、不之溶液。 τ %專利範圍笑】s 野前述第2導，：項之電路裝置之製造方法，其中 9 ·如申兮主 电杲予以全面韻刻。 乂 Μ專利範圍第1 5 則述第2導電膜 > 項之電路裝置之製造方法，其中 1〇·如申請專利二形成較前述第1導電膜更厚。 前述絶緣層^ ^ f ]項之電路裝置之製造方法，其中， 可塑性樹脂、熱硬化性樹脂或感光性 31^952 28 1234259 樹脂。 1 1 ·如申請專利範圍第1項之電路裝置之製造方法，其中， 前述第1導電膜以及前述第2導電膜係為以銅為主材料 之金屬，而前述第3導電膜則係以銀為主材料之金屬。
    12·如申請專利範圍第1項之電路裝置之製造方法，其中， 以前述第2導電膜為基底，藉由電鍍將前述第3導電膜 與前述第1導電膜予以疊層，來製造前述疊層板。 1 3 ·如申請專利範圍第1項之電路裝置之製造方法，其中， 前述疊層板係以壓延接合形成。 14·如申請專利範圍第1項之電路裝置之製造方法，其中， 將前述露出且鍍覆之第1導電膜部分與半導體元件以 外之電子構件予以電性連接。 15·如申請專利範圍第1項之電路裝置之製造方法，其中， 前述絕緣基板係藉由真空壓製或真空層壓而形成。
    16·如申請專利範圍第1項之電路裝置之製造方法，其中， 藉由雷射加工將前述絕緣層予以部分去除。 17·如申請專利範圍第1項之電路裝置之製造方法，其中， 藉由微影製程將前述絕緣層予以部分去除。 1 8·如申請專利範圍第1項之電路裝置之製造方法，其中， 採用前述第2導電層作為電極之電鐘’在將前述第1絕 緣層部分去除之貫通孔上，以鍍覆方式堆疊以銅為主之 金屬，且將前述第.1導電配線層與前述第2導電配線層 予以連接。 29
TW092122326A 2002-09-26 2003-08-14 Method for making an electric circuit device TWI234259B (en)

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