WO2024007412A1 - 半导体封装组件及制备方法 - Google Patents

半导体封装组件及制备方法 Download PDF

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Publication number
WO2024007412A1
WO2024007412A1 PCT/CN2022/110774 CN2022110774W WO2024007412A1 WO 2024007412 A1 WO2024007412 A1 WO 2024007412A1 CN 2022110774 W CN2022110774 W CN 2022110774W WO 2024007412 A1 WO2024007412 A1 WO 2024007412A1
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Prior art keywords
substrate
interconnection
interposer
area
layer
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PCT/CN2022/110774
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English (en)
French (fr)
Inventor
孙晓飞
全昌镐
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227040844A priority Critical patent/KR20240007734A/ko
Priority to EP22786873.4A priority patent/EP4325556A1/en
Priority to US17/951,722 priority patent/US20240014188A1/en
Publication of WO2024007412A1 publication Critical patent/WO2024007412A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor packaging component and a preparation method.
  • embodiments of the present disclosure provide a semiconductor packaging component and a manufacturing method.
  • a semiconductor packaging component including:
  • a chip stack structure is located on the substrate, the chip stack structure includes a plurality of chips sequentially stacked in a direction perpendicular to the substrate, and the chip stack structure is electrically connected to the first surface of the substrate;
  • An interposer layer is located on the chip stack structure; the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, and the first interconnection area and The substrates are electrically connected;
  • the molding compound seals the chip stack structure, the interposer and the first side of the substrate, wherein the first interconnection area is not sealed by the molding compound, and the second interconnection An area is sealed by the molding compound and has a predetermined height between a top surface of the molding compound on the second interconnection area and the first interconnection area.
  • it also includes:
  • each chip is electrically connected to the substrate through the first conductive line;
  • the second interconnection area is electrically connected to the substrate through the second conductive lines.
  • the first interconnection area includes a plurality of first pads
  • the second interconnection area includes a plurality of second pads, wherein the number of the second pads is greater than the number of the second pads.
  • the number of the first bonding pads, and the area of the second bonding pad is smaller than the area of the first bonding pad.
  • an included angle between a side wall between the top surface of the molding compound and the first interconnection area and a direction perpendicular to the substrate is a first included angle, and the first included angle is greater than or Equal to 0° and less than 90°.
  • the interposer includes a substrate having an electromagnetic shielding layer therein.
  • the substrate has a first thickness and the interposer has a second thickness in a direction perpendicular to the substrate, wherein the first thickness is greater than the second thickness.
  • it also includes:
  • a second packaging structure the second packaging structure includes a first solder ball, the first solder ball is electrically connected to the first interconnection area, wherein the height of the first solder ball is greater than the preset height .
  • a method for manufacturing a semiconductor packaging component including:
  • a chip stack structure is formed on the substrate, the chip stack structure includes a plurality of chips sequentially stacked in a direction perpendicular to the substrate, and the chip stack structure is electrically connected to the first surface of the substrate;
  • An interposer layer is formed on the chip stack structure, the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, the first interconnection area and The substrates are electrically connected;
  • a molding compound is formed that seals the chip stack structure, the interposer, and the first side of the substrate, wherein the first interconnection area is not sealed by the molding compound, and the second interconnection region is not sealed by the molding compound.
  • the connection area is sealed by the plastic compound, and there is a predetermined height between a top surface of the plastic compound on the second interconnection area and the first interconnection area.
  • forming an interposer on the chip stack structure includes:
  • An interposer is provided, the bottom of the interposer has an adhesion layer, and the interposer is adhered to the chip stack structure through the adhesion layer.
  • it also includes:
  • each chip is electrically connected to the substrate through the first conductive line;
  • a second conductive line is formed; the second interconnection area is electrically connected to the substrate through the second conductive line.
  • it also includes:
  • a plurality of first bonding pads are formed on the first interconnection area, and a plurality of second bonding pads are formed on the second interconnection area, wherein the number of the second bonding pads is greater than the number of the first bonding pads.
  • the number of pads, the area of the second pad is smaller than the area of the first pad.
  • it also includes:
  • a covering layer with the preset height is formed on the first interconnection area of the interposer, and an angle between a side wall of the covering layer and a direction perpendicular to the substrate is a first angle. angle, the first included angle is greater than or equal to 0° and less than 90°.
  • it also includes:
  • a first packaging mold is formed; the surface of the first packaging mold is parallel to the surface of the substrate, and the first packaging mold is located above the covering layer and between the covering layer and the covering layer. There is a certain distance.
  • it also includes:
  • first packaging mold As a mask, form a pre-layer of plastic sealing material that seals the chip stack structure, the interposer layer, the covering layer and the first side of the substrate;
  • the capping layer is removed to expose the first interconnection area.
  • it also includes:
  • Forming a second packaging structure Forming a second packaging structure, forming a first solder ball on the second packaging structure, and electrically connecting the first solder ball to the first interconnection area, wherein the height of the first solder ball is greater than the height of the first solder ball. Describe the default height.
  • the subsequent second packaging structure can be connected to the chip stack structure and the substrate through the first interconnection area on the interposer.
  • chip structures of different types or specifications can be connected. Interconnection makes the combination of different chip structures more flexible.
  • the chip stack structure and the second packaging structure subsequently connected to the chip stack structure are independently packaged, it is easier to perform testing and failure analysis.
  • the second packaging structure can be placed on the first interconnection area within the area surrounded by the plastic compound, thereby reducing The height and dimensions of the overall structure.
  • Figure 1 is a schematic structural diagram of a semiconductor packaging component provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a substrate provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of an interposer provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a semiconductor packaging component provided by another embodiment of the present disclosure.
  • Figure 5 is a schematic flowchart of a method for manufacturing a semiconductor package component provided by the disclosed embodiment
  • 6a to 6i are schematic diagrams of the device structure during the preparation process of the semiconductor package component provided by the embodiment of the present disclosure.
  • 30-interposer layer 31-first interconnection area; 32-second interconnection area; 301-first interconnection surface; 311-first pad; 321-second pad; 33-substrate; 34-intermediary upper insulating dielectric layer; 35-intermediate lower insulating dielectric layer;
  • FIG. 1 is a schematic structural diagram of a semiconductor packaging component provided by an embodiment of the present disclosure.
  • the semiconductor packaging component includes:
  • Substrate 10 said substrate 10 having a first surface 101;
  • a chip stack structure 20 is located on the substrate 10.
  • the chip stack structure 20 includes a plurality of chips 21 sequentially stacked in a direction perpendicular to the substrate 10.
  • the chip stack structure 20 is connected to the first surface of the substrate 10. Electrical connection between 101;
  • the interposer layer 30 is located on the chip stack structure 20; the interposer layer 30 has a first interconnection surface 301, and the first interconnection surface 301 has a first interconnection area 31 and a second interconnection area 32, so The first interconnection region 31 is electrically connected to the substrate 10;
  • Plastic compound 40 the plastic compound 40 seals the chip stack structure 20 , the interposer 30 and the first side 101 of the substrate 10 , wherein the first interconnection area 31 is not covered by the plastic compound 40 Sealing, the second interconnection area 32 is sealed by the plastic encapsulation material 40 , and there is a gap between the top surface 401 of the plastic encapsulation material 40 on the second interconnection area 32 and the first interconnection area 31 Default height h.
  • the subsequent second packaging structure can be connected to the chip stack structure and the substrate through the first interconnection area on the interposer.
  • chip structures of different types or specifications can be connected. Interconnection makes the combination of different chip structures more flexible.
  • the chip stack structure and the second packaging structure subsequently connected to the chip stack structure are independently packaged, it is easier to perform testing and failure analysis.
  • the second packaging structure can be placed on the first interconnection area within the area surrounded by the plastic compound, thereby reducing The height and dimensions of the overall structure.
  • FIG. 2 is a schematic structural diagram of a substrate provided by an embodiment of the present disclosure.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a base substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the base substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the first surface 101 of the substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate.
  • the substrate 10 further includes a second surface 102 , which is the lower surface of the insulating dielectric layer 13 under the substrate.
  • the substrate 10 also includes an on-substrate connection pad 14 located in the insulating dielectric layer 12 on the substrate, an under-substrate connection pad 15 located in the under-substrate insulating dielectric layer 13 , and a substrate 11 extending through the substrate.
  • the substrate connection through hole 16 connects the upper substrate connection pad 14 and the lower substrate connection pad 15 to each other.
  • connection pad 14 on the substrate and the connection pad 15 under the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate connection via 16 may be a through silicon via (TSV).
  • the substrate 10 further includes substrate connection bumps 17, which can electrically connect the semiconductor package assembly to an external device and can receive control signals, power signals and ground for operating the chip stack structure from the external device. At least one of the signals may either receive a data signal to be stored in the chip stack structure from an external device, or may provide data within the chip stack structure to an external device.
  • the substrate connection bumps 17 include electrically conductive material.
  • the substrate connection bumps 17 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only a lower and feasible shape in the embodiment of the present disclosure. The specific implementation of the invention does not constitute a limitation of the present disclosure, and the substrate connection bumps can also be of other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.
  • the substrate 10 further includes a first signal transmission area 110 and a second signal transmission area 120 respectively located on opposite sides of the substrate 10 .
  • the first signal transmission area 110 is electrically connected to the chip stack structure 20
  • the second signal transmission area 120 is electrically connected to the interposer layer 30 .
  • the substrate 10 further includes a third signal transmission area 130 located between the first signal transmission area 110 and the second signal transmission area 120 , and the chip stack structure 20 is located on the third signal transmission area 130 .
  • the chip stack structure 20 includes a plurality of chips 21 sequentially stacked in a direction perpendicular to the substrate 10 .
  • the horizontal area of the semiconductor packaging component can be saved by stacking multiple chips upward in sequence.
  • the chip may be a DRAM chip.
  • FIG. 3 is a schematic structural diagram of an interposer provided by an embodiment of the present disclosure.
  • the interposer layer 30 includes a base 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper surface and lower surface of the base 33 .
  • the substrate 33 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. , it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure, For example, Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. can also be used.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be made of green paint.
  • the base 33 of the interposer 30 has an electromagnetic shielding layer (not shown). By arranging an electromagnetic shielding layer in the base of the interposer, information interference between the second packaging structure and the chip stack structure can be prevented from affecting the operation of the device.
  • the interposer layer 30 includes a first interconnection area 31 and a second interconnection area 32.
  • the first interconnection area 31 includes a plurality of first pads 311, and the second interconnection area 32 includes a plurality of first bonding pads 311.
  • the layout design is relatively fixed, while the second pad carries the interconnection between the second package structure and the substrate, so the layout design is more flexible.
  • the second pads are designed to be larger in number and smaller in area, which can improve signal transmission efficiency.
  • the material of the first bonding pad 311 and the second bonding pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate 10 in a direction perpendicular to the substrate 10 , the substrate 10 has a first thickness, and the interposer 30 has a second thickness, wherein the first thickness is greater than the second thickness.
  • the semiconductor package assembly further includes: a first conductive line 51 through which each chip 21 is electrically connected to the substrate 10 ; a second conductive line 52 .
  • the second interconnection area 32 is electrically connected to the substrate 10 through the second conductive line 52 .
  • the chip 21 has a first connection end 201.
  • the first connection end 201 is located on the same side as the first signal transmission area 110.
  • a first conductive wire 51 is led from the first connection end 201 to on the first transmission area 110 to achieve electrical connection between the chip 21 and the substrate 10 .
  • a second bonding pad 321 is formed on the second interconnection area 32 , and a second conductive line 52 is led from the second bonding pad 321 to the second transmission area 120 to realize the connection between the interposer layer 30 and the electrical connections between substrates 10 .
  • the chip stack structure and the substrate are electrically connected using a wire bonding method, wherein the wire bonding method includes an overhang method and a film on wire (FOW) method.
  • the wire bonding method includes an overhang method and a film on wire (FOW) method.
  • wire bonding is performed using an overhang method.
  • Two adjacent chips 21 are connected through an adhesive film 60.
  • the adhesive film 60 does not cover the first connection end 201 and the first conductive line 51 on the chip 21 below it.
  • the adhesive film 60 The chip 21 on the lower layer is dislocated.
  • a wire-on-wire coating method is used for wire bonding (not shown).
  • a plurality of the chips are aligned in a direction perpendicular to the substrate, and the adhesive film between two adjacent chips covers the first connection end and the first conductive line on the chip below them.
  • leads for electrical connection in the embodiments of the present disclosure is only a lower and feasible implementation method in the embodiments of the present disclosure, and does not constitute a limitation on the present disclosure. Other methods can also be used. Electrical connections, such as hybrid bonding or bump interconnects.
  • an included angle between the side wall between the top surface 401 of the plastic molding compound 40 and the first interconnection area 31 and a direction perpendicular to the substrate 10 is a first included angle.
  • the included angle is greater than or equal to 0° and less than 90°.
  • the angle between the side wall between the top surface 401 of the plastic molding compound 40 and the first interconnection region 31 and the direction perpendicular to the substrate 10 is 0°. , that is, the side wall between the top surface 401 of the plastic molding material 40 and the first interconnection area 31 is perpendicular to the substrate 10 . Setting the side wall of the plastic sealing material into a vertical shape makes the process simpler.
  • the angle between the side wall between the top surface 401 of the plastic molding material 40 and the first interconnection area 31 and the direction perpendicular to the substrate 10 is angle a, where , angle a is greater than 0° and less than 90°.
  • the side walls of the plastic encapsulation material are arranged in a non-vertical shape, so that subsequent interconnection with the second packaging structure can be more convenient.
  • the semiconductor packaging component further includes: a second packaging structure 70 , the second packaging structure 70 includes a first solder ball 71 , the first solder ball 71 and the first interconnection region 31 Electrical connection, wherein the height H of the first solder ball 71 is greater than the preset height h.
  • the second package structure can be tightly connected to the interposer, and at the same time, in the second package After the structure is connected to the interposer, there can be a gap between the second packaging structure and the plastic packaging material. This can increase the heat dissipation efficiency of the controller and reduce the impact of heat on the chip.
  • the second packaging structure 70 further includes a second substrate 72 .
  • the structure of the second substrate 72 may be the same as or different from the structure of the substrate 10 , and will not be described again here.
  • the plastic molding material 40 has a first thickness in a direction perpendicular to the substrate 10 ;
  • the second packaging structure 70 includes a second plastic molding material 73 , and in a direction perpendicular to the substrate 10
  • the second plastic molding material 73 has a second thickness; wherein the first thickness is greater than or equal to the second thickness.
  • the second packaging structure 70 further includes at least one second chip structure (not shown), which is the same or different type as the chip 21 in the chip stack structure 20 .
  • the second packaging structure 70 includes a plurality of stacked second chip structures, and the stacking method of each second chip structure is the same as the stacking method of the chips 21 in the chip stacking structure 20 , through this arrangement, the mechanical adaptability between the second packaging structure 70 and the chip stack structure 20 is improved, and the stability of the package body is improved.
  • the second chip structure may be a universal flash memory chip (Universal File Store, UFS).
  • UFS Universal File Store
  • the semiconductor packaging component provided by the embodiment of the present disclosure can be applied to a multi-chip package (UFS Multi Chip Package, UMCP) with a package on package (Package on Package, PoP) structure.
  • UFS Multi Chip Package UMCP
  • PoP package on Package
  • Embodiments of the present disclosure also provide a method for preparing a semiconductor packaging component. Please refer to FIG. 5 for details. As shown in the figure, the method includes the following steps:
  • Step 501 Provide a substrate, the substrate having a first side;
  • Step 502 Form a chip stack structure on the substrate.
  • the chip stack structure includes a plurality of chips sequentially stacked in a direction perpendicular to the substrate.
  • the chip stack structure is electrically connected to the first surface of the substrate. ;
  • Step 503 Form an interposer layer on the chip stack structure, the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, the first interconnection area electrical connection between the connection area and the substrate;
  • Step 504 Form a molding compound that seals the chip stack structure, the interposer, and the first side of the substrate, wherein the first interconnection area is not sealed by the molding compound, and the The second interconnection area is sealed by the plastic compound, and has a predetermined height between a top surface of the plastic compound on the second interconnection area and the first interconnection area.
  • 6a to 6i are schematic structural diagrams of the semiconductor package component during the preparation process according to embodiments of the present disclosure.
  • step 501 is performed to provide a substrate 10 having a first side 101.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a base substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the base substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the first surface 101 of the substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate.
  • the substrate 10 further includes a second surface 102 , which is the lower surface of the insulating dielectric layer 13 under the substrate.
  • the substrate 10 also includes an on-substrate connection pad 14 located in the insulating dielectric layer 12 on the substrate, an under-substrate connection pad 15 located in the under-substrate insulating dielectric layer 13 , and a substrate 11 extending through the substrate.
  • the substrate connection through hole 16 connects the upper substrate connection pad 14 and the lower substrate connection pad 15 to each other.
  • connection pad 14 on the substrate and the connection pad 15 under the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate connection via 16 may be a through silicon via (TSV).
  • the substrate 10 further includes a first signal transmission area 110 and a second signal transmission area 120 respectively located on opposite sides of the substrate 10 .
  • the first signal transmission area 110 is electrically connected to the subsequently formed chip stack structure 20
  • the second signal transmission area 120 is electrically connected to the subsequently formed interposer 30 .
  • the first signal transmission area 110 and the second signal transmission area 120 are not interconnected.
  • the substrate 10 further includes a third signal transmission area 130 located between the first signal transmission area 110 and the second signal transmission area 120 , and a subsequent chip stack structure 20 is formed on the third signal transmission area 130 .
  • the first signal transmission area 110 and the third signal transmission area 130 are interconnected, and the third signal transmission area 130 and the second signal transmission area 120 are not interconnected.
  • step 502 is performed to form a chip stack structure 20 on the substrate 10.
  • the chip stack structure 20 includes a plurality of chips 21 sequentially stacked in a direction perpendicular to the substrate 10.
  • the chip stack structure 20 is electrically connected to the first surface 101 of the substrate 10 .
  • the horizontal area of the semiconductor package component can be saved.
  • the adhesive film 60 can It's DAF.
  • step 503 is performed to form an interposer 30 on the chip stack structure 20 .
  • the interposer 30 has a first interconnection surface 301
  • the first interconnection surface 301 has a first interconnection surface 301 .
  • the interconnection area 31 and the second interconnection area 32 are electrically connected to the first interconnection area 31 and the substrate 10 .
  • the carrier tape 2 is pasted on the ring 1, and then the adhesive film 60 is pasted on the carrier tape 2, and then the intermediary layer is pasted on the adhesive film 60. At this time, the intermediary layer is the entire piece.
  • the interposer is cut into strips to form units one by one as shown in Figure 6c.
  • a covering layer 80 having a preset height h in a direction perpendicular to the substrate 10 is formed on the first interconnection area 31 of the interposer 30 .
  • the angle between the side wall of the layer 80 and the direction perpendicular to the substrate 10 is a first angle, and the first angle is greater than or equal to 0° and less than 90°.
  • the material of the covering layer may be polyimide, polyester material, polyethylene terephthalate film, etc.
  • the angle between the side wall of the covering layer 80 and the direction perpendicular to the substrate 10 is 0°, and the structure of the formed plastic sealant is as shown in Figure 1.
  • the angle between the side wall of the covering layer and the direction perpendicular to the substrate is greater than 0° and less than 90°, and the structure of the formed plastic packaging material is as shown in Figure 4.
  • the exposure height of the first interconnection area on the interposer layer 30 is set by a cover layer with a preset thickness on the interposer layer 30, so that the design of the preset height of the first interconnection area is more flexible.
  • the use of the cover layer so that there is no need to use a special-shaped packaging mold during plastic packaging, and the first interconnection area can be exposed directly by removing the covering layer, which can reduce costs and make the formation process simpler.
  • the interposer attached to the ring 1 needs to be cleaned to remove impurities and dust to prevent the interposer from being dirty and affecting the performance of the semiconductor package components.
  • an interposer 30 is formed on the chip stack structure 20 .
  • the interposer 30 is separated from the carrier tape 2 , and the interposer 30 is adhered to the chip on the top of the chip stack structure 20 using the adhesive film 60 at the bottom of the interposer 30 .
  • the interposer layer 30 includes a base 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper surface and lower surface of the base 33 .
  • the substrate 33 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. , it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure, For example, Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. can also be used.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be made of green paint.
  • the base 33 of the interposer 30 has an electromagnetic shielding layer (not shown). By arranging an electromagnetic shielding layer in the base of the interposer, information interference between the second packaging structure and the chip stack structure can be prevented from affecting the operation of the device.
  • the method further includes: forming a plurality of first bonding pads 311 on the first interconnection area 31, and forming a plurality of second bonding pads 321 on the second interconnection area 32, wherein , the number of the second bonding pads 321 is greater than the number of the first bonding pads 311 , and the area of the second bonding pad 321 is smaller than the area of the first bonding pad 311 .
  • the layout design is relatively fixed, while the second pad carries the interconnection between the second package structure and the substrate, so the layout design is more flexible.
  • the second pads are designed to be larger in number and smaller in area, which can improve signal transmission efficiency.
  • the first bonding pad 311 and the second bonding pad 321 are located in the upper insulating dielectric layer 34 .
  • the material of the first bonding pad 311 and the second bonding pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate 10 in a direction perpendicular to the substrate 10 , the substrate 10 has a first thickness, and the interposer 30 has a second thickness, wherein the first thickness is greater than the second thickness.
  • the method further includes: after forming the interposer 30,
  • each chip 21 is electrically connected to the substrate 10 through the first conductive line 51;
  • a second conductive line 52 is formed; the second interconnection area 32 is electrically connected to the substrate 10 through the second conductive line 52 .
  • the chip 21 has a first connection terminal 201, which is located on the same side as the first signal transmission area 110, and a first conductive wire 51 is led from the first connection terminal 201 to on the first transmission area 110 to achieve electrical connection between the chip 21 and the substrate 10 .
  • a second bonding pad 321 is formed on the second interconnection area 32 , and a second conductive line 52 is led from the second bonding pad 321 to the second transmission area 120 to realize the connection between the interposer layer 30 and the electrical connections between substrates 10 .
  • the chip stack structure and the substrate are electrically connected using a wire bonding method, wherein the wire bonding method includes an overhang method and a film on wire (FOW) method. .
  • wire bonding is performed using an overhang method.
  • Two adjacent chips 21 are connected through an adhesive film 60.
  • the adhesive film 60 does not cover the first connection end 201 and the first conductive line 51 on the chip 21 below it.
  • the adhesive film 60 The chip 21 on the lower layer is dislocated.
  • a wire-on-wire coating method is used for wire bonding (not shown).
  • a plurality of the chips are aligned in a direction perpendicular to the substrate, and the adhesive film between two adjacent chips covers the first connection end and the first conductive line on the chip below them.
  • step 504 is performed to form a plastic compound 40 that seals the chip stack structure 20, the interposer 30 and the first side 101 of the substrate 10, wherein The first interconnection area 31 is not sealed by the plastic compound 40, the second interconnection area 32 is sealed by the plastic compound 40, and the top of the plastic compound 40 on the second interconnection area 32 There is a preset height h between the surface 401 and the first interconnection area 31 .
  • the method further includes: after forming the covering layer 80, forming a first packaging mold 91; the surface of the first packaging mold 91 is parallel to the surface of the substrate 10, and the first packaging mold 91 is parallel to the surface of the substrate 10.
  • the packaging mold 91 is located above the covering layer 80 and has a certain distance from the covering layer 80 .
  • the method further includes: forming a second packaging mold 92 , the second packaging mold 92 is located below the substrate 10 and parallel to the surface of the substrate 10 .
  • the method further includes: using the first packaging mold 91 as a mask, forming a first sealing layer that seals the chip stack structure 20, the interposer 30, the covering layer 80 and the substrate 10. Pre-layer 400 of plastic sealant on surface 101 .
  • the first packaging mold 91 and the second packaging mold 92 are used as masks to form the plastic sealant pre-layer 400 .
  • the first packaging mold 91 and the second packaging mold 92 are removed.
  • part of the plastic pre-layer 400 is removed to expose the covering layer 80 .
  • a grinding wheel can be used to grind the surface of the plastic sealing material pre-layer 400 to remove part of the plastic sealing material pre-layer 400 to form the plastic sealing material 40 .
  • the molding compound 40 may be EMC.
  • the method further includes removing the pre-layer of plastic sealant under the substrate to expose the second side of the substrate.
  • part of the pre-layer of plastic material on the interposer is removed to expose the cover layer 80 .
  • the covering layer 80 is removed to expose the first interconnection area 31 .
  • the removal of the covering layer 80 includes using a chemical solution to remove the covering layer 80 .
  • the chemical solution used can dissolve the covering layer but does not cause damage to structures such as chips and plastic packaging materials.
  • substrate connection bumps 17 are formed on the second surface 102 of the substrate 10 , and the substrate connection bumps 17 include conductive material.
  • the method further includes: forming a second packaging structure 70, forming a first solder ball 71 on the second packaging structure 70, the first solder ball 71 being connected to the first interconnection area 31 is electrically connected, wherein the height H of the first solder ball 71 is greater than the preset height h.
  • the second package structure can be tightly connected to the interposer, and at the same time, in the second package After the structure is connected to the interposer, there can be a gap between the second packaging structure and the plastic packaging material. This can increase the heat dissipation efficiency of the controller and reduce the impact of heat on the chip.
  • the second packaging structure 70 also includes a second substrate 72.
  • the structure of the second substrate 72 is the same as that of the substrate 10, which will not be described again here.
  • the plastic molding material 40 has a first thickness in a direction perpendicular to the substrate 10 ;
  • the second packaging structure 70 includes a second plastic molding material 73 , and in a direction perpendicular to the substrate 10 above, the second plastic molding material 73 has a second thickness; wherein the first thickness is greater than or equal to the second thickness.
  • the second packaging structure 70 further includes a second chip structure (not shown), which is the same or different type as the chip stack structure 20 .
  • the second chip structure may be a universal flash memory chip (Universal File Store, UFS).
  • UFS Universal File Store
  • the subsequent second packaging structure can be connected to the chip stack structure and the substrate through the first interconnection area on the interposer.
  • chip structures of different types or specifications can be connected. Interconnection makes the combination of different chip structures more flexible.
  • the chip stack structure and the second packaging structure subsequently connected to the chip stack structure are independently packaged, it is easier to perform testing and failure analysis.
  • the second packaging structure can be placed on the first interconnection area within the area surrounded by the plastic compound, thereby reducing The height and dimensions of the overall structure.

Abstract

一种半导体封装组件及制备方法，其中，所述半导体封装组件，包括：基板（10），所述基板（10）具有第一面（101）；芯片堆叠结构（20），位于所述基板（10）上，所述芯片堆叠结构（20）包括沿垂直于所述基板（10）方向依次堆叠的多个芯片（21），所述芯片堆叠结构（20）与所述基板（10）的第一面（101）之间电连接；中介层（30），位于所述芯片堆叠结构（20）上；所述中介层（30）具有第一互连面（301），所述第一互连面（301）具有第一互连区域（31）和第二互连区域（32），所述第二互连区域（32）与所述基板（10）之间电连接；塑封料（40），所述塑封料（40）密封所述芯片堆叠结构（20）、所述中介层（30）和所述基板（10）的第一面（101），所述第一互连区域（31）不被所述塑封料（40）密封，所述第二互连区域（32）被所述塑封料（40）密封，且所述第二互连区域（32）上的所述塑封料（40）的顶表面与所述第一互连区域（31）之间具有预设高度h。

Description

半导体封装组件及制备方法
相关申请的交叉引用
本公开基于申请号为202210806367.7、申请日为2022年07月08日、发明名称为“半导体封装组件及制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体封装组件及制备方法。
背景技术
在所有部门，行业和地区，电子行业都在不断要求提供更轻、更快、更小、多功能、更可靠和更具成本效益的产品。为了满足众多不同消费者的这些不断增长的需求，需要集成更多的电路来提供所需的功能。在几乎所有应用中，对减小尺寸，提高性能和改善集成电路功能的需求不断增长。
发明内容
有鉴于此，本公开实施例提供一种半导体封装组件及制备方法。
根据本公开实施例的第一方面，提供了一种半导体封装组件，包括：
基板，所述基板具有第一面；
芯片堆叠结构，位于所述基板上，所述芯片堆叠结构包括沿垂直于所述基板方向依次堆叠的多个芯片，所述芯片堆叠结构与所述基板的第一面之间电连接；
中介层，位于所述芯片堆叠结构上；所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域与所述基板之间电连接；
塑封料，所述塑封料密封所述芯片堆叠结构、所述中介层和所述基板的第一面，其中，所述第一互连区域不被所述塑封料密封，所述第二互连区域被所述塑封料密封，且所述第二互连区域上的所述塑封料的顶表面与所述第一互连区域之间具有预设高度。
在一些实施例中，还包括：
第一导电线，每个所述芯片通过所述第一导电线与所述基板之间电连 接；
第二导电线，所述第二互连区域通过所述第二导电线与所述基板之间电连接。
在一些实施例中，所述第一互连区域上包括多个第一焊盘，所述第二互连区域上包括多个第二焊盘，其中，所述第二焊盘的数量大于所述第一焊盘的数量，所述第二焊盘的面积小于所述第一焊盘的面积。
在一些实施例中，所述塑封料的顶表面与所述第一互连区域之间的侧壁与垂直于所述基板方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
在一些实施例中，所述中介层包括基底，所述基底内具有电磁屏蔽层。
在一些实施例中，在垂直于所述基板的方向上，所述基板具有第一厚度，所述中介层具有第二厚度，其中，所述第一厚度大于所述第二厚度。
在一些实施例中，还包括：
第二封装结构，所述第二封装结构包括第一焊球，所述第一焊球与所述第一互连区域电连接，其中，所述第一焊球的高度大于所述预设高度。
根据本公开实施例的第二方面，提供了一种半导体封装组件的制备方法，包括：
提供基板，所述基板具有第一面；
在所述基板上形成芯片堆叠结构，所述芯片堆叠结构包括沿垂直于所述基板方向依次堆叠的多个芯片，所述芯片堆叠结构与所述基板的第一面之间电连接；
在所述芯片堆叠结构上形成中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域与所述基板之间电连接；
形成塑封料，所述塑封料密封所述芯片堆叠结构、所述中介层和所述基板的第一面，其中，所述第一互连区域不被所述塑封料密封，所述第二互连区域被所述塑封料密封，且所述第二互连区域上的所述塑封料的顶表面与所述第一互连区域之间具有预设高度。
在一些实施例中，在所述芯片堆叠结构上形成中介层包括：
提供中介层，所述中介层的底部具有粘附层，将所述中介层通过所述粘附层粘附到所述芯片堆叠结构上。
在一些实施例中，还包括：
在形成中介层后，
形成第一导电线；每个所述芯片通过所述第一导电线与所述基板之间电连接；
形成第二导电线；所述第二互连区域通过所述第二导电线与所述基板之间电连接。
在一些实施例中，还包括：
在所述第一互连区域上形成多个第一焊盘，在所述第二互连区域上形成多个第二焊盘，其中，所述第二焊盘的数量大于所述第一焊盘的数量，所述第二焊盘的面积小于所述第一焊盘的面积。
在一些实施例中，还包括：
在形成中介层后，在所述中介层的第一互连区域上形成具有所述预设高度的覆盖层，所述覆盖层的侧壁与垂直于所述基板方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
在一些实施例中，还包括：
在形成覆盖层后，形成第一封装模具；所述第一封装模具的表面平行于所述基板的表面，所述第一封装模具位于所述覆盖层的上方，且与所述覆盖层之间存在一定距离。
在一些实施例中，还包括：
以第一封装模具为掩膜，形成密封所述芯片堆叠结构、所述中介层、所述覆盖层和所述基板的第一面的塑封料预层；
去除部分所述塑封料预层，暴露所述覆盖层；
去除所述覆盖层，暴露所述第一互连区域。
在一些实施例中，还包括：
形成第二封装结构，在所述第二封装结构上形成第一焊球，将所述第一焊球与所述第一互连区域电连接，其中，所述第一焊球的高度大于所述预设高度。
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一互连区域与芯片堆叠结构以及基板连接，如此，可实现不同类型或不同规格的芯片结构之间的互连，使得不同芯片结构之间的组合更加灵活。同时因为芯片堆叠结构和后续与芯片堆叠结构连接的第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。并且由于中介层的第一互连区域与塑封料的顶表面之间存在预设高度，如此，第二封装结构可放置于第一互连区域上，由塑封料围成的区域内，进而减少整体结构的高度和尺寸。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体封装组件的结构示意图；
图2为本公开实施例提供的基板的结构示意图；
图3为本公开实施例提供的中介层的结构示意图；
图4为本公开另一实施例提供的半导体封装组件的结构示意图；
图5为公开实施例提供的半导体封装组件的制备方法的流程示意图；
图6a至图6i为本公开实施例提供的半导体封装组件在制备过程中的器件结构示意图。
附图标记说明：
1-圆环；2-载带；
10-基板；101-第一面；102-第二面；11-基板衬底；12-基板上绝缘介质层；13-基板下绝缘介质层；14-基板上连接焊盘；15-基板下连接焊盘；16-基板连接通孔；17-基板连接凸块；110-第一信号传输区域；120-第二信号传输区域；130-第三信号传输区域；
20-芯片堆叠结构；21-芯片；201-第一连接端；
30-中介层；31-第一互连区域；32-第二互连区域；301-第一互连面；311-第一焊盘；321-第二焊盘；33-基底；34-中介上绝缘介质层；35-中介下绝缘介质层；
40-塑封料；401-顶表面；400-塑封料预层；
51-第一导电线；52-第二导电线；
60-粘附膜；
70-第二封装结构；71-第一焊球；72-第二基板；73-第二塑封料；
80-覆盖层；
91-第一封装模具；92-第二封装模具。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反， 当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
本公开实施例提供了一种半导体封装组件。图1为本公开实施例提供的半导体封装组件的结构示意图。
如图1所示，所述半导体封装组件包括：
基板10，所述基板10具有第一面101；
芯片堆叠结构20，位于所述基板10上，所述芯片堆叠结构20包括沿垂直于所述基板10方向依次堆叠的多个芯片21，所述芯片堆叠结构20与所述基板10的第一面101之间电连接；
中介层30，位于所述芯片堆叠结构20上；所述中介层30具有第一互连面301，所述第一互连面301具有第一互连区域31和第二互连区域32，所述第一互连区域31与所述基板10之间电连接；
塑封料40，所述塑封料40密封所述芯片堆叠结构20、所述中介层30和所述基板10的第一面101，其中，所述第一互连区域31不被所述塑封料40密封，所述第二互连区域32被所述塑封料40密封，且所述第二互连区域32上的所述塑封料40的顶表面401与所述第一互连区域31之间具有预设高度h。
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一互连区域与芯片堆叠结构以及基板连接，如此，可实现不同类型或不同规格的芯片结构之间的互连，使得不同芯片结构之间的组合更加灵活。同时因为芯片堆叠结构和后续与芯片堆叠结构连接的第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。并且由于中介层的第一互连区域与塑封料的顶表面之间存在预设高度，如此，第二封装结构可放置于第一互连区域上，由塑封料围成的区域内，进而减少整体结构的高度和尺寸。
图2为本公开实施例提供的基板的结构示意图。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
如图2所示，所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在本公开实施例中，所述基板10的第一面101即为所述基板上绝缘介质层12的上表面。所述基板10还包括第二面102，即为所述基板下绝缘介质层13的下表面。
所述基板10还包括位于所述基板上绝缘介质层12内的基板上连接焊盘14，位于所述基板下绝缘介质层13内的基板下连接焊盘15，以及贯穿所述基板衬底11并将所述基板上连接焊盘14和所述基板下连接焊盘15彼此连接的基板连接通孔16。
所述基板上连接焊盘14和所述基板下连接焊盘15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述基板连接通孔16可以为穿硅通孔(TSV)。
所述基板10还包括基板连接凸块17，所述基板连接凸块17可将半导 体封装组件电连接到外部装置上，可以从外部装置接收用于操作芯片堆叠结构的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在芯片堆叠结构内的数据信号，也可将芯片堆叠结构内的数据提供给外部装置。
所述基板连接凸块17包括导电材料。在本公开实施例中，所述基板连接凸块17为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
继续参见图2，所述基板10还包括分别位于所述基板10相对的两侧的第一信号传输区域110和第二信号传输区域120。所述第一信号传输区域110与芯片堆叠结构20电连接，所述第二信号传输区域120与所述中介层30电连接。
所述基板10还包括位于所述第一信号传输区域110和第二信号传输区域120之间的第三信号传输区域130，所述芯片堆叠结构20位于所述第三信号传输区域130上。
继续参见图1，所述芯片堆叠结构20包括沿垂直于所述基板10方向依次堆叠的多个芯片21。本实施例中，采用向上依次堆叠多个芯片的方式，可以节省半导体封装组件的水平面积。
在本公开的一个实施例中，所述芯片可以为DRAM芯片。
图3为本公开实施例提供的中介层的结构示意图。
如图3所示，所述中介层30包括基底33和分别设置在所述基底33的上表面和下表面上的中介上绝缘介质层34和中介下绝缘介质层35。
所述基底33可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述中介上绝缘介质层34和所述中介下绝缘介质层35可以为阻焊层，例如所述中介上绝缘介质层34和所述中介下绝缘介质层35的材料可以为绿漆。
在一实施例中，所述中介层30的基底33内具有电磁屏蔽层(未图示)。通过在中介层的基底内设置电磁屏蔽层，可以防止第二封装结构与芯片堆叠结构之间发生信息干扰，影响器件工作。
所述中介层30包括第一互连区域31和第二互连区域32，所述第一互连区域31上包括多个第一焊盘311，所述第二互连区域32上包括多个第二焊盘321，其中，所述第二焊盘321的数量大于所述第一焊盘311的数量， 所述第二焊盘321的面积小于所述第一焊盘311的面积。
因为第一焊盘后续需要与第二封装结构进行匹配互连，因此布局设计相对比较固定，而第二焊盘承载的是第二封装结构与基板的互连，因此布局设计更为灵活，将第二焊盘设计成数量较多，面积较小，可以提高信号传输效率。
所述第一焊盘311和所述第二焊盘321的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。
在一实施例中，在垂直于所述基板10的方向上，所述基板10具有第一厚度，所述中介层30具有第二厚度，其中，所述第一厚度大于所述第二厚度。
继续参见图1，所述半导体封装组件还包括：第一导电线51，每个所述芯片21通过所述第一导电线51与所述基板10之间电连接；第二导电线52，所述第二互连区域32通过所述第二导电线52与所述基板10之间电连接。
具体地，所述芯片21具有第一连接端201，所述第一连接端201与所述第一信号传输区域110位于同一侧，从所述第一连接端201上引出第一导电线51到所述第一传输区域110上，以实现所述芯片21与所述基板10之间的电连接。
所述第二互连区域32上形成有第二焊盘321，从第二焊盘321上引出第二导电线52到所述第二传输区域120上，以实现所述中介层30与所述基板10之间的电连接。
本公开实施例中，所述芯片堆叠结构与所述基板之间采用引线键合方式进行电连接，其中，引线键合方式包括悬垂(Overhang)方式和导线上膜(Film on wire，FOW)方式。
图1所示的实施例中，采用悬垂方式进行引线键合。相邻两个芯片21之间通过粘附膜60连接，所述粘附膜60不覆盖其下方一层的芯片21上的第一连接端201以及第一导电线51，所述粘附膜60与其下方一层的所述芯片21错位设置。
在另一些实施例中，采用导线上膜方式进行引线键合(未图示)。多个所述芯片沿垂直于所述基板的方向对齐设置，相邻两个芯片之间的粘附膜覆盖其下方一层的芯片上的第一连接端以及第一导电线。
可以理解的是，本公开实施例中利用引线的方式进行电连接仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，也可以使用其他方式进行电连接，例如混合键合或者凸块互连。
在一实施例中，所述塑封料40的顶表面401与所述第一互连区域31之间的侧壁与垂直于所述基板10方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
例如，在如图1所示的实施例中，所述塑封料40的顶表面401和所述 第一互连区域31之间的侧壁与垂直于所述基板10方向的夹角为0°，即塑封料40的顶表面401与所述第一互连区域31之间的侧壁垂直于所述基板10。将塑封料的侧壁设置成垂直形状，工艺更加简单。
在如图4所示的实施例中，所述塑封料40的顶表面401和所述第一互连区域31之间的侧壁与垂直于所述基板10方向的夹角为角a，其中，角a大于0°，且小于90°。将塑封料的侧壁设置成非垂直形，如此，可以更加方便后续与第二封装结构的互连。
在一实施例中，所述半导体封装组件还包括：第二封装结构70，所述第二封装结构70包括第一焊球71，所述第一焊球71与所述第一互连区域31电连接，其中，所述第一焊球71的高度H大于所述预设高度h。
本公开实施例中，通过设置第一焊球的高度大于塑封料的顶表面与第一互连区域之间的高度，可以使得第二封装结构能够与中介层紧密连接，同时，在第二封装结构与中介层连接后，第二封装结构与塑封料之间能存在空隙，如此，能增加控制器散热效率，减小热量对芯片的影响。
所述第二封装结构70还包括第二基板72，所述第二基板72的结构与所述基板10的结构可以相同，也可以不同，这里不再赘述。
在一实施例中，在垂直于所述基板10的方向上，所述塑封料40具有第一厚度；所述第二封装结构70包括第二塑封料73，在垂直于所述基板10的方向上，所述第二塑封料73具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
所述第二封装结构70还包括至少一个第二芯片结构(未图示)，所述第二芯片结构与所述芯片堆叠结构20中的芯片21的类型相同或不同。
在本公开的一个实施例中，所述第二封装结构70中包括多个堆叠的第二芯片结构，各个第二芯片结构的堆叠方式与所述芯片堆叠结构20中的芯片21的堆叠方式相同，通过这种设置，提高第二封装结构70与芯片堆叠结构20之间的机械适配性，提高封装体的稳定性。
例如，所述第二芯片结构可以为通用闪存存储芯片(Universal File Store，UFS)。
本公开实施例提供的半导体封装组件可应用于叠层封装(Package on Package，PoP)结构的多芯片封装(UFS Multi Chip Package，UMCP)。
本公开实施例还提供了一种半导体封装组件的制备方法，具体请参见附图5，如图所示，所述方法包括以下步骤：
步骤501：提供基板，所述基板具有第一面；
步骤502：在所述基板上形成芯片堆叠结构，所述芯片堆叠结构包括沿垂直于所述基板方向依次堆叠的多个芯片，所述芯片堆叠结构与所述基板的第一面之间电连接；
步骤503：在所述芯片堆叠结构上形成中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连 区域与所述基板之间电连接；
步骤504：形成塑封料，所述塑封料密封所述芯片堆叠结构、所述中介层和所述基板的第一面，其中，所述第一互连区域不被所述塑封料密封，所述第二互连区域被所述塑封料密封，且所述第二互连区域上的所述塑封料的顶表面与所述第一互连区域之间具有预设高度。
下面结合具体实施例对本公开实施例提供的半导体封装组件的制备方法再作进一步详细的说明。
图6a至图6i为本公开实施例提供的半导体封装组件在制备过程中的结构示意图。
首先，参见图6a，执行步骤501，提供基板10，所述基板10具有第一面101。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
如图2所示，所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在本公开实施例中，所述基板10的第一面101即为所述基板上绝缘介质层12的上表面。所述基板10还包括第二面102，即为所述基板下绝缘介质层13的下表面。
所述基板10还包括位于所述基板上绝缘介质层12内的基板上连接焊盘14，位于所述基板下绝缘介质层13内的基板下连接焊盘15，以及贯穿所述基板衬底11并将所述基板上连接焊盘14和所述基板下连接焊盘15彼此连接的基板连接通孔16。
所述基板上连接焊盘14和所述基板下连接焊盘15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述基板连接通孔16可以为穿硅通孔(TSV)。
所述基板10还包括分别位于所述基板10相对的两侧的第一信号传输区域110和第二信号传输区域120。所述第一信号传输区域110与后续形成的芯片堆叠结构20电连接，所述第二信号传输区域120与后续形成的中介层30电连接。
在一些实施例中，第一信号传输区域110与第二信号传输区域120不互连。
所述基板10还包括位于所述第一信号传输区域110和第二信号传输区域120之间的第三信号传输区域130，后续芯片堆叠结构20形成在所述第三信号传输区域130上。
在一些实施例中，第一信号传输区域110与第三信号传输区域130互连，第三信号传输区域130与第二信号传输区域120之间不互连。
接着，参见图6b，执行步骤502，在所述基板10上形成芯片堆叠结构20，所述芯片堆叠结构20包括沿垂直于所述基板10方向依次堆叠的多个芯片21，所述芯片堆叠结构20与所述基板10的第一面101之间电连接。
在本公开实施例中，采用向上依次堆叠多个芯片的方式，可以节省半导体封装组件的水平面积。
相邻两个所述芯片21之间通过粘附膜60连接，所述芯片堆叠结构20与基板10之间也通过粘附膜60连接，在本公开的一个实施例中，粘附膜60可以是DAF。
接着，参见图6c至图6d，执行步骤503，在所述芯片堆叠结构20上形成中介层30，所述中介层30具有第一互连面301，所述第一互连面301具有第一互连区域31和第二互连区域32，所述第一互连区域31与所述基板10之间电连接。
具体地，先参见图6c，在圆环1上粘贴载带2，然后在载带2上粘贴粘附膜60，然后将中介层粘贴在粘附膜60上，此时的中介层为整片的条状，对中介层进行切割，形成如图6c所示的一个一个的单元。
参见图6c和图6d，在形成中介层30后，在所述中介层30的第一互连区域31上形成在垂直于基板10的方向上具有预设高度h的覆盖层80，所述覆盖层80的侧壁与垂直于所述基板10方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
在本公开的一个实施例中，覆盖层的材料可以是聚酰亚胺、聚酯类材料、聚乙烯对苯二甲酸酯膜等。
在图6d所示的实施例中，所述覆盖层80的侧壁与垂直于所述基板10方向的夹角为0°，形成的塑封料的结构如图1所示，在其他实施例中，所述覆盖层的侧壁与垂直于所述基板方向的夹角大于0°，且小于90°，形成的塑封料的结构如图4所示。
本公开实施例中，通过在所述中介层的第一互连区域上形成覆盖层，如此，后续形成塑封料后，既能避免塑封过程中塑封料对第一互连区域的污染，还能在中介层30上通过预设厚度的覆盖层来设定中介层30上第一互连区域上的暴露高度，使得第一互连区域的预设高度设计更为灵活，此外，覆盖层的使用，使得在塑封的时候无需使用异形封装模具，而可以直接通过去除覆盖层的方式露出第一互连区域，能减少成本，同时形成工艺 也更为简单。
在形成覆盖层80后，需要将贴附在所述圆环1上的中介层进行清洗，以便清除杂质和灰尘，以避免中介层不干净而对半导体封装组件的性能产生影响。
接着，继续参见图6d，在所述芯片堆叠结构20上形成中介层30。
具体地，将中介层30从载带2上分离，利用中介层30底部的粘附膜60将中介层30粘附到芯片堆叠结构20顶部的芯片上。
如图3所示，所述中介层30包括基底33和分别设置在所述基底33的上表面和下表面上的中介上绝缘介质层34和中介下绝缘介质层35。
所述基底33可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述中介上绝缘介质层34和所述中介下绝缘介质层35可以为阻焊层，例如所述中介上绝缘介质层34和所述中介下绝缘介质层35的材料可以为绿漆。
在一实施例中，所述中介层30的基底33内具有电磁屏蔽层(未图示)。通过在中介层的基底内设置电磁屏蔽层，可以防止第二封装结构与芯片堆叠结构之间发生信息干扰，影响器件工作。
继续参见图6d，所述方法还包括：在所述第一互连区域31上形成多个第一焊盘311，在所述第二互连区域32上形成多个第二焊盘321，其中，所述第二焊盘321的数量大于所述第一焊盘311的数量，所述第二焊盘321的面积小于所述第一焊盘311的面积。
因为第一焊盘后续需要与第二封装结构进行匹配互连，因此布局设计相对比较固定，而第二焊盘承载的是第二封装结构与基板的互连，因此布局设计更为灵活，将第二焊盘设计成数量较多，面积较小，可以提高信号传输效率。
所述第一焊盘311和所述第二焊盘321位于所述中介上绝缘介质层34内。
所述第一焊盘311和所述第二焊盘321的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。
在一实施例中，在垂直于所述基板10的方向上，所述基板10具有第一厚度，所述中介层30具有第二厚度，其中，所述第一厚度大于所述第二厚度。
继续参见图6d，所述方法还包括：在形成中介层30后，
形成第一导电线51；每个所述芯片21通过所述第一导电线51与所述 基板10之间电连接；
形成第二导电线52；所述第二互连区域32通过所述第二导电线52与所述基板10之间电连接。
具体地，所述芯片21具有第一连接端201，所述第一连接端201与所述第一信号传输区域110位于同一侧，从所述第一连接端201上引出第一导电线51到所述第一传输区域110上，以实现所述芯片21与所述基板10之间的电连接。
所述第二互连区域32上形成有第二焊盘321，从第二焊盘321上引出第二导电线52到所述第二传输区域120上，以实现所述中介层30与所述基板10之间的电连接。本公开实施例中，所述芯片堆叠结构与所述基板之间采用引线键合方式进行电连接，其中，引线键合方式包括悬垂(Overhang)方式和导线上膜(Film on wire，FOW)方式。
图6d所示的实施例中，采用悬垂方式进行引线键合。相邻两个芯片21之间通过粘附膜60连接，所述粘附膜60不覆盖其下方一层的芯片21上的第一连接端201以及第一导电线51，所述粘附膜60与其下方一层的所述芯片21错位设置。
在另一些实施例中，采用导线上膜方式进行引线键合(未图示)。多个所述芯片沿垂直于所述基板的方向对齐设置，相邻两个芯片之间的粘附膜覆盖其下方一层的芯片上的第一连接端以及第一导电线。
接着，参见图6e至图6h，执行步骤504，形成塑封料40，所述塑封料40密封所述芯片堆叠结构20、所述中介层30和所述基板10的第一面101，其中，所述第一互连区域31不被所述塑封料40密封，所述第二互连区域32被所述塑封料40密封，且所述第二互连区域32上的所述塑封料40的顶表面401与所述第一互连区域31之间具有预设高度h。
具体地，先参见图6e，所述方法还包括：在形成覆盖层80后，形成第一封装模具91；所述第一封装模具91的表面平行于所述基板10的表面，所述第一封装模具91位于所述覆盖层80的上方，且与所述覆盖层80之间存在一定距离。
继续参见图6e，所述方法还包括：形成第二封装模具92，所述第二封装模具92位于所述基板10的下方，且平行于所述基板10的表面。
接着，参见图6f，所述方法还包括：以第一封装模具91为掩膜，形成密封所述芯片堆叠结构20、所述中介层30、所述覆盖层80和所述基板10的第一面101的塑封料预层400。
具体地，以第一封装模具91和第二封装模具92为掩膜，形成塑封料预层400。
在形成塑封料预层400后，去除所述第一封装模具91和所述第二封装模具92。
接着，参见图6g，去除部分所述塑封料预层400，暴露所述覆盖层80。
具体地，可以用砂轮在所述塑封料预层400的表面进行打磨，去除部分塑封料预层400，以形成塑封料40。在本公开的一个实施例中，塑封料40可以是EMC。
在本公开的一个实施例中，在去除所述第一封装模具91和第二封装模具92后，还包括去除基板下方的塑封料预层，暴露出基板的第二面。
在本公开的一个实施例中，在去除基板下方的塑封料预层，暴露出基板的第二面之后，去除中介层上的部分所述塑封料预层，暴露出所述覆盖层80。通过这样除去多余塑封料预层的步骤，有效的控制塑封过程中的应力，防止基板、芯片堆叠结构以及中介层之间发生翘曲，影响封装稳定性。
接着，参见图6h，去除所述覆盖层80，暴露所述第一互连区域31。
具体地，所述去除覆盖层80，包括：使用化学溶液去除所述覆盖层80，所使用的化学溶液可以溶解所述覆盖层，但是不对芯片以及塑封料等结构造成损失。
继续参见图6h，在形成塑封料40后，在所述基板10的第二面102上形成基板连接凸块17，所述基板连接凸块17包括导电材料。
接着，参见图6i，所述方法还包括：形成第二封装结构70，在所述第二封装结构70上形成第一焊球71，所述第一焊球71与所述第一互连区域31电连接，其中，所述第一焊球71的高度H大于所述预设高度h。
本公开实施例中，通过设置第一焊球的高度大于塑封料的顶表面与第一互连区域之间的高度，可以使得第二封装结构能够与中介层紧密连接，同时，在第二封装结构与中介层连接后，第二封装结构与塑封料之间能存在空隙，如此，能增加控制器散热效率，减小热量对芯片的影响。
所述第二封装结构70还包括第二基板72，所述第二基板72的结构与所述基板10的结构相同，这里不再赘述。
在一实施例中，在垂直于所述基板10的方向上，所述塑封料40具有第一厚度；所述第二封装结构70包括第二塑封料73，在垂直于所述基板10的方向上，所述第二塑封料73具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
所述第二封装结构70还包括第二芯片结构(未图示)，所述第二芯片结构与所述芯片堆叠结构20的类型相同或不同。
例如，所述第二芯片结构可以为通用闪存存储芯片(Universal File Store，UFS)。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一互连区域与芯片堆叠结构以及基板连接，如此，可实现不同类型或不同规格的芯片结构之间的互连，使得不同芯片结构之间的组合更加灵活。同时因为芯片堆叠结构和后续与芯片堆叠结构连接的第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。并且由于中介层的第一互连区域与塑封料的顶表面之间存在预设高度，如此，第二封装结构可放置于第一互连区域上，由塑封料围成的区域内，进而减少整体结构的高度和尺寸。

Claims (15)

  1. 一种半导体封装组件，包括：
    基板，所述基板具有第一面；
    芯片堆叠结构，位于所述基板上，所述芯片堆叠结构包括沿垂直于所述基板方向依次堆叠的多个芯片，所述芯片堆叠结构与所述基板的第一面之间电连接；
    中介层，位于所述芯片堆叠结构上；所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域与所述基板之间电连接；
    塑封料，所述塑封料密封所述芯片堆叠结构、所述中介层和所述基板的第一面，其中，所述第一互连区域不被所述塑封料密封，所述第二互连区域被所述塑封料密封，且所述第二互连区域上的所述塑封料的顶表面与所述第一互连区域之间具有预设高度。
  2. 根据权利要求1所述的半导体封装组件，其中，还包括：
    第一导电线，每个所述芯片通过所述第一导电线与所述基板之间电连接；
    第二导电线，所述第二互连区域通过所述第二导电线与所述基板之间电连接。
  3. 根据权利要求1所述的半导体封装组件，其中，
    所述第一互连区域上包括多个第一焊盘，所述第二互连区域上包括多个第二焊盘，其中，所述第二焊盘的数量大于所述第一焊盘的数量，所述第二焊盘的面积小于所述第一焊盘的面积。
  4. 根据权利要求1所述的半导体封装组件，其中，
    所述塑封料的顶表面与所述第一互连区域之间的侧壁与垂直于所述基板方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
  5. 根据权利要求1所述的半导体封装组件，其中，
    所述中介层包括基底，所述基底内具有电磁屏蔽层。
  6. 根据权利要求1所述的半导体封装组件，其中，
    在垂直于所述基板的方向上，所述基板具有第一厚度，所述中介层具有第二厚度，其中，所述第一厚度大于所述第二厚度。
  7. 根据权利要求1所述的半导体封装组件，其中，还包括：
    第二封装结构，所述第二封装结构包括第一焊球，所述第一焊球与所述第一互连区域电连接，其中，所述第一焊球的高度大于所述预设高度。
  8. 一种半导体封装组件的制备方法，包括：
    提供基板，所述基板具有第一面；
    在所述基板上形成芯片堆叠结构，所述芯片堆叠结构包括沿垂直于所 述基板方向依次堆叠的多个芯片，所述芯片堆叠结构与所述基板的第一面之间电连接；
    在所述芯片堆叠结构上形成中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域与所述基板之间电连接；
    形成塑封料，所述塑封料密封所述芯片堆叠结构、所述中介层和所述基板的第一面，其中，所述第一互连区域不被所述塑封料密封，所述第二互连区域被所述塑封料密封，且所述第二互连区域上的所述塑封料的顶表面与所述第一互连区域之间具有预设高度。
  9. 根据权利要求8所述的方法，其中，在所述芯片堆叠结构上形成中介层包括：
    提供中介层，所述中介层的底部具有粘附层，将所述中介层通过所述粘附层粘附到所述芯片堆叠结构上。
  10. 根据权利要求8所述的方法，其中，还包括：
    在形成中介层后，
    形成第一导电线；每个所述芯片通过所述第一导电线与所述基板之间电连接；
    形成第二导电线；所述第二互连区域通过所述第二导电线与所述基板之间电连接。
  11. 根据权利要求8所述的方法，其中，还包括：
    在所述第一互连区域上形成多个第一焊盘，在所述第二互连区域上形成多个第二焊盘，其中，所述第二焊盘的数量大于所述第一焊盘的数量，所述第二焊盘的面积小于所述第一焊盘的面积。
  12. 根据权利要求8所述的方法，其中，还包括：
    在形成中介层后，在所述中介层的第一互连区域上形成具有所述预设高度的覆盖层，所述覆盖层的侧壁与垂直于所述基板方向的夹角为第一夹角，所述第一夹角大于或等于0°，且小于90°。
  13. 根据权利要求12所述的方法，其中，还包括：
    在形成覆盖层后，形成第一封装模具；所述第一封装模具的表面平行于所述基板的表面，所述第一封装模具位于所述覆盖层的上方，且与所述覆盖层之间存在一定距离。
  14. 根据权利要求13所述的方法，其中，还包括：
    以第一封装模具为掩膜，形成密封所述芯片堆叠结构、所述中介层、所述覆盖层和所述基板的第一面的塑封料预层；
    去除部分所述塑封料预层，暴露所述覆盖层；
    去除所述覆盖层，暴露所述第一互连区域。
  15. 根据权利要求8所述的方法，其中，还包括：
    形成第二封装结构，在所述第二封装结构上形成第一焊球，将所述第 一焊球与所述第一互连区域电连接，其中，所述第一焊球的高度大于所述预设高度。
PCT/CN2022/110774 2022-07-08 2022-08-08 半导体封装组件及制备方法 WO2024007412A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172157A (ja) * 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
US20050023657A1 (en) * 2003-04-18 2005-02-03 Yu-Fang Tsai Stacked chip-packaging structure
US20090001540A1 (en) * 2007-06-29 2009-01-01 Stats Chippac, Ltd. Stackable Package by Using Internal Stacking Modules
CN204102862U (zh) * 2014-08-01 2015-01-14 深圳市兴森快捷电路科技股份有限公司 一种基于腔体技术多芯片叠加封装装置
CN110797325A (zh) * 2019-12-12 2020-02-14 江阴长电先进封装有限公司 一种具有电磁屏蔽功能的封装结构及其封装方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11211334B2 (en) * 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
JP7409029B2 (ja) * 2019-11-15 2024-01-09 株式会社レゾナック 半導体装置の製造方法、並びにダイシング・ダイボンディング一体型フィルム及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172157A (ja) * 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
US20050023657A1 (en) * 2003-04-18 2005-02-03 Yu-Fang Tsai Stacked chip-packaging structure
US20090001540A1 (en) * 2007-06-29 2009-01-01 Stats Chippac, Ltd. Stackable Package by Using Internal Stacking Modules
CN204102862U (zh) * 2014-08-01 2015-01-14 深圳市兴森快捷电路科技股份有限公司 一种基于腔体技术多芯片叠加封装装置
CN110797325A (zh) * 2019-12-12 2020-02-14 江阴长电先进封装有限公司 一种具有电磁屏蔽功能的封装结构及其封装方法

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