WO2024007431A1 - 半导体封装结构及制备方法 - Google Patents

半导体封装结构及制备方法 Download PDF

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Publication number
WO2024007431A1
WO2024007431A1 PCT/CN2022/115802 CN2022115802W WO2024007431A1 WO 2024007431 A1 WO2024007431 A1 WO 2024007431A1 CN 2022115802 W CN2022115802 W CN 2022115802W WO 2024007431 A1 WO2024007431 A1 WO 2024007431A1
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Prior art keywords
packaging structure
chip
conductive block
substrate
adhesive layer
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PCT/CN2022/115802
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English (en)
French (fr)
Inventor
左明星
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长鑫存储技术有限公司
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Priority to US18/166,465 priority Critical patent/US20240014190A1/en
Publication of WO2024007431A1 publication Critical patent/WO2024007431A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor packaging structure and a preparation method.
  • embodiments of the present disclosure provide a semiconductor packaging structure and a manufacturing method.
  • a semiconductor packaging structure including:
  • the first packaging structure includes a chip stack structure and a plastic packaging material.
  • a first conductive block is provided on the chip stack structure.
  • the plastic packaging material wraps the chip stack structure and exposes the first conductive block;
  • a second packaging structure is provided on the chip stack structure and is electrically connected to the first conductive block;
  • the first packaging structure further includes:
  • a substrate the substrate includes an upper surface and a lower surface arranged oppositely, and a first conductive pattern and a second conductive pattern are respectively provided on the upper surface and the lower surface;
  • the substrate further includes a signal channel between the upper surface and the lower surface, the signal channel connecting the first conductive pattern and the second conductive pattern.
  • the chip stack structure includes:
  • a first chip arranged on the substrate
  • first chip and the second chip are respectively connected to the substrate through leads, and the leads are located on the same side of the chip stack structure.
  • the leads are connected to the same first conductive pattern.
  • the plastic compound covers the leads.
  • the top surface of the first conductive block is lower than the top surface of the plastic encapsulation material.
  • the second packaging structure is disposed on the first conductive block through a first solder ball, and the first solder ball protrudes from the plastic encapsulation material.
  • the chip stack structure includes:
  • the chip includes a first surface and a second surface arranged oppositely, the first conductive block is located on the first surface, and a second conductive block is disposed on the second surface; the first The conductive block and the second conductive block are connected through the first signal hole.
  • the second conductive block at the bottom of the chip stack structure is connected to the first conductive pattern through a second solder ball, and two adjacent chips are connected through a second solder ball.
  • the plastic molding material is also located between two adjacent chips.
  • the first conductive block and the plastic molding compound are coplanar.
  • a filling layer is further included, and the filling layer fills the gap.
  • the thermal conductivity of the filling layer is greater than the thermal conductivity of the plastic molding compound.
  • the filler volume in the filling layer is smaller than the filler volume of the plastic molding material.
  • the first chip is disposed on the substrate through an adhesive layer
  • the substrate further includes a virtual channel
  • the adhesive layer is located on the virtual channel
  • the thermal conductivity of the virtual channel Greater than the thermal conductivity of the adhesive layer.
  • the adhesive layer includes a first adhesive layer and a second adhesive layer, the second adhesive layer is located on the first adhesive layer, and the elasticity of the first adhesive layer The modulus is smaller than the elastic modulus of the second adhesive layer.
  • the substrate further includes a dummy channel through which the second solder ball is connected to the second conductive pattern.
  • a method for preparing a semiconductor packaging structure including:
  • a first packaging structure is provided.
  • the first packaging structure includes a chip stack structure and a plastic sealant.
  • a first conductive block is provided on the chip stack structure.
  • the plastic sealant wraps the chip stack structure and exposes the first conductive block. conductive block;
  • a second packaging structure dispose the second packaging structure on the chip stack structure, and the second packaging structure is electrically connected to the first conductive block;
  • the first conductive block serves as an intermediary. Additional intermediary structures are required for connection, which reduces the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly. Therefore, after forming the semiconductor packaging structure, the The overall structure is not tested. Moreover, there is a gap between the second packaging structure and the first packaging structure, thereby increasing the distance between them, thereby improving the heat dissipation efficiency of the second packaging structure and reducing the impact of heat on the chip.
  • Figure 1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of a first packaging structure provided by another embodiment of the present disclosure.
  • Figure 7 is a schematic flow chart of a method for preparing a semiconductor packaging structure provided by the disclosed embodiment
  • FIGS 8a to 8f are schematic diagrams of the device structure during the preparation process of the semiconductor packaging structure provided by embodiments of the present disclosure.
  • 9a to 9c are schematic diagrams of the device structure during the preparation process of the semiconductor packaging structure provided by another embodiment of the present disclosure.
  • 70-Filling layer 701-Second filler.
  • FIG. 1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure.
  • the semiconductor packaging structure includes: a first packaging structure, including a chip stack structure 20 and a plastic sealant 30.
  • the chip stack structure 20 is provided with a first conductive block 201, and the plastic sealant 30 wraps the Chip stack structure 20, and expose the first conductive block 201;
  • the second packaging structure 60 is provided on the chip stack structure 20 and is electrically connected to the first conductive block 201;
  • the first conductive block serves as an intermediary. Additional intermediary structures are required for connection, which reduces the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly. Therefore, after forming the semiconductor packaging structure, the The overall structure is not tested. Moreover, there is a gap between the second packaging structure and the first packaging structure, thereby increasing the distance between them, thereby improving the heat dissipation efficiency of the second packaging structure and reducing the impact of heat on the chip.
  • the first packaging structure further includes: a substrate 10.
  • the substrate 10 includes an upper surface and a lower surface arranged oppositely, and first conductive patterns 14 are respectively provided on the upper surface and the lower surface. and the second conductive pattern 15;
  • the substrate 10 further includes a signal channel 16 located between the upper surface and the lower surface, and the signal channel 16 connects the first conductive pattern 14 and the second conductive pattern 15 .
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a base substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the base substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the first conductive pattern 14 is located in the insulating dielectric layer 12 on the substrate, the second conductive pattern 15 is located in the insulating dielectric layer 13 under the substrate, and the signal channel 16 is located in the base substrate 11, and penetrates the base substrate 11 .
  • the first conductive pattern 14 and the second conductive pattern 15 may be connection pads, and the materials of the first conductive pattern 14 and the second conductive pattern 15 may include aluminum, copper, nickel, tungsten, and platinum. and at least one of gold.
  • the signal channel 16 may be a through silicon via (TSV).
  • the first conductive pattern 14 and the second conductive pattern 15 are connected through the signal channel 16, thereby allowing signals to be transmitted.
  • two adjacent first conductive patterns 14 can also be connected through a redistribution layer, so that signal transmission on the substrate can be completed.
  • the substrate 10 also includes substrate connection bumps 17, which can electrically connect the semiconductor package structure to an external device and can receive control signals, power signals and ground for operating the chip stack structure from the external device. At least one of the signals may either receive a data signal to be stored in the chip stack structure from an external device, or provide data within the chip stack structure to an external device.
  • the substrate connection bumps 17 include electrically conductive material.
  • the substrate connection bumps 17 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only a lower and feasible shape in the embodiment of the present disclosure. The specific implementation of the invention does not constitute a limitation of the present disclosure, and the substrate connection bumps can also be of other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.
  • FIG. 2 is a schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure.
  • the embodiment of the present disclosure there are two ways of connecting the first chip, the second chip and the substrate. One is as shown in Figure 1, using an adhesive layer for connection, and the other is as shown in Figure 1. As shown in Figure 2, the first conductive block, the second conductive block and the first signal hole are used for connection.
  • the chip stack structure 20 includes:
  • the first chip 21 is provided on the substrate 10;
  • the second chip 22 is offsetly arranged on the first chip 21;
  • the first chip 21 and the second chip 22 are respectively connected to the substrate 10 through leads 40 , and the leads 40 are located on the same side of the chip stack structure 20 . Since the second chip 22 is offsetly disposed on the first chip 21, wiring is more convenient.
  • the first chip 21 and the second chip 22 may be a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, or an electrically erasable programmable read-only memory (EEPROM). chip, Phase Change Random Access Memory (PRAM) chip, Magnetic Random Access Memory (MRAM) chip or Resistive Random Access Memory (RRAM) chip.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • PRAM Phase Change Random Access Memory
  • MRAM Magnetic Random Access Memory
  • RRAM Resistive Random Access Memory
  • the first chip 21 is disposed on the substrate 10 through an adhesive layer 50.
  • the substrate 10 also includes a virtual channel 18.
  • the adhesive layer 50 is located on the virtual channel 18, and the virtual channel 18 has The thermal conductivity is greater than the thermal conductivity of the adhesive layer 50 .
  • the adhesive layer 50 may be a DAF film.
  • the adhesive layer includes a first adhesive layer 51 and a second adhesive layer 52 located on the first adhesive layer 51.
  • the second adhesive layer The elastic modulus of 52 is greater than the elastic modulus of the first adhesive layer 51 .
  • the first adhesive layer mainly plays a bonding role
  • the second adhesive layer mainly plays a role in preventing chip warpage
  • the high elastic modulus of the second adhesive layer it is difficult to cut when cutting.
  • the first adhesive layer has a low elastic modulus, which will not affect the bonding force between the substrate and the chip in subsequent processes.
  • the thermal conductivity of the virtual channel is greater than the thermal conductivity of the adhesive layer, which can dissipate the heat generated by the chip operation through the virtual channel and reduce the impact on device performance.
  • the virtual channel 18 is composed of a first conductive pattern 14, a second conductive pattern 15 and a signal channel 16. However, no substrate connection bumps 17 are formed below the virtual channel 18, so signal transmission cannot be realized and it is only used for heat dissipation.
  • the thermal conductivity of the virtual channel is greater than the thermal conductivity of other structures composed of the first conductive pattern 14 , the second conductive pattern 15 and the signal channel 16 that function as signal transmission, which can reduce the impact of heat on signal transmission.
  • the leads 40 are connected to the same first conductive pattern 14 .
  • the plastic encapsulation material 30 covers the leads 40 .
  • the plastic encapsulation material covers the leads to ensure that the leads are in a sealed and insulated state and will not react with oxygen or other substances in the air to affect the performance of the device.
  • the top surface of the first conductive block 201 is lower than the top surface of the plastic molding material 30 . Since the top surface of the first conductive block is lower than the top surface of the plastic encapsulation material, a groove is formed. Subsequently, the second packaging structure can be placed in the groove to reduce the height of the device structure.
  • the second packaging structure 60 is disposed on the first conductive block 201 through a first solder ball 61 , and the first solder ball 61 protrudes from the plastic encapsulation material 30 .
  • the height from the top surface of the first conductive block 201 to the top surface of the plastic molding material 30 is h
  • the height of the first solder ball 61 is H
  • the third The height H of a solder ball 61 is greater than the height h from the top surface of the first conductive block 201 to the top surface of the plastic encapsulation material 30 .
  • the first solder ball By setting the height of the first solder ball to be greater than the height from the top surface of the first conductive block to the top surface of the plastic encapsulation material, the first solder ball can be in closer contact with the first conductive block, and at the same time, the first package structure can be in contact with the first conductive block. There can be a gap between the two packaging structures, thereby increasing the distance between the two, thereby improving the heat dissipation efficiency of the second packaging structure and reducing the impact of heat dissipation on the chip. Otherwise, if the height of the first solder ball is less than the height from the top surface of the first conductive block to the top surface of the plastic encapsulation material, the first solder ball and the first conductive block will not be in contact, affecting device performance.
  • the second packaging structure also includes a second substrate 62.
  • the structure of the second substrate 62 is the same as that of the substrate 10, which will not be described again here.
  • the second packaging structure may be Universal Flash Storage (Universal File Store, UFS).
  • the angle between the side wall between the top surface of the plastic molding material 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is greater than or equal to 0° and less than 90°. .
  • the angle between the side wall between the top surface of the plastic molding material 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is 0°, that is, the plastic molding material 30
  • the side wall between the top surface of the second chip 22 and the top surface of the second chip 22 is perpendicular to the substrate 10 .
  • the side walls of the plastic molding material are set into a vertical shape, making the process simpler.
  • the angle a between the side wall between the top surface of the plastic compound 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is greater than 0° and less than 90°.
  • the side walls of the plastic molding material are set in a non-vertical shape, so that subsequent interconnection with the second packaging structure can be more convenient.
  • the chip stack structure includes:
  • the chip includes a first surface 210 and a second surface 220 arranged oppositely, the first conductive block 201 is located on the first surface 210, and a second conductive block is disposed on the second surface 220 202;
  • the first conductive block 201 and the second conductive block 202 are connected through the first signal hole 203.
  • the material of the first conductive block 201 and the second conductive block 202 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the first signal hole 203 may be a through silicon via (TSV).
  • the second conductive block 202 at the bottom of the chip stack structure 20 is connected to the first conductive pattern 14 through a second solder ball 204, and two adjacent chips are connected through a second conductive block 204. Solder ball 204 connection.
  • the chip stack structure 20 may include a first chip 21 and a second chip 22 .
  • the first chip 21 and the second chip 22 are connected by a second conductive block 202 located on the second surface 220 of the second chip 22 and a second conductive block 202 located on the first surface 210 of the first chip 21 .
  • the first conductive block 201 and the second solder ball 204 between the first conductive block 201 and the second conductive block 202 are connected.
  • the substrate 10 further includes a dummy channel 18 through which the second solder ball 204 is connected to the second conductive pattern 15 .
  • the plastic molding material 30 is also located between two adjacent chips.
  • the plastic packaging material is located between two adjacent chips, that is, the plastic packaging material completely wraps the chip stack structure, which can insulate the chip stack structure.
  • the first conductive block 201 and the plastic molding material 30 are coplanar.
  • the top surface of the first conductive block 201 on the second chip 22 is coplanar with the top surface of the plastic molding material 30 .
  • the plastic molding material finally formed is The first conductive blocks are coplanar, so in the process of forming the plastic sealing compound, there is no need to use special-shaped molds, only molds with normal shapes need to be used. Since molds with normal shapes have simple shapes, the manufacturing process is simple and the cost is low.
  • the plastic encapsulation material is coplanar with the first conductive block, so that after the second encapsulation structure is subsequently connected to the first encapsulation structure, a large gap can be formed between the first encapsulation structure and the second encapsulation structure, ensuring that The heat dissipation efficiency of the second packaging structure.
  • the gap between the first packaging structure and the second packaging structure will be reduced, which is not conducive to heat dissipation. At the same time, it is not conducive to the filling of the filling layer when the filling layer is subsequently formed. ; If the surface of the first conductive block is higher than the surface of the plastic sealing material, although the gap can be increased, the plastic sealing material may not be able to completely cover the chip under the first conductive block, causing the chip to be exposed, which is not conducive to protecting the chip.
  • FIGS. 4 and 5 are schematic structural diagrams of a semiconductor packaging structure provided by yet another embodiment of the present disclosure.
  • the semiconductor packaging structure further includes a filling layer 70 that fills the gap.
  • the thermal conductivity of the filling layer 70 is greater than the thermal conductivity of the plastic molding material 30 .
  • the filling layer not only can the first packaging structure and the second packaging structure have a sealed interface, reducing the contact between the metal structures of the first packaging structure and the second packaging structure and the outside air or other materials, but also can achieve Thermal conductivity. And because the thermal conductivity of the filling layer is large, more heat can be dissipated from the filling layer, reducing the impact of heat on the first packaging structure. At the same time, since the thermal expansion coefficient of the filling layer matches the first packaging structure and the second packaging structure, the volume change of the filling layer is small, and no outward pressure is exerted on the first packaging structure and the second packaging structure, ensuring the structural stability. stability.
  • the filler volume in the filling layer 70 is smaller than the filler volume of the plastic molding material 30 .
  • the filler in the plastic molding material 30 is a first filler 301
  • the filler in the filling layer 70 is a second filler 701.
  • the volume of the second filler 701 is smaller than the volume of the first filler 301. .
  • the main material of the plastic molding material 30 and the filling layer 70 may be epoxy resin, and the filler may be silica powder.
  • the gap filled by the plastic molding material is large and the gap between the first packaging structure and the second packaging structure is small, a filling layer with greater fluidity is selected, and the filler volume in the filling layer is small. , the main material has high fluidity.
  • the semiconductor packaging structure provided by the embodiment of the present disclosure can be applied to a multi-process package chip (UFS Multi Chip Package, UMCP) with a package on package (Package on Package, PoP) structure.
  • UFS Multi Chip Package, UMCP multi-process package chip
  • PoP package on Package
  • An embodiment of the present disclosure also provides a method for preparing a semiconductor packaging structure. Please refer to Figure 7 for details. As shown in the figure, the method includes the following steps:
  • Step 701 Provide a first packaging structure.
  • the first packaging structure includes a chip stack structure and a plastic compound.
  • the chip stack structure is provided with a first conductive block.
  • the plastic compound wraps the chip stack structure and exposes the chip stack structure.
  • Step 702 Provide a second packaging structure, dispose the second packaging structure on the chip stack structure, and the second packaging structure is electrically connected to the first conductive block; wherein the first packaging structure and the There is a gap between the second packaging structures.
  • FIGS 8a to 8f are schematic structural diagrams of a semiconductor packaging structure during the preparation process provided by an embodiment of the present disclosure.
  • Figures 9a to 9c are schematic structural diagrams of a semiconductor packaging structure provided by another embodiment of the present disclosure during the preparation process. Explanation is required. What is interesting is that the embodiment shown in Figures 8a to 8f and the embodiment shown in Figures 9a to 9c are only different in the chip stack structure and the structure of the plastic packaging material, and the other structures are the same.
  • FIGS. 8a to 8f will be described in detail.
  • step 701 is performed to provide a first packaging structure.
  • the first packaging structure includes a chip stack structure 20 and a plastic encapsulation material 30.
  • the chip stack structure 20 is provided with a first conductive block 201.
  • the plastic compound 30 wraps the chip stack structure 20 and exposes the first conductive block 201 .
  • a substrate 10 is provided.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a base substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the base substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the substrate 10 also includes an upper surface and a lower surface arranged oppositely.
  • a first conductive pattern 14 and a second conductive pattern 15 are respectively provided on the upper surface and the lower surface; the first conductive pattern 14 is located on the In the insulating dielectric layer 12 on the upper substrate, the second conductive pattern 15 is located in the insulating dielectric layer 13 under the substrate.
  • the signal channel 16 is located in the base substrate 11 and penetrates the base substrate 11 .
  • the first conductive pattern 14 and the second conductive pattern 15 may be connection pads, and the materials of the first conductive pattern 14 and the second conductive pattern 15 may include aluminum, copper, nickel, tungsten, and platinum. and at least one of gold.
  • the signal channel 16 may be a through silicon via (TSV).
  • the first conductive pattern 14 and the second conductive pattern 15 are connected through the signal channel 16, thereby allowing signals to be transmitted.
  • two adjacent first conductive patterns 14 can also be connected through a redistribution layer, so that signal transmission on the substrate can be completed.
  • the substrate 10 also includes virtual channels 18 .
  • the virtual channel 18 is composed of a first conductive pattern 14, a second conductive pattern 15 and a signal channel 16.
  • no substrate connection bumps 17 are formed below the virtual channel 18, so signal transmission cannot be realized and it is only used for heat dissipation.
  • the thermal conductivity of the virtual channel is greater than the thermal conductivity of other structures composed of the first conductive pattern 14 , the second conductive pattern 15 and the signal channel 16 that function as signal transmission, which can reduce the impact of heat on signal transmission.
  • a chip stack structure 20 is formed on the substrate 10.
  • the cut chip is placed on the substrate 10 .
  • an adhesive layer 50 is formed on the substrate 10 , and a chip stack structure 20 is formed on the adhesive layer 50 .
  • the adhesive layer 50 may be a DAF film.
  • the adhesive layer includes a first adhesive layer 51 and a second adhesive layer 52 located on the first adhesive layer 51.
  • the second adhesive layer The elastic modulus of 52 is greater than the elastic modulus of the first adhesive layer 51 .
  • the first adhesive layer mainly plays a bonding role
  • the second adhesive layer mainly plays a role in preventing chip warpage
  • the high elastic modulus of the second adhesive layer it is difficult to cut when cutting.
  • the first adhesive layer has a low elastic modulus, which will not affect the bonding force between the substrate and the chip in subsequent processes.
  • the adhesive layer 50 is located on the virtual channel 18 , and the thermal conductivity of the virtual channel 18 is greater than the thermal conductivity of the adhesive layer 50 .
  • the thermal conductivity of the virtual channel is greater than the thermal conductivity of the adhesive layer, which can dissipate the heat generated by the chip operation through the virtual channel and reduce the impact on device performance.
  • the forming the chip stack structure 20 includes: forming a first chip 21 on the adhesive layer 50 and forming a second chip 22 on the first chip 21, wherein the first chip 21 and the second chip 22 are formed on the adhesive layer 50. Chip 22 offset setting.
  • the first chip 21 and the second chip 22 are also connected through an adhesive layer 50 .
  • the first chip 21 and the second chip 22 are respectively connected to the substrate 10 through leads 40 , and the leads 40 are located on the same side of the chip stack structure 20 .
  • the leads 40 are connected to the same first conductive pattern 14 .
  • a plastic encapsulation material 30 is formed to wrap the chip stack structure 20 , and the plastic encapsulation material 30 exposes the first conductive block 201 .
  • the plastic encapsulation material 30 covers the leads 40 .
  • the plastic encapsulation material covers the leads, which can ensure that the leads are in a sealed and insulated state and will not react with oxygen or other substances in the air, thereby affecting the performance of the device.
  • the top surface of the first conductive block 201 is lower than the top surface of the plastic molding material 30 . Since the top surface of the first conductive block is lower than the top surface of the plastic encapsulation material, a groove is formed. Subsequently, the second packaging structure can be placed in the groove to reduce the height of the device structure.
  • the angle between the side wall between the top surface of the plastic molding material 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is greater than or equal to 0° and less than 90°. .
  • the angle between the side wall between the top surface of the plastic molding material 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is 0°, that is, the plastic molding material 30
  • the side wall between the top surface of the second chip 22 and the top surface of the second chip 22 is perpendicular to the substrate 10 .
  • the side walls of the plastic molding material are set into a vertical shape, making the process simpler.
  • the angle a between the side wall between the top surface of the plastic compound 30 and the top surface of the second chip 22 and the direction perpendicular to the substrate 10 is greater than 0° and less than 90°.
  • the side walls of the plastic molding material are set in a non-vertical shape, so that subsequent interconnection with the second packaging structure can be more convenient.
  • substrate connection bumps 17 are formed on the second conductive pattern 15 of the substrate 10 , and the substrate connection bumps 17 include conductive material.
  • step 702 is performed to provide a second packaging structure 60, and dispose the second packaging structure 60 on the chip stack structure 20.
  • the second packaging structure 20 is electrically connected to the first conductive block 201. ; Wherein, there is a gap between the first packaging structure and the second packaging structure 60.
  • a first solder ball 61 is formed on the second package structure 60 , the first solder ball 61 is electrically connected to the first conductive block 201 , and the first solder ball 61 protrudes from the plastic package. Material 30.
  • the height from the top surface of the first conductive block 201 to the top surface of the plastic encapsulation material 30 is h
  • the height of the first solder ball 61 is H, where the first solder ball
  • the height H of 61 is greater than the height h from the top surface of the first conductive block 201 to the top surface of the plastic molding material 30 .
  • the first solder ball By setting the height of the first solder ball to be greater than the height from the top surface of the first conductive block to the top surface of the plastic encapsulation material, the first solder ball can be in closer contact with the first conductive block, and at the same time, the first package structure can be in contact with the first conductive block. There can be a gap between the two packaging structures, thereby increasing the distance between the two, thereby improving the heat dissipation efficiency of the second packaging structure and reducing the impact of heat dissipation on the chip. Otherwise, if the height of the first solder ball is less than the height from the top surface of the first conductive block to the top surface of the plastic encapsulation material, the first solder ball and the first conductive block will not be in contact, affecting device performance.
  • the second packaging structure also includes a second substrate 62.
  • the structure of the second substrate 62 is the same as that of the substrate 10, which will not be described again here.
  • the first solder ball 61 is located on the second substrate 62 .
  • a filling layer 70 is formed in the gap between the first package structure and the second package 60 .
  • the thermal conductivity of the filling layer 70 is greater than the thermal conductivity of the plastic molding material 30 .
  • the filling layer not only can the first packaging structure and the second packaging structure have a sealed interface, reducing the contact between the metal structures of the first packaging structure and the second packaging structure and the outside air or other materials, but also can achieve Thermal conductivity. And because the thermal conductivity of the filling layer is large, more heat can be dissipated from the filling layer, reducing the impact of heat on the first packaging structure. Although the thermal conductivity of the filling layer is large, due to the small volume of the filling layer, the volume change of the filling layer is small, which will not produce outward pressure on the first packaging structure and the second packaging structure, and can ensure the stability of the structure. sex.
  • the filler volume in the filling layer is smaller than the filler volume of the plastic molding material.
  • the filler in the molding compound 30 is a first filler 301
  • the filler in the filling layer 70 is a second filler 701 .
  • the volume of the second filler 701 is smaller than the volume of the first filler 301 .
  • the main material of the plastic molding material 30 and the filling layer 70 may be epoxy resin, and the filler may be silicon dioxide.
  • the gap filled by the plastic molding material is large and the gap between the first packaging structure and the second packaging structure is small, a filling layer with greater fluidity is selected, and the filler volume in the filling layer is small. , the main material has high fluidity.
  • FIGS. 9a to 9c Next, the embodiment shown in FIGS. 9a to 9c will be described in detail.
  • a chip stack structure 20 is formed on the substrate 10. It should be explained that the substrate in this embodiment is the same as the substrate in the embodiment shown in Figures 8a to 8e, and will not be described again here.
  • the chip stack structure 20 includes a plurality of chips.
  • the chips include a first surface 210 and a second surface 220 arranged oppositely.
  • a first conductive block 201 is formed on the first surface 210, and a first conductive block 201 is formed on the second surface 220.
  • a second conductive block 202 is formed; the first conductive block 201 and the second conductive block 202 are connected through a first signal hole 203 .
  • the material of the first conductive block 201 and the second conductive block 202 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the first signal hole 203 may be a through silicon via (TSV).
  • the second conductive block 202 at the bottom of the chip stack structure 20 is connected to the first conductive pattern 14 through a second solder ball 204, and two adjacent chips are connected through the second solder ball 204.
  • the chip stack structure 20 includes a first chip 21 and a second chip 22.
  • the first chip 21 and the second chip 22 are connected by a second conductive block 202 located on the second surface 220 of the second chip 22 and a second conductive block 202 located on the first surface 210 of the first chip 21 .
  • the first conductive block 201 and the second solder ball 204 between the first conductive block 201 and the second conductive block are connected.
  • a plastic encapsulation material 30 is formed to wrap the chip stack structure 20 .
  • the plastic molding material 30 is also located between two adjacent chips.
  • the plastic packaging material is located between two adjacent chips, that is, the plastic packaging material completely wraps the chip stack structure, which can insulate the chip stack structure.
  • the first conductive block 201 and the plastic molding material 30 are coplanar.
  • the top surface of the first conductive block 201 on the second chip 22 is coplanar with the top surface of the plastic molding material 30 .
  • the plastic molding material finally formed is The first conductive blocks are coplanar, so in the process of forming the plastic sealing compound, there is no need to use special-shaped molds, only molds with normal shapes need to be used. Since molds with normal shapes have simple shapes, the manufacturing process is simple and the cost is low.
  • the plastic encapsulation material is coplanar with the first conductive block, so that after the second encapsulation structure is subsequently connected to the first encapsulation structure, a large gap can be formed between the first encapsulation structure and the second encapsulation structure, ensuring that The heat dissipation efficiency of the second packaging structure.
  • the gap between the first packaging structure and the second packaging structure will be reduced, which is not conducive to heat dissipation. At the same time, it is not conducive to the filling of the filling layer when the filling layer is subsequently formed. ; If the surface of the first conductive block is higher than the surface of the plastic sealant, although the gap can be increased, the plastic sealant may not be able to cover the chip under the first conductive block, causing the chip to be exposed, which is not conducive to protecting the chip.
  • a second packaging structure 60 is formed on the first packaging structure. It should be explained that the steps after forming the second packaging structure in this embodiment are the same as the steps after forming the second packaging structure in the embodiments shown in 8a to 8e, and will not be described again here.
  • the first conductive block serves as an intermediary. Additional intermediary structures are required for connection, which reduces the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly. Therefore, after forming the semiconductor packaging structure, the The overall structure is not tested. Moreover, there is a gap between the second packaging structure and the first packaging structure, thereby increasing the distance between them, thereby improving the heat dissipation efficiency of the second packaging structure and reducing the impact of heat on the chip.

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Abstract

本公开实施例公开了一种半导体封装结构及制备方法，其中，所述半导体封装结构，包括：第一封装结构，包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；第二封装结构，设置在所述芯片堆叠结构上，与所述第一导电块电连接；其中，所述第一封装结构与所述第二封装结构之间存在空隙。

Description

半导体封装结构及制备方法
相关申请的交叉引用
本公开基于申请号为202210806527.8、申请日为2022年07月08日、发明名称为“半导体封装结构及制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体封装结构及制备方法。
背景技术
在所有部门，行业和地区，电子行业都在不断要求提供更轻、更快、更小、多功能、更可靠和更具成本效益的产品。为了满足众多不同消费者的这些不断增长的需求，需要集成更多的电路来提供所需的功能。在几乎所有应用中，对减小尺寸，提高性能和改善集成电路功能的需求不断增长。
发明内容
有鉴于此，本公开实施例提供一种半导体封装结构及制备方法。
根据本公开实施例的第一方面，提供了一种半导体封装结构，包括：
第一封装结构，包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；
第二封装结构，设置在所述芯片堆叠结构上，与所述第一导电块电连接；
其中，所述第一封装结构与所述第二封装结构之间存在空隙。
在一些实施例中，所述第一封装结构还包括：
基板，所述基板包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案和第二导电图案；
所述基板还包括位于所述上表面和所述下表面之间的信号通道，所述信号通道连接所述第一导电图案和所述第二导电图案。
在一些实施例中，所述芯片堆叠结构包括：
第一芯片，设置在所述基板上；
第二芯片，偏移地设置在所述第一芯片上；
其中，所述第一芯片和所述第二芯片分别通过引线连接所述基板，所述引线位于所述芯片堆叠结构的同侧。
在一些实施例中，所述引线连接至同一所述第一导电图案上。
在一些实施例中，所述塑封料覆盖所述引线。
在一些实施例中，所述第一导电块的顶面低于所述塑封料的顶面。
在一些实施例中，所述第二封装结构通过第一焊球设置在所述第一导电块上，且所述第一焊球突出于所述塑封料。
在一些实施例中，所述芯片堆叠结构包括：
多个芯片，所述芯片包括相对设置的第一表面和第二表面，所述第一导电块位于所述第一表面上，所述第二表面上设置有第二导电块；所述第一导电块和所述第二导电块通过第一信号孔连接。
在一些实施例中，所述芯片堆叠结构中最底部的所述第二导电块通过第二焊球连接所述第一导电图案，相邻两个所述芯片之间通过第二焊球连接。
在一些实施例中，所述塑封料还位于相邻两个所述芯片之间。
在一些实施例中，所述第一导电块与所述塑封料共面。
在一些实施例中，还包括填充层，所述填充层填满所述空隙。
在一些实施例中，所述填充层的导热系数大于所述塑封料的导热系数。
在一些实施例中，所述填充层中的填料体积小于所述塑封料的填料体积。
在一些实施例中，所述第一芯片通过粘结层设置在所述基板上，所述基板还包括虚拟通道，所述粘结层位于所述虚拟通道上，且所述虚拟通道的导热系数大于所述粘结层的导热系数。
在一些实施例中，所述粘结层包括第一粘结层和第二粘结层，所述第二粘结层位于所述第一粘结层上，所述第一粘结层的弹性模量小于所述第二粘结层的弹性模量。
在一些实施例中，所述基板还包括虚拟通道，所述第二焊球通过所述虚拟通道连接至所述第二导电图案。
根据本公开实施例的第二方面，提供了一种半导体封装结构的制备方法，包括：
提供第一封装结构，所述第一封装结构包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；
提供第二封装结构，将第二封装结构设置在所述芯片堆叠结构上，所述第二封装结构与所述第一导电块电连接；
其中，所述第一封装结构与所述第二封装结构之间存在间隙。
本公开实施例中，通过在芯片堆叠结构上设置第一导电块，通过第一 导电块将独立的第一封装结构和第二封装结构连接，因此第一导电块就起到中介的作用，不需要额外使用其他中介结构进行连接，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。并且第二封装结构与第一封装结构之间存在空隙，由此增加了二者之间的间距，从而能提高第二封装结构的散热效率，减少热量对芯片的影响。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体封装结构的结构示意图；
图2为本公开另一实施例提供的半导体封装结构的结构示意图；
图3为本公开另一实施例提供的第一封装结构的结构示意图；
图4至图6为公开实施例提供的半导体封装结构的其他示例；
图7为公开实施例提供的半导体封装结构的制备方法的流程示意图；
图8a至图8f为本公开实施例提供的半导体封装结构在制备过程中的器件结构示意图；
图9a至图9c为本公开另一实施例提供的半导体封装结构在制备过程中的器件结构示意图。
附图标记说明：
1-圆环；2-载带；
10-基板；11-基板衬底；12-基板上绝缘介质层；13-基板下绝缘介质层；14-第一导电图案；15-第二导电图案；16-信号通道；17-基板连接凸块；18-虚拟通道；
20-芯片堆叠结构；21-第一芯片；22-第二芯片；210-第一表面；220-第二表面；201-第一导电块；202-第二导电块；203-第一信号孔；204-第二焊球；
30-塑封料；301-第一填料；
40-引线；
50-粘结层；51-第一粘结层；52-第二粘结层；
60-第二封装结构；61-第一焊球；62-第二基板；
70-填充层；701-第二填料。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包 括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
本公开实施例提供了一种半导体封装结构。图1为本公开实施例提供的半导体封装结构的结构示意图。
参见图1，所述半导体封装结构，包括：第一封装结构，包括芯片堆叠结构20和塑封料30，所述芯片堆叠结构20上设置有第一导电块201，所述塑封料30包裹所述芯片堆叠结构20，并暴露所述第一导电块201；
第二封装结构60，设置在所述芯片堆叠结构20上，与所述第一导电块201电连接；
其中，所述第一封装结构与所述第二封装结构60之间存在空隙。
本公开实施例中，通过在芯片堆叠结构上设置第一导电块，通过第一导电块将独立的第一封装结构和第二封装结构连接，因此第一导电块就起到中介的作用，不需要额外使用其他中介结构进行连接，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。并且第二封装结构与第一封装结构之间存在空隙，由此增加了二者之间的间距，从而能提高第二封装结构的散热效率，减少热量对芯片的影响。
在一实施例中，所述第一封装结构还包括：基板10，所述基板10包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案14和第二导电图案15；
所述基板10还包括位于所述上表面和所述下表面之间的信号通道16，所述信号通道16连接所述第一导电图案14和所述第二导电图案15。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体 上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
所述第一导电图案14位于所述基板上绝缘介质层12内，所述第二导电图案15位于所述基板下绝缘介质层13内，所述信号通道16位于所述基板衬底11内，并贯穿所述基板衬底11。
所述第一导电图案14和所述第二导电图案15可以为连接焊盘，且所述第一导电图案14和所述第二导电图案15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述信号通道16可以为穿硅通孔(TSV)。
第一导电图案14与第二导电图案15通过信号通道16连接，从而能够让信号进行传输。同时，相邻的两个第一导电图案14还可以通过重布线层连接，从而能够完成信号在基板上的传输。
所述基板10还包括基板连接凸块17，所述基板连接凸块17可将半导体封装结构电连接到外部装置上，可以从外部装置接收用于操作芯片堆叠结构的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在芯片堆叠结构内的数据信号，也可将芯片堆叠结构内的数据提供给外部装置。
所述基板连接凸块17包括导电材料。在本公开实施例中，所述基板连接凸块17为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
图2为本公开另一实施例提供的半导体封装结构的结构示意图。在本公开实施例中，所述第一芯片和所述第二芯片以及基板之间的连接方式有两种，一种是如图1所示，使用粘结层进行连接，另一种是如图2所示，使用第一导电块、第二导电块和第一信号孔进行连接。
在图1所示的实施例中，所述芯片堆叠结构20包括：
第一芯片21，设置在所述基板10上；
第二芯片22，偏移地设置在所述第一芯片21上；
其中，所述第一芯片21和所述第二芯片22分别通过引线40连接所述基板10，所述引线40位于所述芯片堆叠结构20的同侧。由于第二芯片22偏移地设置在第一芯片21上，由此打线更加方便。
所述第一芯片21和所述第二芯片22可以为动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或电阻随机存取存储器(RRAM)芯片。
所述第一芯片21通过粘结层50设置在所述基板10上，所述基板10还包括虚拟通道18，所述粘结层50位于所述虚拟通道18上，且所述虚拟通道18的导热系数大于所述粘结层50的导热系数。
所述粘结层50可以为DAF膜。
在一实施例中，如图6所示，所述粘结层包括第一粘结层51和位于所述第一粘结层51上的第二粘结层52，所述第二粘结层52的弹性模量大于所述第一粘结层51的弹性模量。
本公开实施例中，因为第一粘结层主要起到粘结的作用，第二粘结层主要起到防止芯片翘曲的作用，由于第二粘结层的弹性模量较高，在切割过程中不会出现翘曲，第一粘结层具有较低的弹性模量，在后续的工艺中不会影响基板与芯片的结合力。
本公开实施例中，虚拟通道的导热系数大于粘结层的导热系数，能够将芯片工作产生的热量通过虚拟通道散发出去，减少对器件性能的影响。
所述虚拟通道18为第一导电图案14、第二导电图案15和信号通道16组成，但是虚拟通道18的下方不形成基板连接凸块17，无法实现信号传输，仅用作散热处理。
在一些实施例中，虚拟通道的导热系数比其他作为信号传输作用的第一导电图案14、第二导电图案15和信号通道16组成的结构的导热系数大，能够减少热量对信号传输的影响。
在一实施例中，所述引线40连接至同一所述第一导电图案14上。
在一实施例中，所述塑封料30覆盖所述引线40。塑封料覆盖住引线，能够保证引线处于密封绝缘状态，不与空气中的氧气或其他物质发生反应，而影响器件的性能。
在图1所示的实施例中，所述第一导电块201的顶面低于所述塑封料30的顶面。由于第一导电块的顶面比塑封料的顶面低，因此形成一个凹槽，后续，第二封装结构可放置于该凹槽内，以减少器件结构的高度。
在一实施例中，所述第二封装结构60通过第一焊球61设置在所述第一导电块201上，且所述第一焊球61突出于所述塑封料30。
具体地，如图1所示，所述第一导电块201的顶面至所述塑封料30的顶面的高度为h，所述第一焊球61的高度为H，其中，所述第一焊球61的高度H大于所述第一导电块201的顶面至所述塑封料30的顶面的高度h。
通过设置第一焊球的高度大于第一导电块的顶面至塑封料的顶面的高度，可以使得第一焊球与第一导电块的接触更加紧密，同时又使得第一封装结构与第二封装结构之间能存在空隙，由此增加了二者之间的间距，从而提高第二封装结构的散热效率，减小散热对芯片的影响。否则，如果第一焊球的高度小于第一导电块的顶面至塑封料的顶面的高度，会导致第一焊球与第一导电块无法接触，影响器件性能。
所述第二封装结构还包括第二基板62，所述第二基板62的结构与所述 基板10的结构相同，这里不再赘述。
所述第二封装结构可以为通用闪存存储(Universal File Store，UFS)。
在一实施例中，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角大于或等于0°，且小于90°。
例如，如图1所示，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角为0°，即塑封料30的顶面和所述第二芯片22的顶面之间的侧壁垂直于所述基板10。在此实施例中，将塑封料的侧壁设置成垂直形状，工艺更加简单。
如图3所示，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角a大于0°，且小于90°。在此实施例中，将塑封料的侧壁设置成非垂直形状，如此，可以更加方便后续与第二封装结构的互连。
在图2所示的实施例中，所述芯片堆叠结构包括：
多个芯片，所述芯片包括相对设置的第一表面210和第二表面220，所述第一导电块201位于所述第一表面210上，所述第二表面220上设置有第二导电块202；所述第一导电块201和所述第二导电块202通过第一信号孔203连接。
所述第一导电块201和所述第二导电块202的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述第一信号孔203可以为穿硅通孔(TSV)。
在一实施例中，所述芯片堆叠结构20中最底部的所述第二导电块202通过第二焊球204连接所述第一导电图案14，相邻两个所述芯片之间通过第二焊球204连接。
如图2所示，所述芯片堆叠结构20可以包括第一芯片21和第二芯片22。所述第一芯片21和所述第二芯片22之间通过位于所述第二芯片22的第二表面220上的第二导电块202、位于所述第一芯片21的第一表面210上的第一导电块201，以及第一导电块201和第二导电块202之间的第二焊球204进行连接。
在此实施例中，第一芯片和第二芯片与基板之间不需要通过打线进行电连接，由此可以减少打线工艺。同时由于第一芯片和第二芯片之间的信号路径变小，也可以降低信号损耗。
所述基板10还包括虚拟通道18，所述第二焊球204通过所述虚拟通道18连接至所述第二导电图案15。
在一实施例中，所述塑封料30还位于相邻两个所述芯片之间。塑封料位于相邻两个芯片之间，即塑封料完全包裹芯片堆叠结构，能使芯片堆叠结构绝缘隔离。
在一实施例中，所述第一导电块201与所述塑封料30共面。
具体地，如图2所示，所述第二芯片22上的第一导电块201的顶面与所述塑封料30的顶面共面，本公开实施例中，因为最终形成的塑封料与第 一导电块共面，所以在形成塑封料的过程中，不需要用到异形模具，只需要使用形状正常的模具，而形状正常的模具因为形状简单，所以制作工艺简单，成本较低。
并且所述塑封料与所述第一导电块共面，这样后续第二封装结构与第一封装结构连接后，使得第一封装结构和第二封装结构之间能够具有较大的空隙，保证了第二封装结构的散热效率。
如果塑封料的表面高于第一导电块的表面，则使得第一封装结构和第二封装结构之间的空隙减小，不利于散热，同时在后续形成填充层时，不利于填充层的填充；如果第一导电块的表面高于塑封料的表面，虽然可以增加空隙，但是可能导致塑封料无法完全覆盖第一导电块下方的芯片，导致芯片裸露，不利于保护芯片。
图4和图5为本公开又一实施例提供的半导体封装结构的结构示意图。
如图4和图5所示，所述半导体封装结构还包括填充层70，所述填充层70填满所述空隙。
所述填充层70的导热系数大于所述塑封料30的导热系数。
通过设置填充层，不仅可以使第一封装结构和第二封装结构之间具有密封的界面，减少第一封装结构和第二封装结构的金属结构与外界空气或其他材料的接触，而且可以起到导热作用。并且由于填充层的导热系数较大，这样更多的热量能够从填充层散失掉，减少热量对第一封装结构的影响。同时由于填充层与第一封装结构和第二封装结构的热膨胀系数匹配，这样填充层的体积变化较小，不会对第一封装结构和第二封装结构产生向外的压力，能够保证结构的稳定性。
所述填充层70中的填料体积小于所述塑封料30的填料体积。
如图4和图5所示，所述塑封料30中的填料为第一填料301，所述填充层70中的填料为第二填料701，第二填料701的体积小于第一填料301的体积。
所述塑封料30和所述填充层70的主体材料可以为环氧树脂，填料可以为二氧化硅粉。
在此实施例中，由于塑封料填充的空隙较大，而第一封装结构和第二封装结构之间的空隙较小，由此选择流动性较大的填充层，填充层中的填料体积小，主体材料的流动性大。
本公开实施例提供的半导体封装结构可应用于叠层封装(Package on Package，PoP)结构的多制程封装芯片(UFS Multi Chip Package，UMCP)。
本公开实施例还提供了一种半导体封装结构的制备方法，具体请参见图7，如图所示，所述方法包括以下步骤：
步骤701：提供第一封装结构，所述第一封装结构包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；
步骤702：提供第二封装结构，将第二封装结构设置在所述芯片堆叠结构上，所述第二封装结构与所述第一导电块电连接；其中，所述第一封装结构与所述第二封装结构之间存在间隙。
下面结合具体实施例对本公开实施例提供的半导体封装结构的制备方法作进一步详细的说明。
图8a至图8f为本公开实施例提供的半导体封装结构在制备过程中的结构示意图，图9a至图9c为本公开另一实施例提供的半导体封装结构在制备过程中的结构示意图，需要解释的是，图8a至图8f所示的实施例和图9a至图9c所示的实施例，只有芯片堆叠结构和塑封料的结构不同，其他结构均相同。
先对图8a至图8f所示的实施例进行详细的描述。
首先，参见图8a至图8d，执行步骤701，提供第一封装结构，所述第一封装结构包括芯片堆叠结构20和塑封料30，所述芯片堆叠结构20上设置有第一导电块201，所述塑封料30包裹所述芯片堆叠结构20，并暴露所述第一导电块201。
具体地，先参见图8a，提供基板10。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
所述基板10还包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案14和第二导电图案15；所述第一导电图案14位于所述基板上绝缘介质层12内，所述第二导电图案15位于所述基板下绝缘介质层13内，所述信号通道16位于所述基板衬底11内，并贯穿所述基板衬底11。
所述第一导电图案14和所述第二导电图案15可以为连接焊盘，且所述第一导电图案14和所述第二导电图案15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述信号通道16可以为穿硅通孔(TSV)。
第一导电图案14与第二导电图案15通过信号通道16连接，从而能够 让信号进行传输。同时，相邻的两个第一导电图案14还可以通过重布线层连接，从而能够完成信号在基板上的传输。
所述基板10还包括虚拟通道18。所述虚拟通道18为第一导电图案14、第二导电图案15和信号通道16组成，但是虚拟通道18的下方不形成基板连接凸块17，无法实现信号传输，仅用作散热处理。
在一些实施例中，虚拟通道的导热系数比其他作为信号传输作用的第一导电图案14、第二导电图案15和信号通道16组成的结构的导热系数大，能够减少热量对信号传输的影响。
接着，参见图8b和图8c，在所述基板10上形成芯片堆叠结构20。
具体地，先参见图8b，在圆环1上粘贴载带2，在载带2上贴上粘结层50，然后将芯片堆叠结构中最上层的芯片粘贴在粘结层50上，切割后形成为分立的芯片。
接着，参见图8c，将切割后的芯片放置到基板10上。
具体地，在所述基板10上形成粘结层50，在粘结层50上形成芯片堆叠结构20。
所述粘结层50可以为DAF膜。
在一实施例中，如图6所示，所述粘结层包括第一粘结层51和位于所述第一粘结层51上的第二粘结层52，所述第二粘结层52的弹性模量大于所述第一粘结层51的弹性模量。
本公开实施例中，因为第一粘结层主要起到粘结的作用，第二粘结层主要起到防止芯片翘曲的作用，由于第二粘结层的弹性模量较高，在切割过程中不会出现翘曲，第一粘结层具有较低的弹性模量，在后续的工艺中不会影响基板与芯片的结合力。
所述粘结层50位于所述虚拟通道18上，且所述虚拟通道18的导热系数大于所述粘结层50的导热系数。本公开实施例中，虚拟通道的导热系数大于粘结层的导热系数，能够将芯片工作产生的热量通过虚拟通道散发出去，减少对器件性能的影响。
所述形成芯片堆叠结构20包括：在所述粘结层50上形成第一芯片21，在所述第一芯片21上形成第二芯片22，其中，所述第一芯片21与所述第二芯片22偏移设置。
所述第一芯片21和所述第二芯片22之间也通过粘结层50连接。
继续参见图8c，进行打线。
具体地，所述第一芯片21和所述第二芯片22分别通过引线40连接所述基板10，所述引线40位于所述芯片堆叠结构20的同侧。
在一实施例中，所述引线40连接至同一所述第一导电图案14上。
接着，参见图8d，形成包裹所述芯片堆叠结构20的塑封料30，所述塑封料30暴露所述第一导电块201。
在一实施例中，所述塑封料30覆盖所述引线40。塑封料覆盖住引线， 能够保证引线处于密封绝缘状态，不与空气中的氧气或其他物质发生反应，而影响器件的性能。
所述第一导电块201的顶面低于所述塑封料30的顶面。由于第一导电块的顶面比塑封料的顶面低，因此形成一个凹槽，后续，第二封装结构可放置于该凹槽内，以减少器件结构的高度。
在一实施例中，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角大于或等于0°，且小于90°。
例如，如图8d所示，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角为0°，即塑封料30的顶面和所述第二芯片22的顶面之间的侧壁垂直于所述基板10。在此实施例中，将塑封料的侧壁设置成垂直形状，工艺更加简单。
如图3所示，所述塑封料30的顶面和所述第二芯片22的顶面之间的侧壁与垂直于所述基板10方向的夹角a大于0°，且小于90°。在此实施例中，将塑封料的侧壁设置成非垂直形状，如此，可以更加方便后续与第二封装结构的互连。
继续参见图8d，在形成塑封料30后，在所述基板10的第二导电图案15上形成基板连接凸块17，所述基板连接凸块17包括导电材料。
接着，参见图8e，执行步骤702，提供第二封装结构60，将第二封装结构60设置在所述芯片堆叠结构20上，所述第二封装结构20与所述第一导电块201电连接；其中，所述第一封装结构与所述第二封装结构60之间存在间隙。
具体的，在所述第二封装结构60上形成第一焊球61，所述第一焊球61与所述第一导电块201电连接，且所述第一焊球61突出于所述塑封料30。
如图8e所示，所述第一导电块201的顶面至所述塑封料30的顶面的高度为h，所述第一焊球61的高度为H，其中，所述第一焊球61的高度H大于所述第一导电块201的顶面至所述塑封料30的顶面的高度h。
通过设置第一焊球的高度大于第一导电块的顶面至塑封料的顶面的高度，可以使得第一焊球与第一导电块的接触更加紧密，同时又使得第一封装结构与第二封装结构之间能存在空隙，由此增加了二者之间的间距，从而提高第二封装结构的散热效率，减小散热对芯片的影响。否则，如果第一焊球的高度小于第一导电块的顶面至塑封料的顶面的高度，会导致第一焊球与第一导电块无法接触，影响器件性能。
所述第二封装结构还包括第二基板62，所述第二基板62的结构与所述基板10的结构相同，这里不再赘述。
所述第一焊球61位于所述第二基板62上。
接着，参见图8f，在所述第一封装结构和所述第二封装60之间的空隙内形成填充层70。
所述填充层70的导热系数大于所述塑封料30的导热系数。
通过设置填充层，不仅可以使第一封装结构和第二封装结构之间具有密封的界面，减少第一封装结构和第二封装结构的金属结构与外界空气或其他材料的接触，而且可以起到导热作用。并且由于填充层的导热系数较大，这样更多的热量能够从填充层散失掉，减少热量对第一封装结构的影响。虽然填充层的导热系数较大，但是由于填充层的体积较小，这样填充层的体积变化较小，不会对第一封装结构和第二封装结构产生向外的压力，能够保证结构的稳定性。
所述填充层中的填料体积小于所述塑封料的填料体积。
如图8f所示，所述塑封料30中的填料为第一填料301，所述填充层70中的填料为第二填料701，第二填料701的体积小于第一填料301的体积。
所述塑封料30和所述填充层70的主体材料可以为环氧树脂，填料可以为二氧化硅。
在此实施例中，由于塑封料填充的空隙较大，而第一封装结构和第二封装结构之间的空隙较小，由此选择流动性较大的填充层，填充层中的填料体积小，主体材料的流动性大。
接下来，对图9a至图9c所示的实施例进行详细的描述。
首先，参见图9a，在所述基板10上形成芯片堆叠结构20。需要解释的是，本实施例中的基板与图8a至图8e所示的实施例中的基板相同，这里不再赘述。
所述芯片堆叠结构20包括多个芯片，所述芯片包括相对设置的第一表面210和第二表面220，在所述第一表面210形成第一导电块201，在所述第二表面220上形成第二导电块202；所述第一导电块201和所述第二导电块202通过第一信号孔203连接。
所述第一导电块201和所述第二导电块202的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述第一信号孔203可以为穿硅通孔(TSV)。
所述芯片堆叠结构20中最底部的所述第二导电块202通过第二焊球204连接所述第一导电图案14，相邻两个所述芯片之间通过第二焊球204连接。
具体的，如图9a所示，所述芯片堆叠结构20包括第一芯片21和第二芯片22。所述第一芯片21和所述第二芯片22之间通过位于所述第二芯片22的第二表面220上的第二导电块202、位于所述第一芯片21的第一表面210上的第一导电块201，以及第一导电块201和第二导电块之间的第二焊球204进行连接。
在此实施例中，第一芯片和第二芯片与基板之间不需要通过打线进行电连接，由此可以减少打线工艺。
接着，参见图9b，形成包裹所述芯片堆叠结构20的塑封料30。
所述塑封料30还位于相邻两个所述芯片之间。塑封料位于相邻两个芯 片之间，即塑封料完全包裹芯片堆叠结构，能使芯片堆叠结构绝缘隔离。
在一实施例中，所述第一导电块201与所述塑封料30共面。
具体地，如图9b所示，所述第二芯片22上的第一导电块201的顶面与所述塑封料30的顶面共面，本公开实施例中，因为最终形成的塑封料与第一导电块共面，所以在形成塑封料的过程中，不需要用到异形模具，只需要使用形状正常的模具，而形状正常的模具因为形状简单，所以制作工艺简单，成本较低。
并且所述塑封料与所述第一导电块共面，这样后续第二封装结构与第一封装结构连接后，使得第一封装结构和第二封装结构之间能够具有较大的空隙，保证了第二封装结构的散热效率。
如果塑封料的表面高于第一导电块的表面，则使得第一封装结构和第二封装结构之间的空隙减小，不利于散热，同时在后续形成填充层时，不利于填充层的填充；如果第一导电块的表面高于塑封料的表面，虽然可以增加空隙，但是可能导致塑封料无法覆盖第一导电块下方的芯片，导致芯片裸露，不利于保护芯片。
接着，参见图9c，在所述第一封装结构上形成第二封装结构60。需要解释的是，本实施例中在形成第二封装结构之后的步骤，与8a至8e所示的实施例中形成第二封装结构之后的步骤相同，这里不再赘述。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，通过在芯片堆叠结构上设置第一导电块，通过第一导电块将独立的第一封装结构和第二封装结构连接，因此第一导电块就起到中介的作用，不需要额外使用其他中介结构进行连接，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。并且第二封装结构与第一封装结构之间存在空隙，由此增加了二者之间的间距，从而能提高第二封装结构的散热效率，减少热量对芯片的影响。

Claims (18)

  1. 一种半导体封装结构，包括：
    第一封装结构，包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；
    第二封装结构，设置在所述芯片堆叠结构上，与所述第一导电块电连接；
    其中，所述第一封装结构与所述第二封装结构之间存在空隙。
  2. 根据权利要求1所述的半导体封装结构，其中，所述第一封装结构还包括：
    基板，所述基板包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案和第二导电图案；
    所述基板还包括位于所述上表面和所述下表面之间的信号通道，所述信号通道连接所述第一导电图案和所述第二导电图案。
  3. 根据权利要求2所述的半导体封装结构，其中，所述芯片堆叠结构包括：
    第一芯片，设置在所述基板上；
    第二芯片，偏移地设置在所述第一芯片上；
    其中，所述第一芯片和所述第二芯片分别通过引线连接所述基板，所述引线位于所述芯片堆叠结构的同侧。
  4. 根据权利要求3所述的半导体封装结构，其中，所述引线连接至同一所述第一导电图案上。
  5. 根据权利要求3所述的半导体封装结构，其中，所述塑封料覆盖所述引线。
  6. 根据权利要求1所述的半导体封装结构，其中，所述第一导电块的顶面低于所述塑封料的顶面。
  7. 根据权利要求6所述的半导体封装结构，其中，所述第二封装结构通过第一焊球设置在所述第一导电块上，且所述第一焊球突出于所述塑封料。
  8. 根据权利要求1-2任一所述的半导体封装结构，其中，所述芯片堆叠结构包括：
    多个芯片，所述芯片包括相对设置的第一表面和第二表面，所述第一导电块位于所述第一表面上，所述第二表面上设置有第二导电块；所述第一导电块和所述第二导电块通过第一信号孔连接。
  9. 根据权利要求8所述的半导体封装结构，其中，所述芯片堆叠结构中最底部的所述第二导电块通过第二焊球连接所述第一导电图案，相邻两个所述芯片之间通过第二焊球连接。
  10. 根据权利要求8所述的半导体封装结构，其中，所述塑封料还位于相邻两个所述芯片之间。
  11. 根据权利要求1所述的半导体封装结构，其中，所述第一导电块与所述塑封料共面。
  12. 根据权利要求1所述的半导体封装结构，其中，还包括填充层，所述填充层填满所述空隙。
  13. 根据权利要求12所述的半导体封装结构，其中，所述填充层的导热系数大于所述塑封料的导热系数。
  14. 根据权利要求12所述的半导体封装结构，其中，所述填充层中的填料体积小于所述塑封料的填料体积。
  15. 根据权利要求3所述的半导体封装结构，其中，所述第一芯片通过粘结层设置在所述基板上，所述基板还包括虚拟通道，所述粘结层位于所述虚拟通道上，且所述虚拟通道的导热系数大于所述粘结层的导热系数。
  16. 根据权利要求9所述的半导体封装结构，其中，所述基板还包括虚拟通道，所述第二焊球通过所述虚拟通道连接至所述第二导电图案。
  17. 根据权利要求15所述的半导体封装结构，其中，所述粘结层包括第一粘结层和第二粘结层，所述第二粘结层位于所述第一粘结层上，所述第一粘结层的弹性模量小于所述第二粘结层的弹性模量。
  18. 一种半导体封装结构的制备方法，包括：
    提供第一封装结构，所述第一封装结构包括芯片堆叠结构和塑封料，所述芯片堆叠结构上设置有第一导电块，所述塑封料包裹所述芯片堆叠结构，并暴露所述第一导电块；
    提供第二封装结构，将第二封装结构设置在所述芯片堆叠结构上，所述第二封装结构与所述第一导电块电连接；
    其中，所述第一封装结构与所述第二封装结构之间存在间隙。
PCT/CN2022/115802 2022-07-08 2022-08-30 半导体封装结构及制备方法 WO2024007431A1 (zh)

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