WO2024031812A1 - 一种半导体封装结构及其制备方法 - Google Patents

一种半导体封装结构及其制备方法 Download PDF

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Publication number
WO2024031812A1
WO2024031812A1 PCT/CN2022/123768 CN2022123768W WO2024031812A1 WO 2024031812 A1 WO2024031812 A1 WO 2024031812A1 CN 2022123768 W CN2022123768 W CN 2022123768W WO 2024031812 A1 WO2024031812 A1 WO 2024031812A1
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Prior art keywords
semiconductor chip
substrate
semiconductor
conductive bump
stack structure
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PCT/CN2022/123768
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English (en)
French (fr)
Inventor
吕开敏
庄凌艺
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长鑫存储技术有限公司
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Priority to US18/451,060 priority Critical patent/US20240055408A1/en
Publication of WO2024031812A1 publication Critical patent/WO2024031812A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • the present disclosure relates to the field of three-dimensional process technology, and in particular, to a semiconductor packaging structure and a preparation method thereof.
  • HBM memory High Bandwidth Memory
  • 3D stacking technology 3D stacking technology.
  • HBM memory has higher bandwidth, more I/O numbers, lower power consumption, and smaller size. It can be used in high-performance computing, supercomputers, large data centers, artificial intelligence/deep learning, cloud computing and other fields.
  • HBM memory technology was mainly developed based on the demand for processor computing scale.
  • people did not have high requirements for computer data processing.
  • the number of processor architecture model layers was small, the computing scale was small, and the computing power was low; later
  • the requirements for processors are getting higher and higher, and the demand for computing power increases accordingly when the model is deepened, resulting in a bandwidth bottleneck, that is, an I/O problem.
  • data is increased by increasing the on-chip cache and optimizing the scheduling model.
  • the popularization of AI and other technologies in the later period the number of users increased, and cloud AI processing required multi-user, high throughput, low latency, and high-density deployment.
  • embodiments of the present disclosure provide a semiconductor packaging structure and a manufacturing method thereof.
  • a semiconductor packaging structure including:
  • a first semiconductor chip connected to the first substrate
  • a second semiconductor chip stack structure is located on the first semiconductor chip; the second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked sequentially along the first direction; the second semiconductor chip stack structure is located along the first direction.
  • a plurality of second conductive bumps are formed on one side of one direction; wherein the first direction is a direction parallel to the plane of the first substrate;
  • a second substrate, the signal line in the second substrate is connected to the second conductive bump; the second substrate is connected to the first substrate in a direction perpendicular to the plane of the first substrate.
  • the first semiconductor chip includes a logic chip and the second semiconductor chip stack includes a DRAM chip.
  • it also includes:
  • An adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure.
  • the adhesive film includes a first adhesive film and a second adhesive film located on the first adhesive film, and the elastic modulus of the second adhesive film is greater than that of the first adhesive film.
  • the elastic modulus of the adhesive film is greater than that of the first adhesive film.
  • communication between the first semiconductor chip and the second semiconductor chip stack structure is performed wirelessly.
  • a groove is formed in the first substrate, the first semiconductor chip is located in the groove, and the first semiconductor chip and the first substrate are connected through a first conductive bump, The second substrate and the first substrate are connected through third conductive bumps.
  • the first semiconductor chip is located on the first substrate, the first semiconductor chip and the first substrate are connected through a first conductive bump, and the second substrate is connected to the first substrate.
  • the substrates are connected through third conductive bumps.
  • it also includes:
  • a plurality of through silicon vias penetrating the second semiconductor chip along the first direction;
  • a plurality of fourth conductive bumps are located between two adjacent second semiconductor chips and are correspondingly connected to the through silicon vias;
  • the second conductive bump is correspondingly connected to the through silicon via and the fourth conductive bump.
  • the signal line includes a ground line and a power line
  • the second conductive bump includes a first sub-conductive bump and a second sub-conductive bump
  • the ground line is electrically connected to the first sub-conductive bump, and the power line is electrically connected to the second sub-conductive bump.
  • At least one first sub-conductive bump is spaced between two adjacent second sub-conductive bumps, and the first sub-conductive bump surrounds the second sub-conductive bump.
  • it also includes:
  • a filling layer is located between the second semiconductor chip stack structure and the second substrate, and/or between the first semiconductor chip, the second substrate, and the first substrate.
  • it also includes:
  • the packaging compound structure located on the first substrate; the packaging compound structure at least wraps the second semiconductor chip stack structure and the second substrate;
  • the Young's modulus of the filling layer is greater than the Young's modulus of the encapsulating compound structure.
  • a method for manufacturing a semiconductor packaging structure as described in any of the above embodiments including:
  • the second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked in sequence; forming a plurality of second conductive bumps on one side of the second semiconductor chip stack structure along the stacking direction piece;
  • a second substrate is provided; the second substrate is located on one side of the second semiconductor chip stack structure where the second conductive bump is formed along the stacking direction, and the signal lines in the second substrate are connected to the second conductive bump. connect;
  • a first substrate is provided; the first semiconductor chip is connected to the first substrate, and the second substrate is connected to the first substrate.
  • forming the second semiconductor chip stack structure includes:
  • a fourth conductive bump is formed between two adjacent second semiconductor chips, and the fourth conductive bump is correspondingly connected to the through silicon via;
  • the second semiconductor chip stack is formed into a plurality of second semiconductor chip stack structures.
  • providing the second substrate includes: cutting the second substrate, forming a third conductive bump on the second substrate, forming the third conductive bump on the second substrate.
  • a surface of the block is flush with a surface of the second semiconductor chip stack close to the first semiconductor chip.
  • forming a groove in the first substrate forming a groove in the first substrate
  • the first semiconductor chip is placed in the groove.
  • it also includes:
  • an adhesive film is formed on the first semiconductor chip, and the second semiconductor chip stack structure and the first semiconductor chip are connected through the adhesive film.
  • communication between the first semiconductor chip and the second semiconductor chip stack structure is performed wirelessly.
  • it also includes:
  • a plurality of second semiconductor chips in the second semiconductor chip stack structure are vertically stacked (V-Stacked) on the first semiconductor chip in parallel.
  • the first semiconductor chip and the second semiconductor chip can be connected by Wireless communication can effectively solve the communication difficulties caused by the increase in the number of stacked layers of second semiconductor chips when multiple second semiconductor chips are sequentially stacked in parallel (P-Stack) on the first semiconductor chip.
  • the first substrate supplies power to the first semiconductor chip and the second semiconductor chip stack structure in a wired manner, and simultaneously exchanges signals with the first semiconductor chip, which has high reliability.
  • Figure 1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure.
  • Figure 3 is a side view along the first direction of the second conductive bump provided by the embodiment of the present disclosure.
  • 4a and 4b are schematic structural diagrams of a semiconductor packaging structure provided by yet another embodiment of the present disclosure.
  • Figure 5 is a schematic flowchart of a method for preparing a semiconductor packaging structure provided by an embodiment of the present disclosure
  • 6a to 6h are schematic diagrams of device structures during the preparation process of the semiconductor packaging structure provided by embodiments of the present disclosure.
  • 30-second semiconductor chip stack structure 300-second semiconductor chip stack; 31-second semiconductor chip; 311-through silicon via; 312-fourth conductive bump; 32-second conductive bump; 321-th One sub-conductive bump; 322-the second sub-conductive bump;
  • HBM technology is the main representative product of the development of DRAM from traditional 2D to three-dimensional 3D, opening the road to 3D DRAM. It mainly stacks chips through Through Silicon Via (TSV) technology to increase throughput and overcome bandwidth limitations within a single package. Several DRAM dies are stacked vertically, and the dies are connected using TVS technology. From a technical perspective, HBM makes full use of space and reduces area, which is in line with the development trend of miniaturization and integration in the semiconductor industry. It also breaks through the bottlenecks of memory capacity and bandwidth and is regarded as a new generation DRAM solution.
  • TSV Through Silicon Via
  • DRAM chips are generally stacked on logic chips (Logic die) in parallel stacking (P-Stack).
  • P-Stack logic chips
  • the communication distance between the DRAM chips stacked on the upper layer and the underlying logic die is getting longer and longer, and the communication delays between DRAM chips and logic chips on different layers will occur due to the difference in distance. Difference; TSV through holes used for communication will increase proportionally, sacrificing wafer area.
  • FIG. 1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure.
  • the semiconductor packaging structure includes:
  • the first semiconductor chip 20 is connected to the first substrate 10;
  • the second semiconductor chip stack structure 30 is located on the first semiconductor chip 20; the second semiconductor chip stack structure 30 includes a plurality of second semiconductor chips 31 sequentially stacked along the first direction; the second semiconductor chip stack The structure 30 is formed with a plurality of second conductive bumps 32 on one side along the first direction; wherein the first direction is a direction parallel to the plane of the first substrate 10;
  • the second substrate 40 , the signal line 41 in the second substrate 40 is connected to the second conductive bump 32 ; along the direction perpendicular to the plane of the first substrate 10 , the second substrate 40 is connected to the second conductive bump 32 .
  • the first substrate 10 is connected.
  • a plurality of second semiconductor chips in the second semiconductor chip stack structure are vertically stacked (V-Stacked) on the first semiconductor chip in parallel.
  • the first semiconductor chip and the second semiconductor chip can be connected by Wireless communication can effectively solve the communication difficulties caused by the increase in the number of stacked layers of second semiconductor chips when multiple second semiconductor chips are sequentially stacked in parallel (P-Stack) on the first semiconductor chip.
  • the first substrate supplies power to the first semiconductor chip and the second semiconductor chip stack structure in a wired manner, and simultaneously exchanges signals with the first semiconductor chip, which has high reliability.
  • the first substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the first substrate 10 may include a first base (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) respectively located on the upper surface and lower surface of the first base. .
  • the first substrate may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate. etc., it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure. , such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the first upper insulating dielectric layer and the first lower insulating dielectric layer may be solder resist layers.
  • the material of the first upper insulating dielectric layer and the first lower insulating dielectric layer may be green paint.
  • a substrate connection bump 12 is formed on the lower surface of the first substrate 10.
  • the substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, and can receive from the external device a component used to operate the first semiconductor chip and At least one of the control signal, power signal and ground signal of the second semiconductor chip, or a data signal to be stored in the first semiconductor chip and the second semiconductor chip may be received from an external device, or the first semiconductor chip and the The data in the second semiconductor chip is provided to the external device.
  • the substrate connection bumps 12 include conductive material.
  • the substrate connection bumps 12 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only a lower and feasible shape in the embodiment of the present disclosure. The specific implementation of the invention does not constitute a limitation of the present disclosure, and the substrate connection bumps can also be of other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.
  • first conductive bumps 21 are formed on one side of the first semiconductor chip 20 .
  • the material of the first conductive bump 21 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the first semiconductor chip 20 and the first substrate 10 are electrically connected through first conductive bumps 21 .
  • the first substrate 10 supplies power to the first semiconductor chip through wires and performs signal exchange.
  • the first conductive bumps 21 are also connected to the substrate connection bumps 12 through the leads 11 in the first substrate 10 . In this way, the first semiconductor chip 20 can exchange information with external devices through the substrate connection bumps 12 .
  • a groove 101 is formed in the first substrate 10 , the first semiconductor chip 20 is located in the groove 101 , and the first semiconductor chip 20 is connected to the groove 101 .
  • the first substrate 10 is connected through the first conductive bumps 21 , and the second substrate 40 and the first substrate 10 are connected through the third conductive bumps 42 .
  • placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor packaging structure.
  • the first semiconductor chip 20 is located on the first substrate 10 , and the first semiconductor chip 20 and the first substrate 10 pass through the first conductive bump 21 The second substrate 40 and the first substrate 10 are connected through third conductive bumps 42 .
  • the first semiconductor chip is located above the first substrate.
  • the first substrate does not need to be provided with a groove, so the process is simpler, and there is a gap between the first semiconductor chip and the first substrate, which can increase the number of first semiconductor chips.
  • the heat dissipation effect of semiconductor chips is described below.
  • the number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 may be multiple. In the embodiment of the present disclosure, as shown in FIG. 1 , the number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 is five.
  • the first semiconductor chip 20 includes a logic chip
  • the second semiconductor chip stack structure 30 includes a DRAM chip.
  • the semiconductor packaging structure further includes an adhesive film 50 located between the first semiconductor chip 20 and the second semiconductor chip stack structure 30 .
  • the adhesive film 50 can adhere the first semiconductor chip 20 and the second semiconductor chip stack structure 30 to enhance the adhesion between them, thereby improving the firmness of the semiconductor packaging structure.
  • the adhesive film can adjust the distance between the second semiconductor chip stack structure and the first semiconductor chip, that is, prevent the angle between the second substrate and the second conductive block from causing additional stress, so that the second semiconductor chip stack structure on the second semiconductor chip stack structure has an angle. Two conductive blocks are damaged.
  • the adhesive film 50 includes a die-hardening adhesive film.
  • the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, and the elastic modulus of the second adhesive film is greater than the elastic modulus of the first adhesive film.
  • the first adhesive film is connected to the first semiconductor chip, it mainly plays a bonding role, and the second adhesive film is connected to the second semiconductor chip stack structure, and mainly plays a role in preventing the chip from warping.
  • the second adhesive film since the second adhesive film has a higher elastic modulus, it will not warp during the packaging process.
  • the first adhesive film has a lower elastic modulus, which will not affect the connection between the first semiconductor chip and the first semiconductor chip in the subsequent process.
  • the bonding force of the second semiconductor chip stack structure since the second adhesive film has a higher elastic modulus, it will not warp during the packaging process.
  • the first adhesive film has a lower elastic modulus, which will not affect the connection between the first semiconductor chip and the first semiconductor chip in the subsequent process.
  • the first semiconductor chip 20 and the second semiconductor chip stack structure 30 communicate through wireless communication.
  • a wireless coil is provided in each DRAM in the second semiconductor chip stack structure 30 ( (not shown), correspondingly, corresponding wireless coils are provided at the above-mentioned coil corresponding positions on the first semiconductor chip 20 .
  • Wireless communication between the first semiconductor chip and the second semiconductor chip stack structure can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip, while reducing the number of TSVs and reducing the Process difficulty.
  • the semiconductor packaging structure further includes: a plurality of through silicon vias 311 penetrating the second semiconductor chip 31 along the first direction; a plurality of third through silicon vias 311 .
  • Four conductive bumps 312 are located between two adjacent second semiconductor chips 31 and are correspondingly connected to the through silicon holes 311; the second conductive bumps 32 are connected to the through silicon holes 311 and the through silicon holes 311.
  • the fourth conductive bumps 312 are connected correspondingly.
  • subsequent power signals and ground signals can be led to the second conductive bump through the through silicon via and the fourth conductive bump.
  • Two adjacent second semiconductor chips in the second semiconductor chip stack structure are electrically connected through through silicon vias and a fourth conductive block.
  • the second semiconductor chip stack structure is obtained by hybrid bonding. In this way, the stacked chip structure can be treated as a whole, thereby improving the mechanical strength of the vertically placed stack structure and reducing the pressure on the chip.
  • the semiconductor packaging structure further includes: a dielectric layer 60 located between two adjacent second semiconductor chips 31 .
  • a dielectric layer 60 located between two adjacent second semiconductor chips 31 .
  • the material of the dielectric layer 60 includes oxide. In a specific embodiment, the material of the dielectric layer 60 includes SiO 2 .
  • the material and structure of the second substrate 40 may be the same as those of the first substrate 10 , and therefore will not be described again here.
  • the signal line 41 includes a ground line 411 and a power line 412
  • the second conductive bump 32 includes a first sub-conductive bump 321 and a second sub-conductive bump 322; the ground line 411
  • the power line 412 is electrically connected to the first sub-conductive bump 321
  • the power line 412 is electrically connected to the second sub-conductive bump 322 .
  • the ground signal of the second semiconductor chip stack structure 30 is led out from the first sub-conductive bump 321 to the ground line 411, and the power signal of the second semiconductor chip stack structure 30 is led out from the first sub-conductive bump 321.
  • the two sub-conductive bumps 322 are led to the power line 412, and then the ground line 411 and the power line 412 are electrically connected to the first substrate 10 through the third conductive bump 42. Therefore, the first substrate 10 passes through the third conductive bump 42 and The ground line 411 and the power line 412 supply power to the second semiconductor chip stack structure 30 .
  • the third conductive bumps 42 are also connected to the substrate connection bumps 12 through the leads 11 in the first substrate 10 . In this way, the second semiconductor chip stack structure 30 can exchange information with external devices through the substrate connection bumps 12 .
  • FIG. 3 is a side view along the first direction of the second conductive bump provided by an embodiment of the present disclosure.
  • At least one first sub-conductive bump 321 is spaced between two adjacent second sub-conductive bumps 322 , and the first sub-conductive bump 321 surrounds the second sub-conductive bump 322 .
  • P (Power) in FIG. 3 is the second sub-conductive bump 322
  • G (Ground) is the first sub-conductive bump 321 .
  • the first sub-conductive bump 321 completely surrounds the second sub-conductive bump 322, and because the first sub-conductive bump 321 is connected to the ground signal, and the second sub-conductive bump 322 is connected to the power signal, In this way, crosstalk between different power signals can be reduced and the shielding of the power supply can be enhanced.
  • the semiconductor packaging structure further includes: a packaging compound structure 80 located on the first substrate 10 ; the packaging compound structure 80 at least wraps the second semiconductor chip stack structure 30 and the second Substrate 40.
  • the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20 .
  • the encapsulating compound structure 80 includes a silicon-containing compound.
  • the silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.
  • the warpage problem of the second semiconductor chip stack structure 30 can be reduced.
  • the semiconductor packaging structure further includes:
  • the filling layer 70 is located between the second semiconductor chip stack structure 30 and the second substrate 40 , and/or between the first semiconductor chip 20 , the second substrate 40 and the first substrate 10 between.
  • the filling layer 70 may be located in the second semiconductor chip stack structure. 30 and the second substrate 40 , and/or between the second substrate 40 and the first substrate 10 .
  • the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10 . between the two substrates 40 and the first substrate 10 , and/or between the second semiconductor chip stack structure 30 and the second substrate 40 .
  • the warpage of the second semiconductor chip stack structure is higher.
  • the warpage will occur.
  • the high degree makes it difficult to weld between the second semiconductor chip stack structure and the second substrate. Therefore, providing a filling layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip can effectively reduce the mismatch in overall temperature expansion characteristics between the chip and the substrate. Or the impact caused by external force increases the reliability of the semiconductor packaging structure.
  • the filling layer 70 is made of epoxy resin.
  • the principle of capillary action can be used to apply epoxy resin on the edge of the chip, allowing it to penetrate into the bottom of the chip or substrate, and then heat and cure it (cured). Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can improve the chip's performance. service life.
  • the Young's modulus of the filling layer 70 is greater than the Young's modulus of the encapsulating compound structure 80 .
  • Young's modulus is a physical quantity that can describe the ability of a solid material to resist deformation. The greater the Young's modulus, the greater the ability to resist deformation. When the Young's modulus is too low, it will be difficult to maintain the rigidity of the packaging structure, and deformation will easily occur. Problems such as warping or breakage. Therefore, in the embodiments of the present disclosure, a filling layer is formed, and the Young's modulus of the filling layer is greater than the Young's modulus of the packaging compound structure. In this way, the filling layer can have sufficient strength to support the entire packaging structure, so that the packaging structure is not easily Problems such as deformation, warping, or damage occur.
  • Embodiments of the present disclosure also provide a method for preparing a semiconductor packaging structure as described in any of the above embodiments. Please refer to FIG. 5 for details. As shown in the figure, the method includes the following steps:
  • Step 501 Form a second semiconductor chip stack structure, the second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked in sequence; form a plurality of second semiconductor chips on one side of the second semiconductor chip stack structure along the stacking direction. two conductive bumps;
  • Step 502 Form a first semiconductor chip
  • Step 503 Connect the surface of the second semiconductor chip stack structure perpendicular to the stacking direction with the surface of the first semiconductor chip;
  • Step 504 Provide a second substrate; the second substrate is located on the side of the second semiconductor chip stack structure where the second conductive bump is formed along the stacking direction, and the signal lines in the second substrate are connected to the second conductive bump. conductive bump connections;
  • Step 505 Provide a first substrate; connect the first semiconductor chip to the first substrate, and connect the second substrate to the first substrate.
  • 6a to 6h are schematic diagrams of device structures during the preparation process of the semiconductor packaging structure provided by embodiments of the present disclosure.
  • step 501 is performed to form a second semiconductor chip stack structure 30.
  • the second semiconductor chip stack structure 30 includes a plurality of second semiconductor chips 31 stacked in sequence; in the second semiconductor chip
  • the stacked structure 30 forms a plurality of second conductive bumps 32 on one side along the stacking direction.
  • forming the second semiconductor chip stack structure 30 includes: forming a through silicon via 311 penetrating the second semiconductor chip 31 along the stacking direction;
  • a fourth conductive bump 312 is formed between two adjacent second semiconductor chips 31, and the fourth conductive bump 312 is correspondingly connected to the through silicon via 311;
  • the second semiconductor chip stack 300 is formed into a plurality of second semiconductor chip stack structures 30 .
  • the second semiconductor chip stack may be cut to form a plurality of second semiconductor chip stack structures.
  • the second semiconductor chip stack structure 30 includes DRAM chips.
  • the number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 may be multiple. In this embodiment of the disclosure, as shown in FIG. 6b , the number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 is five.
  • the second conductive bump 32 may be located on the bottom second semiconductor chip 31 of the second semiconductor chip stack 300 . In other embodiments, the second conductive bump 32 may also be located on the uppermost second semiconductor chip 31 of the second semiconductor chip stack 300 .
  • the method of preparing the semiconductor packaging structure further includes: forming a dielectric layer 60 between two adjacent second semiconductor chips 31 .
  • a dielectric layer By providing a dielectric layer, two adjacent second semiconductor chips can be insulated and isolated, and the fourth conductive bump is located in the dielectric layer, which can reduce the possibility of coupling between adjacent fourth conductive bumps.
  • the material of the dielectric layer 60 includes oxide. In a specific embodiment, the material of the dielectric layer 60 includes SiO 2 .
  • steps 502 and 503 are performed to form the first semiconductor chip 20; connect the surface of the second semiconductor chip stack structure 30 perpendicular to the stacking direction with the surface of the first semiconductor chip 20.
  • the second semiconductor chip stack structure is rotated 90 degrees before being connected to the first semiconductor chip.
  • the stacking direction is a direction parallel to the plane of the first semiconductor chip, there is no need to rotate the second semiconductor chip stack structure.
  • the first semiconductor chip 20 includes a logic chip.
  • the method further includes: forming a first conductive bump 21 on one side surface of the first semiconductor chip 20; The surface away from the first conductive bump 21 is connected.
  • an adhesive film 50 is formed on the first semiconductor chip 20 , and the second semiconductor chip stack structure 30 and the second semiconductor chip stack structure 30 are connected through the adhesive film 50 .
  • the first semiconductor chip 20 is connected.
  • the adhesive film 50 can adhere the first semiconductor chip 20 and the second semiconductor chip stack structure 30 to enhance the adhesion between them, thereby improving the firmness of the semiconductor packaging structure.
  • the adhesive film can adjust the distance between the second semiconductor chip stack structure and the first semiconductor chip, that is, prevent the second semiconductor chip stack structure from being combined with the first semiconductor chip at an angle, causing additional stress, causing the second semiconductor chip stack structure to The second conductive block is damaged.
  • the adhesive film 50 includes a die-hardening adhesive film.
  • the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, and the elastic modulus of the second adhesive film is greater than the elastic modulus of the first adhesive film.
  • the first adhesive film is connected to the first semiconductor chip, it mainly plays a bonding role, and the second adhesive film is connected to the second semiconductor chip stack structure, and mainly plays a role in preventing the chip from warping.
  • the second adhesive film since the second adhesive film has a higher elastic modulus, it will not warp during the packaging process.
  • the first adhesive film has a lower elastic modulus, which will not affect the connection between the first semiconductor chip and the first semiconductor chip in the subsequent process.
  • the bonding force of the second semiconductor chip stack structure since the second adhesive film has a higher elastic modulus, it will not warp during the packaging process.
  • the first adhesive film has a lower elastic modulus, which will not affect the connection between the first semiconductor chip and the first semiconductor chip in the subsequent process.
  • the first semiconductor chip 20 and the second semiconductor chip stack structure 30 communicate through wireless communication.
  • a wireless coil is provided in each DRAM in the second semiconductor chip stack structure 30 ( (not shown), correspondingly, corresponding wireless coils are provided at the above-mentioned coil corresponding positions on the first semiconductor chip 20 .
  • Wireless communication between the first semiconductor chip and the second semiconductor chip stack structure can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip.
  • step 504 is performed to provide a second substrate 40; the second substrate 40 is located along the stacking direction on the side of the second semiconductor chip stack structure 30 on which the second conductive bumps 32 are formed.
  • the signal lines 41 in the second substrate 40 are connected to the second conductive bumps 32 .
  • the second substrate 40 is provided, including:
  • the second substrate 40 is cut to form third conductive bumps 42 on the second substrate 40 so that the surface of the second substrate 40 formed with the third conductive bumps 42 is in contact with the second semiconductor chip.
  • the surface of the stacked structure 30 close to the first semiconductor chip 20 is flush.
  • the second semiconductor chip stack structure 30 is first welded to the second substrate 40 through the second conductive bumps 32, and then the second substrate 40 is cut to a suitable size, for example, to a size similar to that of the second substrate 40.
  • the surfaces of the two semiconductor chip stack structures 30 close to the first semiconductor chip 20 are flush and the signal lines 41 are exposed, and then the remaining second substrate 40' is removed.
  • the surface of the second substrate 40 on which the third conductive bumps 42 are formed and the second semiconductor chip stack structure 30 are close to the first semiconductor chip 20
  • the surface of the second substrate 40 formed with the third conductive bump 42 is flush with the surface of the first semiconductor chip 20 formed with the first conductive bump.
  • the surface of bump 21 is flush.
  • a third conductive bump 42 is formed on the surface of the cut second substrate 40 where the signal line 41 is exposed, and the third conductive bump 42 is connected to the signal line 41 .
  • the signal line 41 includes a ground line 411 and a power line 412
  • the second conductive bump 32 includes a first sub-conductive bump 321 and a second sub-conductive bump 322; the ground line 411
  • the power line 412 is electrically connected to the first sub-conductive bump 321
  • the power line 412 is electrically connected to the second sub-conductive bump 322 .
  • the ground signal of the second semiconductor chip stack structure 30 is led out from the first sub-conductive bump 321 to the ground line 411, and the power signal of the second semiconductor chip stack structure 30 is led out from the first sub-conductive bump 321.
  • the two sub-conductive bumps 322 are led to the power line 412, and then the ground line 411 and the power line 412 are electrically connected to the subsequently formed first substrate 10 through the third conductive bump 42. Therefore, the first substrate 10 passes through the third conductive bump 42.
  • the block 42 and the ground line 411 and the power line 412 supply power to the second semiconductor chip stack structure 30 .
  • At least one first sub-conductive bump 321 is spaced between two adjacent second sub-conductive bumps 322 , and the first sub-conductive bump 321 surrounds the second sub-conductive bump 322 .
  • P (Power) in FIG. 3 is the second sub-conductive bump 322
  • G (Ground) is the first sub-conductive bump 321 .
  • the first sub-conductive bump 321 completely surrounds the second sub-conductive bump 322, and because the first sub-conductive bump 321 is connected to the ground signal, and the second sub-conductive bump 322 is connected to the power signal, In this way, crosstalk between different power signals can be reduced and the shielding of the power supply can be enhanced.
  • step 505 is performed to provide the first substrate 10; connect the first semiconductor chip 20 to the first substrate 10, and connect the second substrate 40 to the first substrate 10.
  • the first substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the first substrate 10 may include a first base (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) respectively located on the upper surface and lower surface of the first base. .
  • the first substrate may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate. etc., it can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure. , such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the first upper insulating dielectric layer and the first lower insulating dielectric layer may be solder resist layers.
  • the material of the first upper insulating dielectric layer and the first lower insulating dielectric layer may be green paint.
  • a substrate connection bump 12 is formed on the lower surface of the first substrate 10 .
  • the substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, and can receive from the external device a signal for operating the first semiconductor chip. At least one of the control signal, the power signal and the ground signal of the second semiconductor chip, or the data signal to be stored in the first semiconductor chip and the second semiconductor chip may be received from an external device, or the first semiconductor chip and the second semiconductor chip may be The data in the second semiconductor chip is provided to the external device.
  • the substrate connection bumps 12 include conductive material.
  • the substrate connection bumps 12 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only a lower and feasible shape in the embodiment of the present disclosure. The specific implementation of the invention does not constitute a limitation of the present disclosure, and the substrate connection bumps can also be of other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.
  • the first semiconductor chip 20 is connected to the first substrate 10 through a first conductive bump 21
  • the second substrate 40 is connected to the third conductive bump 42 through a third conductive bump 42 .
  • a substrate 10 is connected.
  • a groove 101 is formed in the first substrate 10; the first semiconductor chip 20 is placed in the groove 101.
  • placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor packaging structure.
  • the first semiconductor chip 20 is located on the first substrate 10
  • the first conductive bump 21 is located on the first semiconductor chip 20 and the first substrate 10 . between substrates 10.
  • the first semiconductor chip is located above the first substrate.
  • the first substrate does not need to be provided with a groove, so the process is simpler, and there is a gap between the first semiconductor chip and the first substrate, which can increase the number of first semiconductor chips.
  • the heat dissipation effect of semiconductor chips is described below.
  • the first semiconductor chip 20 and the first substrate 10 are electrically connected through first conductive bumps 21 .
  • the first substrate 10 supplies power to the first semiconductor chip through wires and performs signal exchange.
  • the first conductive bumps 21 are also connected to the substrate connection bumps 12 through the leads 11 in the first substrate 10 . In this way, the first semiconductor chip 20 can exchange information with external devices through the substrate connection bumps 12 .
  • the third conductive bumps 42 are also connected to the substrate connection bumps 12 through the leads 11 in the first substrate 10 . In this way, the second semiconductor chip stack structure 30 can exchange information with external devices through the substrate connection bumps 12 .
  • the method further includes: forming a packaging compound structure 80 on the first substrate 10 , the packaging compound structure 80 at least wrapping the second semiconductor chip stack structure 30 and the second substrate 40 .
  • the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20 .
  • the encapsulating compound structure 80 includes a silicon-containing compound.
  • the silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.
  • the warpage problem of the second semiconductor chip stack structure 30 can be reduced.
  • the method further includes: forming a filling layer 70 between the second semiconductor chip stack structure 30 and the second substrate 40, and/or, the first semiconductor chip 20 and between the second substrate 40 and the first substrate 10 .
  • the filling layer 70 may be located in the second semiconductor chip stack structure. 30 and the second substrate 40 , and/or between the second substrate 40 and the first substrate 10 .
  • the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10 . between the two substrates 40 and the first substrate 10 , and/or between the second semiconductor chip stack structure 30 and the second substrate 40 .
  • the warpage of the second semiconductor chip stack structure is higher.
  • the warpage When it is erected on the first semiconductor chip, there will be a problem due to the warpage. High, resulting in difficulty in welding between the second semiconductor chip stack structure and the second substrate. Therefore, providing a filling layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip can effectively reduce the mismatch in overall temperature expansion characteristics between the chip and the substrate. Or the impact caused by external force increases the reliability of the semiconductor packaging structure.
  • the filling layer 70 is made of epoxy resin.
  • the principle of capillary action can be used to apply epoxy resin on the edge of the chip, allowing it to penetrate into the bottom of the chip or substrate, and then heat and cure it (cured). Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can improve the chip's performance. service life.
  • the Young's modulus of the filling layer 70 is greater than the Young's modulus of the encapsulating compound structure 80 .
  • Young's modulus is a physical quantity that can describe the ability of a solid material to resist deformation. The greater the Young's modulus, the greater the ability to resist deformation. When the Young's modulus is too low, it will be difficult to maintain the rigidity of the packaging structure, and deformation will easily occur. Problems such as warping or breakage. Therefore, in the embodiments of the present disclosure, a filling layer is formed, and the Young's modulus of the filling layer is greater than the Young's modulus of the packaging compound structure. In this way, the filling layer can have sufficient strength to support the entire packaging structure, so that the packaging structure is not easily Problems such as deformation, warping, or damage occur.
  • a plurality of second semiconductor chips in the second semiconductor chip stack structure are vertically stacked (V-Stacked) on the first semiconductor chip in parallel.
  • the first semiconductor chip and the second semiconductor chip can be connected by Wireless communication can effectively solve the communication difficulties caused by the increase in the number of stacked layers of second semiconductor chips when multiple second semiconductor chips are sequentially stacked in parallel (P-Stack) on the first semiconductor chip.
  • the first substrate supplies power to the first semiconductor chip and the second semiconductor chip stack structure in a wired manner, and simultaneously exchanges signals with the first semiconductor chip, which has high reliability.

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Abstract

本公开实施例公开了一种半导体封装结构及其制备方法，其中，所述半导体封装结构包括：第一基板；第一半导体芯片，与所述第一基板连接；第二半导体芯片堆叠结构，位于所述第一半导体芯片上；所述第二半导体芯片堆叠结构包括多个沿第一方向依次堆叠的第二半导体芯片；所述第二半导体芯片堆叠结构在沿第一方向的一侧形成有多个第二导电凸块；其中，所述第一方向为平行于所述第一基板的平面的方向；第二基板，所述第二基板内的信号线与所述第二导电凸块连接；沿垂直于所述第一基板的平面的方向，所述第二基板与所述第一基板连接。

Description

一种半导体封装结构及其制备方法
相关申请的交叉引用
本公开基于申请号为202210959176.4、申请日为2022年08月10日、发明名称为“一种半导体封装结构及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及三维制程技术领域，尤其涉及一种半导体封装结构及其制备方法。
背景技术
HBM存储器(High Bandwidth Memory)是一种基于3D堆栈工艺的高性能DRAM内存，与传统内存技术相比，HBM存储器具有更高带宽、更多I/O数量、更低功耗、更小尺寸，可应用于高性能计算、超级计算机、大型数据中心、人工智能/深度学习、云计算等领域。
HBM存储器技术主要是基于对处理器计算规模需求发展而来，在早期时候，人们对计算机数据处理要求不高，处理器架构模型层数较少，计算规模较小，算力也较低；后随着AI等技术的发展，对处理器要求越来越高，模型加深对算力需求相应增加，导致了带宽瓶颈，即I/O问题，此时通过增大片内缓存、优化调度模型来增加数据复用率等方式解决；但后期随着AI等技术普及，用户量增多，云端AI处理需求多用户、高吞吐、低延迟、高密度部署，计算单元剧增使I/O瓶颈愈加严重，此时，片上HBM存储器出现使AI/深度学习完全放到片上成为可能，集成度提升的同时，使带宽不再受制于芯片引脚的互联数量，从而在一定程度上解决了带宽和计算能力瓶颈。
但是随着HBM存储器的集成度要求增高，芯片堆叠层数越来越多，技术难点也越来越多。
发明内容
有鉴于此，本公开实施例提供一种半导体封装结构及其制备方法。
根据本公开实施例的第一方面，提供了一种半导体封装结构，包括：
第一基板；
第一半导体芯片，与所述第一基板连接；
第二半导体芯片堆叠结构，位于所述第一半导体芯片上；所述第二半导体芯片堆叠结构包括多个沿第一方向依次堆叠的第二半导体芯片；所述第二半导体芯片堆叠结构在沿第一方向的一侧形成有多个第二导电凸块；其中，所述第一方向 为平行于所述第一基板的平面的方向；
第二基板，所述第二基板内的信号线与所述第二导电凸块连接；沿垂直于所述第一基板的平面的方向，所述第二基板与所述第一基板连接。
在一些实施例中，所述第一半导体芯片包括逻辑芯片，所述第二半导体芯片堆叠结构包括DRAM芯片。
在一些实施例中，还包括：
粘附膜，位于所述第一半导体芯片与所述第二半导体芯片堆叠结构之间。
在一些实施例中，所述粘附膜包括第一粘附膜和位于所述第一粘附膜上的第二粘附膜，所述第二粘附膜的弹性模量大于所述第一粘附膜的弹性模量。
在一些实施例中，所述第一半导体芯片与所述第二半导体芯片堆叠结构之间通过无线进行通讯。
在一些实施例中，所述第一基板内形成有凹槽，所述第一半导体芯片位于所述凹槽内，所述第一半导体芯片与所述第一基板通过第一导电凸块连接，所述第二基板与所述第一基板通过第三导电凸块连接。
在一些实施例中，所述第一半导体芯片位于所述第一基板上，所述第一半导体芯片与所述第一基板通过第一导电凸块连接，所述第二基板与所述第一基板通过第三导电凸块连接。
在一些实施例中，还包括：
多个硅通孔，所述硅通孔沿第一方向贯穿所述第二半导体芯片；
多个第四导电凸块，位于相邻两个所述第二半导体芯片之间，且与所述硅通孔对应连接；
所述第二导电凸块与所述硅通孔以及所述第四导电凸块对应连接。
在一些实施例中，所述信号线包括接地线和电源线，所述第二导电凸块包括第一子导电凸块和第二子导电凸块；
所述接地线与所述第一子导电凸块电连接，所述电源线与所述第二子导电凸块电连接。
在一些实施例中，相邻两个第二子导电凸块之间至少间隔一个第一子导电凸块，所述第一子导电凸块包围所述第二子导电凸块。
在一些实施例中，还包括：
填充层，位于所述第二半导体芯片堆叠结构与所述第二基板之间，和/或，所述第一半导体芯片和所述第二基板与所述第一基板之间。
在一些实施例中，还包括：
封装化合物结构，位于所述第一基板上；所述封装化合物结构至少包裹所述第二半导体芯片堆叠结构和所述第二基板；
所述填充层的杨氏模量大于所述封装化合物结构的杨氏模量。
根据本公开实施例的第二方面，提供一种如上述任一项实施例中所述的半导体封装结构的制备方法，包括：
形成第二半导体芯片堆叠结构，所述第二半导体芯片堆叠结构包括多个依次堆叠的第二半导体芯片；在所述第二半导体芯片堆叠结构在沿堆叠方向的一侧形成多个第二导电凸块；
形成第一半导体芯片；
将所述第二半导体芯片堆叠结构的垂直于所述堆叠方向的表面与所述第一半导体芯片表面连接；
提供第二基板；所述第二基板沿堆叠方向位于所述第二半导体芯片堆叠结构形成有第二导电凸块的一侧，所述第二基板内的信号线与所述第二导电凸块连接；
提供第一基板；将所述第一半导体芯片与所述第一基板连接，以及将所述第二基板与所述第一基板连接。
在一些实施例中，所述形成第二半导体芯片堆叠结构，包括：
沿堆叠方向，形成贯穿所述第二半导体芯片的硅通孔；
在相邻两个所述第二半导体芯片之间形成第四导电凸块，所述第四导电凸块与所述硅通孔对应连接；
将多个所述第二半导体芯片通过混合键合连接，形成第二半导体芯片堆叠体；
将所述第二半导体芯片堆叠体形成为多个第二半导体芯片堆叠结构。
在一些实施例中，所述提供第二基板，包括：对所述第二基板进行切割，在所述第二基板上形成第三导电凸块，使所述第二基板形成有第三导电凸块的表面与所述第二半导体芯片堆叠结构的靠近所述第一半导体芯片的表面齐平。
在一些实施例中，在所述第一基板内形成凹槽；
将所述第一半导体芯片放置于所述凹槽内。
在一些实施例中，还包括：
在形成第一半导体芯片后，在所述第一半导体芯片上形成粘附膜，通过所述粘附膜将所述第二半导体芯片堆叠结构和所述第一半导体芯片连接。
在一些实施例中，所述第一半导体芯片与所述第二半导体芯片堆叠结构之间通过无线进行通讯。
在一些实施例中，还包括：
形成填充层，所述填充层位于所述第二半导体芯片堆叠结构与所述第二基板之间，和/或，所述第一半导体芯片和所述第二基板与所述第一基板之间。
本公开实施例中，第二半导体芯片堆叠结构中的多个第二半导体芯片并列垂直堆叠(V-Stack)在第一半导体芯片上，如此，第一半导体芯片与第二半导体芯片之间可以通过无线方式进行通讯，可以有效解决多个第二半导体芯片依次平行堆叠(P-Stack)在第一半导体芯片上时，随着第二半导体芯片的堆叠层数的增多给通讯带来的困难。同时，第一基板通过有线的方式为第一半导体芯片和第二半导体芯片堆叠结构供电，并同时和第一半导体芯片之间进行信号交换，具有高可靠性。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体封装结构的结构示意图；
图2为本公开另一实施例提供的半导体封装结构的结构示意图；
图3为本公开实施例提供的第二导电凸块沿第一方向的侧视图；
图4a和图4b为本公开又一实施例提供的半导体封装结构的结构示意图；
图5为本公开实施例提供的半导体封装结构的制备方法的流程示意图；
图6a至6h为本公开实施例提供的半导体封装结构在制备过程中的器件结构示意图。
附图标记说明：
10-第一基板；11-引线；12-基板连接凸块；101-凹槽；
20-第一半导体芯片；21-第一导电凸块；
30-第二半导体芯片堆叠结构；300-第二半导体芯片堆叠体；31-第二半导体芯片；311-硅通孔；312-第四导电凸块；32-第二导电凸块；321-第一子导电凸块；322-第二子导电凸块；
40-第二基板；41-信号线；411-接地线；412-电源线；42-第三导电凸块；40’-剩余第二基板；
50-粘附膜；
60-介质层；
70-填充层；
80-封装化合物结构。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与 另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
HBM技术是DRAM从传统2D向立体3D发展的主要代表产品，开启了DRAM 3D化道路。它主要是通过硅通孔(Through Silicon Via，TSV)技术进行芯片堆叠，以增加吞吐量并克服单一封装内带宽的限制，将数个DRAM裸片垂直堆叠，裸片之间用TVS技术连接。从技术角度看，HBM充分利用空间、缩小面积，正契合半导体行业小型化、集成化的发展趋势，并且突破了内存容量与带宽瓶颈，被视为新一代DRAM解决方案。
3D IC产品封装中，DRAM芯片一般采用平行堆叠(P-Stack)的方式堆叠在逻辑芯片(Logic die)上，随着集成度要求增高，DRAM芯片堆叠层数越来越多，技术难点也越来越多，譬如，堆叠于高层的DRAM芯片与底层的逻辑芯片(Logic die)之间的通讯距离越来越长，且不同层DRAM芯片与逻辑芯片之间的通讯延迟由于距离的不同会产生差异；用于通讯的TSV通孔会正比例增高，牺牲晶圆面积。
基于此，本公开实施例提供了一种半导体封装结构。图1为本公开实施例提供的半导体封装结构的结构示意图。
参见图1，所述半导体封装结构包括：
第一基板10；
第一半导体芯片20，与所述第一基板10连接；
第二半导体芯片堆叠结构30，位于所述第一半导体芯片20上；所述第二半导体芯片堆叠结构30包括多个沿第一方向依次堆叠的第二半导体芯片31；所述第二半导体芯片堆叠结构30在沿第一方向的一侧形成有多个第二导电凸块32； 其中，所述第一方向为平行于所述第一基板10的平面的方向；
第二基板40，所述第二基板40内的信号线41与所述第二导电凸块32连接；沿垂直于所述第一基板10的平面的方向，所述第二基板40与所述第一基板10连接。
本公开实施例中，第二半导体芯片堆叠结构中的多个第二半导体芯片并列垂直堆叠(V-Stack)在第一半导体芯片上，如此，第一半导体芯片与第二半导体芯片之间可以通过无线方式进行通讯，可以有效解决多个第二半导体芯片依次平行堆叠(P-Stack)在第一半导体芯片上时，随着第二半导体芯片的堆叠层数的增多给通讯带来的困难。同时，第一基板通过有线的方式为第一半导体芯片和第二半导体芯片堆叠结构供电，并同时和第一半导体芯片之间进行信号交换，具有高可靠性。
在一实施例中，所述第一基板10可以是印刷电路板(PCB)或再分布基板。
所述第一基板10可以包括第一基底(未图示)以及分别位于所述第一基底的上表面和下表面上的第一上绝缘介质层和第一下绝缘介质层(未图示)。
所述第一基底可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述第一上绝缘介质层和所述第一下绝缘介质层可以为阻焊层，例如所述第一上绝缘介质层和所述第一下绝缘介质层的材料可以为绿漆。
所述第一基板10的下表面上形成有基板连接凸块12，所述基板连接凸块12可将半导体封装结构电连接到外部装置上，可以从外部装置接收用于操作第一半导体芯片和第二半导体芯片的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在第一半导体芯片和第二半导体芯片内的数据信号，也可将第一半导体芯片和第二半导体芯片内的数据提供给外部装置。
所述基板连接凸块12包括导电材料。在本公开实施例中，所述基板连接凸块12为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
在一实施例中，所述第一半导体芯片20的一面上形成有第一导电凸块21。
所述第一导电凸块21的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。
所述第一半导体芯片20与所述第一基板10之间通过第一导电凸块21进行电连接，所述第一基板10通过有线的方式为第一半导体芯片进行供电，并进行信号交换。
所述第一导电凸块21还通过第一基板10内的引线11与基板连接凸块12连接，如此，第一半导体芯片20可通过基板连接凸块12与外部装置进行信息交互。
在一实施例中，如图1所示，所述第一基板10内形成有凹槽101，所述第一半导体芯片20位于所述凹槽101内，所述第一半导体芯片20与所述第一基板10 通过第一导电凸块21连接，所述第二基板40与所述第一基板10通过第三导电凸块42连接。
在此实施例中，将第一半导体芯片放置于第一基板的凹槽内，可以减少半导体封装结构的封装高度。
在另一实施例中，如图2所示，所述第一半导体芯片20位于所述第一基板10上，所述第一半导体芯片20与所述第一基板10通过第一导电凸块21连接，所述第二基板40与所述第一基板10通过第三导电凸块42连接。
在此实施例中，第一半导体芯片位于第一基板的上方，如此，第一基板无需设置凹槽，因此工艺更加简单，并且第一半导体芯片与第一基板之间存在间隙，能增加第一半导体芯片的散热效果。
所述第二半导体芯片堆叠结构30中的第二半导体芯片31的堆叠数目可以为多个。本公开实施例中，如图1所示，所述第二半导体芯片堆叠结构30中的第二半导体芯片31的堆叠数目为五个。
在一实施例中，所述第一半导体芯片20包括逻辑芯片，所述第二半导体芯片堆叠结构30包括DRAM芯片。
在一实施例中，所述半导体封装结构，还包括：粘附膜50，位于所述第一半导体芯片20与所述第二半导体芯片堆叠结构30之间。
所述粘附膜50能将所述第一半导体芯片20和所述第二半导体芯片堆叠结构30进行粘合，增强它们之间的粘附性，进而提高半导体封装结构的牢固程度。同时，粘附膜可以调节第二半导体芯片堆叠结构与第一半导体芯片的距离，即防止第二基板与第二导电块的结合存在角度，造成额外应力，使得第二半导体芯片堆叠结构上的第二导电块损伤。
在一实施例中，所述粘附膜50包括固晶胶膜。
在一实施例中，所述粘附膜包括第一粘附膜和位于所述第一粘附膜上的第二粘附膜(未图示)，所述第二粘附膜的弹性模量大于所述第一粘附膜的弹性模量。
本公开实施例中，因为第一粘附膜与第一半导体芯片连接，主要起到粘结的作用，第二粘附膜与第二半导体芯片堆叠结构连接，主要起到防止芯片翘曲的作用，由于第二粘附膜的弹性模量较高，在封装过程中不会出现翘曲，第一粘附膜具有较低的弹性模量，在后续的工艺中不会影响第一半导体芯片与第二半导体芯片堆叠结构的结合力。
在一实施例中，所述第一半导体芯片20与所述第二半导体芯片堆叠结构30之间通过无线进行通讯，譬如，在第二半导体芯片堆叠结构30中的每个DRAM中设置无线线圈(未图示)，对应的，在第一半导体芯片20上的上述线圈对应位置设置对应的无线线圈。
第一半导体芯片与第二半导体芯片堆叠结构之间通过无线进行通讯，可以有效解决随着第二半导体芯片的堆叠层数的增多给通讯带来的困难，同时减少了TSV的数量，减小了工艺难度。
在一实施例中，如图1所示，所述半导体封装结构，还包括：多个硅通孔311，所述硅通孔311沿第一方向贯穿所述第二半导体芯片31；多个第四导电凸块312，位于相邻两个所述第二半导体芯片31之间，且与所述硅通孔311对应连接；所述第二导电凸块32与所述硅通孔311以及所述第四导电凸块312对应连接。
本实施例中，后续电源信号和接地信号可以由硅通孔和第四导电凸块引到第二导电凸块上。
所述第二半导体芯片堆叠结构中相邻两个第二半导体芯片之间通过硅通孔和第四导电块进行电连接。
第二半导体芯片堆叠结构采用混合键合方式获得，如此，堆叠的芯片结构可作为一个整体，进而提高堆叠结构垂直放置的机械强度，同时减少芯片所受到的压强。
所述半导体封装结构还包括：介质层60，位于相邻两个所述第二半导体芯片31之间。通过设置介质层，能够使相邻的两个第二半导体芯片绝缘隔离，并且第四导电凸块位于介质层内，能够降低相邻第四导电凸块之间耦合的可能性。
所述介质层60的材料包括氧化物，在一具体实施例中，所述介质层60的材料包括SiO 2。
此外，为了提高第二半导体芯片堆叠结构的厚度，进而增强其机械强度，不需要对最外层芯片进行减薄处理。
所述第二基板40的材质和结构可以与所述第一基板10相同，因此这里不再赘述。
在一实施例中，所述信号线41包括接地线411和电源线412，所述第二导电凸块32包括第一子导电凸块321和第二子导电凸块322；所述接地线411与所述第一子导电凸块321电连接，所述电源线412与所述第二子导电凸块322电连接。
在此实施例中，所述第二半导体芯片堆叠结构30的接地信号由所述第一子导电凸块321引出至接地线411，所述第二半导体芯片堆叠结构30的电源信号由所述第二子导电凸块322引出至电源线412，然后接地线411和电源线412通过第三导电凸块42与第一基板10电连接，由此，第一基板10通过第三导电凸块42以及接地线411和电源线412为第二半导体芯片堆叠结构30供电。
所述第三导电凸块42还通过第一基板10内的引线11与基板连接凸块12连接，如此，第二半导体芯片堆叠结构30可通过基板连接凸块12与外部装置进行信息交互。
图3为本公开实施例提供的第二导电凸块沿第一方向的侧视图。
如图3所示，相邻两个第二子导电凸块322之间至少间隔一个第一子导电凸块321，所述第一子导电凸块321包围所述第二子导电凸块322。
图3中的P(Power)即为第二子导电凸块322，G(Ground)即为第一子导电凸块321。
所述第一子导电凸块321将第二子导电凸块322的四周全部给包围起来，且因为第一子导电凸块321与接地信号连接，第二子导电凸块322与电源信号连接，如此，能够减少不同的电源信号之间的串扰，增强电源的屏蔽。
在一实施例中，所述半导体封装结构还包括：封装化合物结构80，位于所述第一基板10上；所述封装化合物结构80至少包裹所述第二半导体芯片堆叠结构30和所述第二基板40。
在图2所示的实施例中，所述封装化合物结构80还包裹所述第一半导体芯片20。
所述封装化合物结构80包括含硅化合物。所述含硅化合物可以为旋制玻璃 (SOG)、含硅的旋涂电介质(SOD)或其他含硅的旋涂材料。
通过形成封装化合物结构80，且封装化合物结构80的材料包括含硅化合物，能够减少第二半导体芯片堆叠结构30的翘曲问题。
在一实施例中，所述半导体封装结构还包括：
填充层70，位于所述第二半导体芯片堆叠结构30与所述第二基板40之间，和/或，所述第一半导体芯片20和所述第二基板40与所述第一基板10之间。
例如，在一实施例中，如图4a所示，当所述第一半导体芯片20位于所述第一基板10的凹槽内时，所述填充层70可以位于所述第二半导体芯片堆叠结构30与所述第二基板40之间，和/或，位于所述第二基板40与所述第一基板10之间。
在另一实施例中，如图4b所示，当所述第一半导体芯片20位于所述第一基板10的上方时，所述填充层70可以位于所述第一半导体芯片20和所述第二基板40与所述第一基板10之间，和/或，所述第二半导体芯片堆叠结构30与所述第二基板40之间。
对于三维堆叠的第二半导体芯片堆叠结构，因为在沿第一方向上的厚度较薄，因此第二半导体芯片堆叠结构的翘曲度较高，竖立在第一半导体芯片上时，会因为翘曲度高，导致第二半导体芯片堆叠结构与第二基板之间难以焊接。因此，在在第二半导体芯片堆叠结构与第二基板之间，以及在第一基板与第一半导体芯片之间设置填充层，能有效降低由于芯片与基板之间的总体温度膨胀特性的不匹配或外力造成的冲击，增加半导体封装结构的可靠性。
在一实施例中，所述填充层70的材料包括环氧树脂(Epoxy)。
可以利用毛细作用原理把环氧树脂涂抹在芯片的边缘让其渗透到芯片或基板的底部，然后加热予以固化(cured)，因为环氧树脂能有效提高焊点的机械强度，因此能够提高芯片的使用寿命。
在一实施例中，所述填充层70的杨氏模量大于所述封装化合物结构80的杨氏模量。
杨氏模量是能够描述固体材料抵抗形变的能力物理量，杨氏模量越大，抵抗形变的能力越大，而杨氏模量过低时，会难以维持封装结构的刚性，容易发生变形、翘曲或破损等问题。因此，本公开实施例中，通过形成填充层，且填充层的杨氏模量大于封装化合物结构的杨氏模量，如此，填充层能够有足够的强度支撑起整个封装结构，使封装结构不易发生变形、翘曲或破损等问题。
本公开实施例还提供了一种如上述任一项实施例中所述的半导体封装结构的制备方法，具体请参见附图5，如图所示，所述方法包括以下步骤：
步骤501：形成第二半导体芯片堆叠结构，所述第二半导体芯片堆叠结构包括多个依次堆叠的第二半导体芯片；在所述第二半导体芯片堆叠结构在沿堆叠方向的一侧形成多个第二导电凸块；
步骤502：形成第一半导体芯片；
步骤503：将所述第二半导体芯片堆叠结构的垂直于所述堆叠方向的表面与所述第一半导体芯片表面连接；
步骤504：提供第二基板；所述第二基板沿堆叠方向位于所述第二半导体芯片堆叠结构形成有第二导电凸块的一侧，所述第二基板内的信号线与所述第二导电凸块连接；
步骤505：提供第一基板；将所述第一半导体芯片与所述第一基板连接，以及将所述第二基板与所述第一基板连接。
下面结合具体实施例对本公开实施例提供的半导体封装结构的制备方法再作进一步详细的说明。
图6a至6h为本公开实施例提供的半导体封装结构在制备过程中的器件结构示意图。
首先，参见图6a和图6b，执行步骤501，形成第二半导体芯片堆叠结构30，所述第二半导体芯片堆叠结构30包括多个依次堆叠的第二半导体芯片31；在所述第二半导体芯片堆叠结构30在沿堆叠方向的一侧形成多个第二导电凸块32。
参见图6a，所述形成第二半导体芯片堆叠结构30，包括：沿堆叠方向，形成贯穿所述第二半导体芯片31的硅通孔311；
在相邻两个所述第二半导体芯片31之间形成第四导电凸块312，所述第四导电凸块312与所述硅通孔311对应连接；
将多个所述第二半导体芯片31通过混合键合连接，形成第二半导体芯片堆叠体300；
将所述第二半导体芯片堆叠体300形成为多个第二半导体芯片堆叠结构30。
在实际操作中，可以将所述第二半导体芯片堆叠体进行切割，以形成多个第二半导体芯片堆叠结构。
在一实施例中，所述第二半导体芯片堆叠结构30包括DRAM芯片。
所述第二半导体芯片堆叠结构30中的第二半导体芯片31的堆叠数目可以为多个。本公开实施例中，如图6b所示，所述第二半导体芯片堆叠结构30中的第二半导体芯片31的堆叠数目为五个。
在一实施例中，如图6a所示，所述第二导电凸块32可以位于所述第二半导体芯片堆叠体300的最底层第二半导体芯片31上。在其他实施例中，所述第二导电凸块32也可以位于所述第二半导体芯片堆叠体300的最上层第二半导体芯片31上。
参见图6b，所述半导体封装结构的制备方法还包括：在相邻两个所述第二半导体芯片31之间形成介质层60。通过设置介质层，能够使相邻的两个第二半导体芯片绝缘隔离，并且第四导电凸块位于介质层内，能够降低相邻第四导电凸块之间耦合的可能性。
所述介质层60的材料包括氧化物，在一具体实施例中，所述介质层60的材料包括SiO 2。
此外，为了提高第二半导体芯片堆叠结构的厚度，进而增强其机械强度，不需要对最外层芯片进行减薄处理。
接着，参见图6c，执行步骤502和步骤503，形成第一半导体芯片20；将所述第二半导体芯片堆叠结构30的垂直于所述堆叠方向的表面与所述第一半导体芯片20表面连接。
在一些实施例中，如果所述堆叠方向为垂直于所述第一半导体芯片的平面的方向，则将所述第二半导体芯片堆叠结构旋转90度后，与所述第一半导体芯片连接。
在其他一些实施例中，如果所述堆叠方向为平行于所述第一半导体芯片的平 面的方向，则无需将第二半导体芯片堆叠结构进行旋转。
在一实施例中，所述第一半导体芯片20包括逻辑芯片。
在一实施例中，所述方法还包括：在所述第一半导体芯片20的一侧表面形成第一导电凸块21；所述第二半导体芯片堆叠结构30与所述第一半导体芯片20的远离所述第一导电凸块21的表面连接。
在一实施例中，在形成第一半导体芯片20后，在所述第一半导体芯片20上形成粘附膜50，通过所述粘附膜50将所述第二半导体芯片堆叠结构30和所述第一半导体芯片20连接。
所述粘附膜50能将所述第一半导体芯片20和所述第二半导体芯片堆叠结构30进行粘合，增强它们之间的粘附性，进而提高半导体封装结构的牢固程度。同时，粘附膜可以调节第二半导体芯片堆叠结构与第一半导体芯片的距离，即防止第二半导体芯片堆叠结构与第一半导体芯片结合存在角度，造成额外应力，使得第二半导体芯片堆叠结构上的第二导电块损伤。
在一实施例中，所述粘附膜50包括固晶胶膜。
在一实施例中，所述粘附膜包括第一粘附膜和位于所述第一粘附膜上的第二粘附膜(未图示)，所述第二粘附膜的弹性模量大于所述第一粘附膜的弹性模量。
本公开实施例中，因为第一粘附膜与第一半导体芯片连接，主要起到粘结的作用，第二粘附膜与第二半导体芯片堆叠结构连接，主要起到防止芯片翘曲的作用，由于第二粘附膜的弹性模量较高，在封装过程中不会出现翘曲，第一粘附膜具有较低的弹性模量，在后续的工艺中不会影响第一半导体芯片与第二半导体芯片堆叠结构的结合力。
在一实施例中，所述第一半导体芯片20与所述第二半导体芯片堆叠结构30之间通过无线进行通讯，譬如，在第二半导体芯片堆叠结构30中的每个DRAM中设置无线线圈(未图示)，对应的，在第一半导体芯片20上的上述线圈对应位置设置对应的无线线圈。
第一半导体芯片与第二半导体芯片堆叠结构之间通过无线进行通讯，可以有效解决随着第二半导体芯片的堆叠层数的增多给通讯带来的困难。
接着，参见图6d和图6e，执行步骤504，提供第二基板40；所述第二基板40沿堆叠方向位于所述第二半导体芯片堆叠结构30形成有第二导电凸块32的一侧，所述第二基板40内的信号线41与所述第二导电凸块32连接。
参见图6d和图6e，所述提供第二基板40，包括：
对所述第二基板40进行切割，在所述第二基板40上形成第三导电凸块42，使所述第二基板40形成有第三导电凸块42的表面与所述第二半导体芯片堆叠结构30的靠近所述第一半导体芯片20的表面齐平。
具体地，先将所述第二半导体芯片堆叠结构30通过第二导电凸块32焊接到所述第二基板40上，然后将第二基板40切割到合适的尺寸，例如切割到与所述第二半导体芯片堆叠结构30的靠近所述第一半导体芯片20的表面齐平，且暴露出所述信号线41，然后将剩余第二基板40’去除。
需要说明的是，在图6d所示的实施例中，所述第二基板40形成有第三导电凸块42的表面与所述第二半导体芯片堆叠结构30的靠近所述第一半导体芯片20的表面齐平，在形成如图2所示的半导体封装结构的实施例中，所述第二基板40 形成有第三导电凸块42的表面与所述第一半导体芯片20形成有第一导电凸块21的表面齐平。
接着，参见图6e，在切割后的第二基板40的暴露所述信号线41的表面形成第三导电凸块42，所述第三导电凸块42与所述信号线41连接。
在一实施例中，所述信号线41包括接地线411和电源线412，所述第二导电凸块32包括第一子导电凸块321和第二子导电凸块322；所述接地线411与所述第一子导电凸块321电连接，所述电源线412与所述第二子导电凸块322电连接。
在此实施例中，所述第二半导体芯片堆叠结构30的接地信号由所述第一子导电凸块321引出至接地线411，所述第二半导体芯片堆叠结构30的电源信号由所述第二子导电凸块322引出至电源线412，然后接地线411和电源线412通过第三导电凸块42与后续形成的第一基板10电连接，由此，第一基板10通过第三导电凸块42以及接地线411和电源线412为第二半导体芯片堆叠结构30供电。
如图3所示，相邻两个第二子导电凸块322之间至少间隔一个第一子导电凸块321，所述第一子导电凸块321包围所述第二子导电凸块322。
图3中的P(Power)即为第二子导电凸块322，G(Ground)即为第一子导电凸块321。
所述第一子导电凸块321将第二子导电凸块322的四周全部给包围起来，且因为第一子导电凸块321与接地信号连接，第二子导电凸块322与电源信号连接，如此，能够减少不同的电源信号之间的串扰，增强电源的屏蔽。
接着，参见图6f，执行步骤505，提供第一基板10；将所述第一半导体芯片20与所述第一基板10连接，以及将所述第二基板40与所述第一基板10连接。
在一实施例中，所述第一基板10可以是印刷电路板(PCB)或再分布基板。
所述第一基板10可以包括第一基底(未图示)以及分别位于所述第一基底的上表面和下表面上的第一上绝缘介质层和第一下绝缘介质层(未图示)。
所述第一基底可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述第一上绝缘介质层和所述第一下绝缘介质层可以为阻焊层，例如所述第一上绝缘介质层和所述第一下绝缘介质层的材料可以为绿漆。
在所述第一基板10的下表面上形成基板连接凸块12，所述基板连接凸块12可将半导体封装结构电连接到外部装置上，可以从外部装置接收用于操作第一半导体芯片和第二半导体芯片的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在第一半导体芯片和第二半导体芯片内的数据信号，也可将第一半导体芯片和第二半导体芯片内的数据提供给外部装置。
所述基板连接凸块12包括导电材料。在本公开实施例中，所述基板连接凸块12为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
在一实施例中，具体地，所述第一半导体芯片20通过第一导电凸块21与所述第一基板10连接，以及所述第二基板40通过第三导电凸块42与所述第一基板10连接。
在一实施例中，如图6f所示，在所述第一基板10内形成凹槽101；将所述第一半导体芯片20放置于所述凹槽101内。
在此实施例中，将第一半导体芯片放置于第一基板的凹槽内，可以减少半导体封装结构的封装高度。
在其他一些实施例中，如图2所示，所述第一半导体芯片20位于所述第一基板10上，所述第一导电凸块21位于所述第一半导体芯片20和所述第一基板10之间。
在此实施例中，第一半导体芯片位于第一基板的上方，如此，第一基板无需设置凹槽，因此工艺更加简单，并且第一半导体芯片与第一基板之间存在间隙，能增加第一半导体芯片的散热效果。
所述第一半导体芯片20与所述第一基板10之间通过第一导电凸块21进行电连接，所述第一基板10通过有线的方式为第一半导体芯片进行供电，并进行信号交换。
所述第一导电凸块21还通过第一基板10内的引线11与基板连接凸块12连接，如此，第一半导体芯片20可通过基板连接凸块12与外部装置进行信息交互。
所述第三导电凸块42还通过第一基板10内的引线11与基板连接凸块12连接，如此，第二半导体芯片堆叠结构30可通过基板连接凸块12与外部装置进行信息交互。
接着，参见图6g，所述方法还包括：在所述第一基板10上形成封装化合物结构80，所述封装化合物结构80至少包裹所述第二半导体芯片堆叠结构30和所述第二基板40。
在图2所示的实施例中，所述封装化合物结构80还包裹所述第一半导体芯片20。
所述封装化合物结构80包括含硅化合物。所述含硅化合物可以为旋制玻璃(SOG)、含硅的旋涂电介质(SOD)或其他含硅的旋涂材料。
通过形成封装化合物结构80，且封装化合物结构80的材料包括含硅化合物，能够减少第二半导体芯片堆叠结构30的翘曲问题。
接着，所述方法还包括：形成填充层70，所述填充层70位于所述第二半导体芯片堆叠结构30与所述第二基板40之间，和/或，所述第一半导体芯片20和所述第二基板40与所述第一基板10之间。
例如，在一实施例中，如图6h所示，当所述第一半导体芯片20位于所述第一基板10的凹槽内时，所述填充层70可以位于所述第二半导体芯片堆叠结构30与所述第二基板40之间，和/或，位于所述第二基板40与所述第一基板10之间。
在另一实施例中，如图4b所示，当所述第一半导体芯片20位于所述第一基板10的上方时，所述填充层70可以位于所述第一半导体芯片20和所述第二基板40与所述第一基板10之间，和/或，所述第二半导体芯片堆叠结构30与所述第二基板40之间。
对于三维堆叠的第二半导体芯片堆叠结构，因为在沿堆叠方向上的厚度较 薄，因此第二半导体芯片堆叠结构的翘曲度较高，竖立在第一半导体芯片上时，会因为翘曲度高，导致第二半导体芯片堆叠结构与第二基板之间难以焊接。因此，在在第二半导体芯片堆叠结构与第二基板之间，以及在第一基板与第一半导体芯片之间设置填充层，能有效降低由于芯片与基板之间的总体温度膨胀特性的不匹配或外力造成的冲击，增加半导体封装结构的可靠性。
在一实施例中，所述填充层70的材料包括环氧树脂(Epoxy)。
可以利用毛细作用原理把环氧树脂涂抹在芯片的边缘让其渗透到芯片或基板的底部，然后加热予以固化(cured)，因为环氧树脂能有效提高焊点的机械强度，因此能够提高芯片的使用寿命。
在一实施例中，所述填充层70的杨氏模量大于所述封装化合物结构80的杨氏模量。
杨氏模量是能够描述固体材料抵抗形变的能力物理量，杨氏模量越大，抵抗形变的能力越大，而杨氏模量过低时，会难以维持封装结构的刚性，容易发生变形、翘曲或破损等问题。因此，本公开实施例中，通过形成填充层，且填充层的杨氏模量大于封装化合物结构的杨氏模量，如此，填充层能够有足够的强度支撑起整个封装结构，使封装结构不易发生变形、翘曲或破损等问题。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，第二半导体芯片堆叠结构中的多个第二半导体芯片并列垂直堆叠(V-Stack)在第一半导体芯片上，如此，第一半导体芯片与第二半导体芯片之间可以通过无线方式进行通讯，可以有效解决多个第二半导体芯片依次平行堆叠(P-Stack)在第一半导体芯片上时，随着第二半导体芯片的堆叠层数的增多给通讯带来的困难。同时，第一基板通过有线的方式为第一半导体芯片和第二半导体芯片堆叠结构供电，并同时和第一半导体芯片之间进行信号交换，具有高可靠性。

Claims (19)

  1. 一种半导体封装结构，包括：
    第一基板；
    第一半导体芯片，与所述第一基板连接；
    第二半导体芯片堆叠结构，位于所述第一半导体芯片上；所述第二半导体芯片堆叠结构包括多个沿第一方向依次堆叠的第二半导体芯片；所述第二半导体芯片堆叠结构在沿第一方向的一侧形成有多个第二导电凸块；其中，所述第一方向为平行于所述第一基板的平面的方向；
    第二基板，所述第二基板内的信号线与所述第二导电凸块连接；沿垂直于所述第一基板的平面的方向，所述第二基板与所述第一基板连接。
  2. 根据权利要求1所述的半导体封装结构，其中，
    所述第一半导体芯片包括逻辑芯片，所述第二半导体芯片堆叠结构包括DRAM芯片。
  3. 根据权利要求1所述的半导体封装结构，其中，还包括：
    粘附膜，位于所述第一半导体芯片与所述第二半导体芯片堆叠结构之间。
  4. 根据权利要求3所述的半导体封装结构，其中，
    所述粘附膜包括第一粘附膜和位于所述第一粘附膜上的第二粘附膜，所述第二粘附膜的弹性模量大于所述第一粘附膜的弹性模量。
  5. 根据权利要求1所述的半导体封装结构，其中，
    所述第一半导体芯片与所述第二半导体芯片堆叠结构之间通过无线进行通讯。
  6. 根据权利要求1所述的半导体封装结构，其中，
    所述第一基板内形成有凹槽，所述第一半导体芯片位于所述凹槽内，所述第一半导体芯片与所述第一基板通过第一导电凸块连接，所述第二基板与所述第一基板通过第三导电凸块连接。
  7. 根据权利要求1所述的半导体封装结构，其中，
    所述第一半导体芯片位于所述第一基板上，所述第一半导体芯片与所述第一基板通过第一导电凸块连接，所述第二基板与所述第一基板通过第三导电凸块连接。
  8. 根据权利要求1所述的半导体封装结构，其中，还包括：
    多个硅通孔，所述硅通孔沿第一方向贯穿所述第二半导体芯片；
    多个第四导电凸块，位于相邻两个所述第二半导体芯片之间，且与所述硅通孔对应连接；
    所述第二导电凸块与所述硅通孔以及所述第四导电凸块对应连接。
  9. 根据权利要求1所述的半导体封装结构，其中，
    所述信号线包括接地线和电源线，所述第二导电凸块包括第一子导电凸块和第二子导电凸块；
    所述接地线与所述第一子导电凸块电连接，所述电源线与所述第二子导电凸块电连接。
  10. 根据权利要求9所述的半导体封装结构，其中，
    相邻两个第二子导电凸块之间至少间隔一个第一子导电凸块，所述第一子导电凸块包围所述第二子导电凸块。
  11. 根据权利要求1所述的半导体封装结构，其中，还包括：
    填充层，位于所述第二半导体芯片堆叠结构与所述第二基板之间，和/或，所述第一半导体芯片和所述第二基板与所述第一基板之间。
  12. 根据权利要求11所述的半导体封装结构，其中，还包括：
    封装化合物结构，位于所述第一基板上；所述封装化合物结构至少包裹所述第二半导体芯片堆叠结构和所述第二基板；
    所述填充层的杨氏模量大于所述封装化合物结构的杨氏模量。
  13. 一种如权利要求1-12中任一项所述的半导体封装结构的制备方法，包括：
    形成第二半导体芯片堆叠结构，所述第二半导体芯片堆叠结构包括多个依次堆叠的第二半导体芯片；在所述第二半导体芯片堆叠结构在沿堆叠方向的一侧形成多个第二导电凸块；
    形成第一半导体芯片；
    将所述第二半导体芯片堆叠结构的垂直于所述堆叠方向的表面与所述第一半导体芯片表面连接；
    提供第二基板；所述第二基板沿堆叠方向位于所述第二半导体芯片堆叠结构形成有第二导电凸块的一侧，所述第二基板内的信号线与所述第二导电凸块连接；
    提供第一基板；将所述第一半导体芯片与所述第一基板连接，以及将所述第二基板与所述第一基板连接。
  14. 根据权利要求13所述的方法，其中，
    所述形成第二半导体芯片堆叠结构，包括：
    沿堆叠方向，形成贯穿所述第二半导体芯片的硅通孔；
    在相邻两个所述第二半导体芯片之间形成第四导电凸块，所述第四导电凸块与所述硅通孔对应连接；
    将多个所述第二半导体芯片通过混合键合连接，形成第二半导体芯片堆叠体；
    将所述第二半导体芯片堆叠体形成为多个第二半导体芯片堆叠结构。
  15. 根据权利要求13所述的方法，其中，
    所述提供第二基板，包括：对所述第二基板进行切割，在所述第二基板上形成第三导电凸块，使所述第二基板形成有第三导电凸块的表面与所述第二半导体芯片堆叠结构的靠近所述第一半导体芯片的表面齐平。
  16. 根据权利要求13所述的方法，其中，
    在所述第一基板内形成凹槽；
    将所述第一半导体芯片放置于所述凹槽内。
  17. 根据权利要求13所述的方法，其中，还包括：
    在形成第一半导体芯片后，在所述第一半导体芯片上形成粘附膜，通过所述粘附膜将所述第二半导体芯片堆叠结构和所述第一半导体芯片连接。
  18. 根据权利要求13所述的方法，其中，
    所述第一半导体芯片与所述第二半导体芯片堆叠结构之间通过无线进行通讯。
  19. 根据权利要求13所述的方法，其中，还包括：
    形成填充层，所述填充层位于所述第二半导体芯片堆叠结构与所述第二基板之间，和/或，所述第一半导体芯片和所述第二基板与所述第一基板之间。
PCT/CN2022/123768 2022-08-10 2022-10-08 一种半导体封装结构及其制备方法 WO2024031812A1 (zh)

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US20100301475A1 (en) * 2009-05-26 2010-12-02 International Business Machines Corporation Forming Semiconductor Chip Connections
CN104350593A (zh) * 2012-06-25 2015-02-11 英特尔公司 具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装
CN104347578A (zh) * 2013-08-09 2015-02-11 爱思开海力士有限公司 层叠式半导体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080315388A1 (en) * 2007-06-22 2008-12-25 Shanggar Periaman Vertical controlled side chip connection for 3d processor package
US20100301475A1 (en) * 2009-05-26 2010-12-02 International Business Machines Corporation Forming Semiconductor Chip Connections
CN104350593A (zh) * 2012-06-25 2015-02-11 英特尔公司 具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装
CN104347578A (zh) * 2013-08-09 2015-02-11 爱思开海力士有限公司 层叠式半导体装置

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