WO2023206649A1 - 一种半导体器件的制备方法及半导体器件 - Google Patents

一种半导体器件的制备方法及半导体器件 Download PDF

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WO2023206649A1
WO2023206649A1 PCT/CN2022/093545 CN2022093545W WO2023206649A1 WO 2023206649 A1 WO2023206649 A1 WO 2023206649A1 CN 2022093545 W CN2022093545 W CN 2022093545W WO 2023206649 A1 WO2023206649 A1 WO 2023206649A1
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chip
contact pad
layer
wafer
active surface
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PCT/CN2022/093545
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English (en)
French (fr)
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庄凌艺
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长鑫存储技术有限公司
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method of manufacturing a semiconductor device and a semiconductor device.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including:
  • each said wafer including a plurality of chips
  • a first cutting process is performed on the plurality of wafers to form a plurality of cutting grooves located above the carrier and penetrating the plurality of wafers.
  • the plurality of wafers are divided into multiple cutting grooves based on the cutting grooves.
  • a chip stack the chip stack includes a plurality of chips stacked in a vertical direction, and the carrier leaves the plurality of chip stacks in an unseparated state;
  • a second cutting process is performed on the cladding layer along the cutting groove to form a plurality of chip stacks with sidewalls and upper surfaces covered with the cladding layer.
  • the method further includes:
  • the logic wafer including at least one logic chip
  • the chip stack and the logic chip are bonded and connected.
  • forming the coating layer includes:
  • a seed layer is formed on the chip stack, and the seed layer covers the side walls and upper surface of the chip stack; wherein the active surface of the chip located on the topmost layer of the chip stack faces downward. , the active surface is the side of the wafer on which the device layer is formed;
  • An electroplating process is performed to form a cladding layer on the seed layer, the cladding layer covering the seed layer.
  • forming the coating layer includes:
  • An electroplating process is performed to form a second sub-layer on the seed layer, the second sub-layer covering the seed layer.
  • performing a first cutting process on the plurality of wafers includes:
  • a wafer cutting knife and/or cutting lines to perform a first cutting process on the plurality of wafers, forming a plurality of cutting grooves located above the carrier and penetrating the plurality of wafers, the plurality of wafers is divided into a plurality of chip stacks based on the cutting groove;
  • Performing a second cutting process on the cladding layer along the cutting groove includes:
  • a second cutting process is performed on the cladding layer using a grinding wheel, a wafer cutting knife, a cutting line, and/or a laser cutting process to form a plurality of chip stacks with sidewalls and upper surfaces covered with the cladding layer.
  • each wafer includes multiple chips, including:
  • first wafer including a plurality of first chips and a second wafer including a plurality of second chips
  • Stacking the plurality of wafers on the carrier in sequence along the vertical direction, and bonding the chips distributed on the adjacent wafers one by one includes:
  • At least one first contact pad and at least one second contact pad are respectively formed on the surfaces of the first wafer and the second wafer, and a first dielectric layer located around the first contact pad is formed. and a second dielectric layer located on the periphery of the second contact pad;
  • the first wafer and the second wafer are sequentially stacked and arranged on the carrier, so that the first contact pad and the second contact pad are butted;
  • a bonding process is performed so that the first contact pad and the second contact pad, and the first dielectric layer and the second dielectric layer are bonded to each other to form a hybrid bonding component.
  • At least one first contact pad and at least one second contact pad are respectively formed on the surfaces of the first wafer and the second wafer, and a contact pad located on the periphery of the first contact pad is formed.
  • a first dielectric layer and a second dielectric layer located on the periphery of the second contact pad including:
  • a first contact pad is formed in the first through hole, and the first contact pad is connected to the first chip in a one-to-one correspondence;
  • a second contact pad is formed in the second through hole, and the second contact pad is connected to the second chip in a one-to-one correspondence; wherein, the active surface is a device layer formed on the wafer. one side.
  • At least one first contact pad and at least one second contact pad are respectively formed on the surfaces of the first wafer and the second wafer, and a contact pad located on the periphery of the first contact pad is formed.
  • a first dielectric layer and a second dielectric layer located on the periphery of the second contact pad including:
  • a first contact pad is formed in the first through hole, and the first contact pad is connected to the first chip in a one-to-one correspondence;
  • a second contact pad is formed in the second through hole, and the second contact pad is connected to the second chip in a one-to-one correspondence; wherein, the active surface is a device layer formed on the wafer. One side; the non-active surface is the opposite side to the active surface.
  • the chip stack and the logic chip are bonded and connected; including:
  • At least one third contact pad is formed on the surface of the logic wafer, and the third contact pad is connected to the logic chip in a one-to-one correspondence;
  • the chip stack is disposed above the logic chip, and the third contact pad is docked with the fourth contact pad;
  • a bonding process is performed so that the third contact pad and the fourth contact pad are bonded to each other.
  • the method further includes:
  • An encapsulating compound is formed over the logic chip and covering the cladding layer.
  • An embodiment of the present disclosure also provides a semiconductor device, including:
  • a chip stack the chip stack includes a plurality of chips, the plurality of chips are stacked on the logic chip in a vertical direction, and the adjacent chips are interconnected with each other; wherein the chip stack passes through Vertically stacked multiple wafers are formed by performing a cutting process;
  • a coating layer is located above the logic chip and covers the side walls and upper surface of the chip stack.
  • the material of the coating layer includes metal or spin coating compound.
  • the cladding layer includes a first sub-layer and a second sub-layer, and the first sub-layer is located between the second sub-layer and the chip stack; wherein, the second sub-layer The thermal diffusion coefficient is greater than the thermal diffusion coefficient of the first sub-layer.
  • the material of the first sub-layer includes a spin coating compound
  • the material of the second sub-layer includes metal
  • the plurality of chips include a first chip and a second chip interconnected by hybrid bonding members, and the hybrid bonding members include:
  • first contact pad located on the surface of the first chip, and a second contact pad located on the surface of the second chip;
  • first dielectric layer located on the periphery of the first contact pad and a second dielectric layer located on the periphery of the second contact pad;
  • first contact pad and the second contact pad are in contact bonding, and the first dielectric layer and the second dielectric layer are in contact bonding.
  • the first dielectric layer and the first contact pad are located on the active surface of the first chip, and the second dielectric layer and the second contact pad are located on the second chip.
  • the first chip and the second chip are bonded and connected at their active surfaces; wherein, the active surface is the side of the chip on which the device layer is formed.
  • the first dielectric layer and the first contact pad are formed on the active surface of the first chip, and the second dielectric layer and the second contact pad are formed on the second The non-active surface of the chip, the active surface of the first chip is bonded to the non-active surface of the second chip; wherein, the active surface is the side of the chip where the device layer is formed, and the non-active surface The source surface is the side opposite the active surface.
  • the logic chip and the chip stack are interconnected through a first bonding member;
  • the first bonding member includes:
  • a third contact pad located on the surface of the logic chip
  • a fourth contact pad located on the lower surface of the chip at the bottom layer of the chip stack
  • the logic chip and the chip stack are contact bonded through the third contact pad and the fourth contact pad.
  • the third contact pad is located on the non-active surface of the logic chip, and the fourth contact pad is located on the non-active surface of the chip at the lowest layer of the chip stack, so
  • the logic chip and the chip stack are bonded and connected at their non-active surfaces; wherein the active surface is the logic chip or the side on which the device layer is formed on the chip, and the non-active surface
  • the source surface is the side opposite the active surface.
  • the semiconductor device further includes a packaging compound, the packaging compound is located above the logic chip, and the packaging compound covers the cladding layer.
  • a method for manufacturing a semiconductor device and a semiconductor device provided by embodiments of the present disclosure, wherein the method includes: providing a carrier; providing a plurality of wafers, each of the wafers including a plurality of chips; Stack the plurality of wafers on the carrier in sequence, and bond the chips disposed on the adjacent wafers one by one; perform a first cutting process on the plurality of wafers , forming a plurality of cutting grooves located above the carrier and penetrating the plurality of wafers, the plurality of wafers are divided into a plurality of chip stacks based on the cutting grooves, the chip stacks include vertical A plurality of chips are stacked in a straight direction, and the carrier sheet keeps the plurality of chip stacks in an unseparated state; forming a coating layer, and the coating layer covers the side wall and upper surface of at least one of the chip stacks; A second cutting process is performed on the cladding layer along the cutting groove to form a plurality of chip stacks with sidewall
  • multiple wafers are first stacked and bonded on the carrier, and then the first cutting process is performed. At this time, the multiple wafers are cut through without cutting the carrier, forming multiple chips in an unseparated state.
  • Stack then, a coating layer is formed on the chip stack.
  • the formation of the coating layer can wrap and fix particles and other substances generated during the first cutting process on the side walls and upper surface of the chip stack to prevent them from Displacement during the subsequent transfer or packaging process may cause tilting of the final semiconductor device or risk of poor contact.
  • a second cutting process on the cladding layer a plurality of chip stacks with sidewalls and upper surfaces covered with the cladding layer can be formed.
  • the method for manufacturing a semiconductor device provided by embodiments of the present disclosure can significantly improve the stability and reliability of the finally formed semiconductor device.
  • the embodiment of the present disclosure does not cut off the carrier when performing the first cutting process, which provides the possibility of forming cladding layers on the sidewalls and upper surfaces of multiple chip stacks at the same time, optimizing the process flow. , which can effectively improve production efficiency.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • Figure 2 Figure 3, Figure 4a to Figure 4c, Figure 5a to Figure 5c are process flow diagrams of the preparation process of the semiconductor device provided by the embodiment of the present disclosure
  • Figure 6 is a schematic three-dimensional structural diagram of multiple wafers stacked on a carrier according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a process for performing a first cutting process on a semiconductor device according to an embodiment of the present disclosure
  • 8a and 8b are respectively a top schematic view and a partial cross-sectional schematic view of the semiconductor device after performing the first cutting process according to the embodiment of the present disclosure
  • 9a to 9b and 10a to 10c are process flow diagrams of forming a cladding layer on a semiconductor device according to different embodiments of the present disclosure
  • FIG. 11 is a schematic cross-sectional view of a chip stack formed after performing a second cutting process on a semiconductor device according to an embodiment of the present disclosure
  • 12 to 14 are process flow charts for bonding a chip stack and a logic wafer according to embodiments of the present disclosure
  • Figure 15 is a schematic cross-sectional view of a structure formed after the chip stack and the logic wafer are bonded according to an embodiment of the present disclosure
  • Figure 16 is a schematic cross-sectional view of another structure formed after the chip stack and the logic wafer are bonded according to an embodiment of the present disclosure
  • Figure 17 is a schematic cross-sectional view of yet another structure formed after the chip stack and the logic wafer are bonded according to an embodiment of the present disclosure
  • Figure 18 is a schematic cross-sectional view of a structure of a semiconductor device after forming a packaging compound according to an embodiment of the present disclosure
  • 19 is a schematic cross-sectional view of another structure of a semiconductor device after forming a packaging compound according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, as shown in Figure 1.
  • the method includes the following steps:
  • Step S101 Provide slide
  • Step S102 Provide multiple wafers, each of which includes multiple chips;
  • Step S103 Stack the plurality of wafers on the carrier in sequence along the vertical direction, and bond and connect the chips distributed on the adjacent wafers one by one;
  • Step S104 Perform a first cutting process on the plurality of wafers to form a plurality of cutting grooves located above the carrier and penetrating the plurality of wafers, and the plurality of wafers are divided based on the cutting grooves. It is a plurality of chip stacks, the chip stack includes a plurality of chips stacked in a vertical direction, and the carrier makes the plurality of chip stacks in an unseparated state;
  • Step S105 Form a coating layer that covers the side wall and upper surface of at least one of the chip stacks;
  • Step S106 Perform a second cutting process on the cladding layer along the cutting groove to form a plurality of chip stacks with sidewalls and upper surfaces covered with the cladding layer.
  • multiple wafers are first stacked and bonded on the carrier, and then the first cutting process is performed. At this time, the multiple wafers are only cut through without cutting the carrier, forming a plurality of wafers in the future.
  • the chip stack in a separated state; then a coating layer is formed on the chip stack.
  • the formation of the coating layer can wrap and fix particles and other substances generated during the first cutting process on the side walls and upper surface of the chip stack. to prevent the final semiconductor device from being displaced during the subsequent transfer or packaging process, causing the risk of tilting or poor contact.
  • a second cutting process on the cladding layer a plurality of chip stacks with sidewalls and upper surfaces covered with the cladding layer can be formed.
  • the method for manufacturing a semiconductor device provided by embodiments of the present disclosure can significantly improve the stability and reliability of the finally formed semiconductor device.
  • the embodiment of the present disclosure does not cut off the carrier when performing the first cutting process, which provides the possibility of forming cladding layers on the sidewalls and upper surfaces of multiple chip stacks at the same time, optimizing the process flow. , which can effectively improve production efficiency.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • Figures 2, Figure 3, Figures 4a to 4c, and Figure 5a to Figure 5c are processes during the preparation of a semiconductor device provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic three-dimensional structural diagram of multiple wafers stacked on a carrier provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the process of performing the first cutting process on a semiconductor device provided by an embodiment of the present disclosure
  • Figures 8a and 8b A schematic top view and a partial cross-sectional view of a semiconductor device provided by embodiments of the present disclosure after performing the first cutting process respectively
  • Figures 9a to 9b and Figures 10a to 10c are cladding layers formed on semiconductor devices provided by different embodiments of the disclosure.
  • Figure 11 is a schematic cross-sectional view of the chip stack formed after the second cutting process is performed on the semiconductor device provided by the embodiment of the present disclosure
  • Figures 12 to 14 are the chip stack and the logic crystal provided by the embodiment of the present disclosure.
  • the process flow chart of circular bonding is a schematic cross-sectional view of a structure formed after bonding a chip stack provided by an embodiment of the present disclosure and a logic wafer
  • Figure 16 is a chip stack provided by an embodiment of the present disclosure
  • Figure 17 is a schematic cross-sectional view of another structure formed after bonding a chip stack provided by an embodiment of the present disclosure with a logic wafer
  • Figure 18 Figure 19 is a schematic cross-sectional view of another structure of a semiconductor device provided by an embodiment of the present disclosure after forming a packaging compound.
  • step S101 is performed, as shown in Figure 2, to provide slide 1.
  • the material of the carrier 1 may include but is not limited to discarded wafers, glass substrates, semiconductor substrates or ceramic substrates.
  • step S102 is performed. As shown in FIG. 3 , a plurality of wafers 10 are provided, each of the wafers 10 including a plurality of chips C.
  • step S103 is performed. As shown in FIGS. 4a to 4c, 5a to 5c, and 6, the plurality of wafers 10 are sequentially stacked on the carrier 1 in the vertical direction, and the wafers 10 are placed separately. The chips C on the adjacent wafers 10 are bonded and connected in a one-to-one correspondence.
  • 4a to 4c and 5a to 5c are partial cross-sectional views of the plurality of wafers 10 sequentially stacked on the carrier 1 along the vertical direction.
  • multiple wafers 10 are provided, and each of the wafers 10 includes multiple chips C, including:
  • the first wafer W1 includes a plurality of first chips 11, and the second wafer W2 includes a plurality of second chips 12;
  • the plurality of wafers 10 are stacked sequentially on the carrier 1 in the vertical direction, and the chips C arranged on the adjacent wafers 10 are bonded and connected one by one, including:
  • At least one first contact pad 13 and at least one second contact pad 14 are formed on the surfaces of the first wafer W1 and the second wafer W2 respectively, and are formed on the periphery of the first contact pad 13 The first dielectric layer L1 and the second dielectric layer L2 located on the periphery of the second contact pad 14;
  • the first wafer W1 and the second wafer W2 are sequentially stacked on the carrier 1 so that the first contact pad 13 and the second contact pad 14 are butted;
  • a bonding process is performed so that the first contact pad 13 and the second contact pad 14 and the first dielectric layer L1 and the second dielectric layer L2 are bonded to each other to form a hybrid bonding component.
  • the materials of the first dielectric layer include, but are not limited to, oxides, nitrides, oxynitrides, etc.; the materials of the second dielectric layer may also include, but are not limited to, oxides, nitrides, oxynitrides, etc. Materials, etc.; the materials of the first contact pad and the second contact pad include but are not limited to copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes. One or more formed alloys.
  • the first dielectric layer and the second dielectric layer may be made of the same material. In fact, different materials can also be used to form the first dielectric layer and the second dielectric layer respectively, and there is no specific limitation here. Similarly, the materials of the first contact pad and the second contact pad may be the same or different, and are not specifically limited here.
  • a hybrid bonding method is used to perform one-to-one correspondence between the chips of adjacent wafers. Bonding to form electrical connections can effectively shorten the wiring distance between corresponding chips located on adjacent wafers, shortening the communication distance between chips, effectively improving signal transmission efficiency and shortening communication time.
  • At least one first contact pad 13 and at least one second contact pad are formed on the surfaces of the first wafer W1 and the second wafer W2 respectively.
  • a first contact pad 13 is formed in the first through hole H1, and the first contact pad 13 is connected to the first chip 11 in a one-to-one correspondence;
  • a second contact pad 14 is formed in the second through hole H2, and the second contact pad 14 is connected to the second chip 12 in a one-to-one correspondence; wherein the active surface S1 is the wafer The side on which the device layer is formed; the non-active surface S2 is the opposite side to the active surface.
  • hybrid bonding is used to perform one-to-one bonding between chips on adjacent wafers to form electrical connections, which can effectively shorten the distance between corresponding chips on adjacent wafers.
  • the gap shortens the communication distance between chips, which can effectively improve signal transmission efficiency and shorten communication time.
  • At least one first contact pad is formed on the surface of the first wafer W1 and the second wafer W2 respectively. 13 and at least one second contact pad 14, and forming a first dielectric layer L1 located on the periphery of the first contact pad 13 and a second dielectric layer L2 located on the periphery of the second contact pad 14; including:
  • a first contact pad 13 is formed in the first through hole H1, and the first contact pad 13 is connected to the first chip 11 in a one-to-one correspondence;
  • a second contact pad 14 is formed in the second through hole H2, and the second contact pad 14 is connected to the second chip 12 in a one-to-one correspondence; wherein the active surface S1 is the wafer 10 is the side on which the device layer is formed.
  • the wafer 10 includes the first wafer W1 and the second wafer W2; the chip C includes the first chip 11 and the second chip 12.
  • the second dielectric layer and the first contact pad are formed on the active surface of the second wafer.
  • the method of the second contact pad enables hybrid bonding between the two wafers in a face-to-face manner, that is, the chips at corresponding positions in adjacent wafers are face-to-face hybrid bonding between the active surfaces. . It can be understood that compared with other embodiments, this hybrid bonding and face-to-face bonding method can further shorten the communication distance between two adjacent chips, further improve communication efficiency, and more effectively shorten communication time.
  • this disclosure only illustrates a part of the implementation of bonding between wafers.
  • the bonding method between the first wafer and the second wafer, the first dielectric layer and the first contact pad, the second dielectric layer and the The specific positions where the second contact pad is formed on the first wafer and the second wafer can be flexibly adjusted according to actual conditions.
  • step S104 is performed.
  • a first cutting process is performed on the plurality of wafers 10 to form a pattern above the carrier 1 and penetrating the plurality of wafers 10 .
  • a plurality of cutting grooves 101, the plurality of wafers 10 are divided into a plurality of chip stacks ST based on the cutting grooves 101, the chip stack ST includes a plurality of chips C stacked in the vertical direction, the The carrier 1 maintains the plurality of chip stacks ST in an unseparated state.
  • performing a first cutting process on the plurality of wafers 10 includes:
  • a first cutting process is performed on the plurality of wafers 10 using a wafer cutting knife 4 and/or a cutting line to form a plurality of cutting grooves 101 located above the carrier 1 and penetrating the plurality of wafers 10, so The plurality of wafers 10 are divided into a plurality of chip stacks ST based on the dicing grooves 101 .
  • the cutting wire includes but is not limited to diamond wire and the like.
  • the practice of not cutting the slide when performing the first cutting process provides the possibility of forming cladding layers on the sidewalls and upper surfaces of multiple chip stacks at the same time, optimizing By simplifying the process flow, production efficiency can be effectively improved.
  • step S105 is continued.
  • a cladding layer 30 is formed.
  • the cladding layer 30 covers the sidewall and upper surface of at least one of the chip stacks ST.
  • forming the cladding layer 30 includes:
  • a seed layer 33 is formed on the chip stack ST, and the seed layer 33 covers the side walls and upper surface of the chip stack ST; wherein, the chip C located on the topmost layer of the chip stack ST The active surface S1 faces downward, and the active surface S1 is the side of the wafer on which the device layer is formed;
  • An electroplating process is performed to form a cladding layer 30 on the seed layer 33 , and the cladding layer 30 covers the seed layer 33 .
  • materials of the seed layer and the cladding layer include but are not limited to copper. But it is not limited to this, the material of the coating layer can also be other materials with good thermal conductivity.
  • forming the coating layer includes:
  • An electroplating process is performed to form a second sub-layer 32 on the seed layer 33 , and the second sub-layer 32 covers the seed layer 33 .
  • the material of the first sub-layer includes but is not limited to spin-on glass (SOG), etc.
  • the spin-on glass (SOG) can be spin-coated in a liquid state (similar to the spin-coating of photoresist) to
  • the raw materials of the interlayer dielectric material on the semiconductor structure may include but are not limited to hydrogen silsesquioxane polymers and siloxane solvents; the materials of the seed layer and the second sub-layer may include but are not limited to Copper etc. But it is not limited to this, the material of the second sub-layer can also be other materials with relatively good thermal conductivity.
  • an electroplating process is performed, including:
  • the semiconductor device Immersing the semiconductor device in an electroplating copper solution, the semiconductor device including a seed layer;
  • An electroplated copper layer is formed on the seed layer, wherein the electroplated copper solution includes but is not limited to water, copper supply source, electrolyte material, etc.
  • the particles 5 may include but are not limited to debris or powder generated during the production process. Even during the cutting process, It is also difficult to completely remove all these substances by performing a subsequent cleaning process.
  • the coating layer 30 can wrap the particles 5 generated during the first cutting process.
  • the existence of the coating layer can effectively prevent the above-mentioned substances from being displaced during the subsequent transfer or packaging process, causing the risk of tilting or poor contact of the finally formed semiconductor device, and improving the final formation of the semiconductor device. It improves the stability and reliability of the device and helps to improve the production yield.
  • the information transmission rate is easily affected by the quality of heat dissipation.
  • the information transmission rate of the semiconductor device will be reduced, prolonging the communication time. What's more, when the heat inside the semiconductor device continues to accumulate, the stability and reliability of the semiconductor device will be greatly affected.
  • the semiconductor device when the material of the cladding layer includes a metal material or other material with relatively good thermal conductivity, the heat generated inside the semiconductor device during operation will be conducted to the semiconductor device through the cladding layer. external. Therefore, in the embodiments of the present disclosure, the semiconductor device can avoid the situation where the information transmission rate is slowed down and the stability and reliability are reduced due to the failure to export heat in time, and the stability and reliability problems of the semiconductor device can be effectively improved.
  • the material of the cladding layer is a conductive material with good heat dissipation, and the conductive material directly contacts the wafer, the active surface of the wafer, that is, the wafer needs to be formed with One side of the device layer faces away from the cladding layer.
  • step S106 is performed. As shown in FIGS. 9 b and 11 , a second cutting process is performed on the cladding layer 30 along the cutting groove 101 to form a plurality of side walls and upper surfaces covered with the cladding layer 30 . chip stack ST.
  • Performing a second cutting process on the cladding layer 30 along the cutting groove 101 includes:
  • a grinding wheel, a wafer cutting knife 4, a cutting line and/or a laser cutting process to perform a second cutting process on the cladding layer 30 to form a plurality of chip stacks with side walls and upper surfaces covered with the cladding layer 30 ST.
  • the method further includes:
  • a logic wafer 20 is provided, the logic wafer 20 including at least one logic chip 21;
  • the chip stack ST and the logic chip 21 are bonded and connected.
  • the logic chip 21 may be one or more processors configured to communicate with a plurality of chips C to access data from the chips C and store data in the plurality of chips C.
  • the logic chip 21 includes, but is not limited to, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU) or other known electronic circuits used as processors.
  • the chip C includes but is not limited to a dynamic random access memory (DRAM) memory chip.
  • DRAM dynamic random access memory
  • bonding the chip stack ST and the logic chip 21 includes:
  • At least one third contact pad 23 is formed on the surface of the logic wafer 20, and the third contact pad 23 is connected to the logic chip 21 in a one-to-one correspondence;
  • a fourth contact pad 18 is formed on the lower surface of the chip C in the lowest layer of the chip stack ST;
  • the chip stack ST is disposed above the logic chip 21, and the third contact pad 23 is butted with the fourth contact pad 18;
  • a bonding process is performed so that the third contact pad 23 and the fourth contact pad 18 are bonded to each other.
  • forming the third contact pad 23 and the fourth contact pad 18 includes:
  • the fourth contact pad 18 is formed on the fourth dielectric layer L4.
  • the material of the third contact pad 23 and the fourth contact pad 18 may be the same as the material of the first contact pad 13 and the second contact pad 14, which will not be described again here.
  • the method further includes: forming a plurality of copper pillar bumps on a surface of the logic wafer 20 facing away from the chip stack ST. 22(Copper Pillar Bump).
  • the copper pillar bump 22 (Copper Pillar Bump) can be used to form an electrical connection between the semiconductor device and other devices, such as a PCB board.
  • the method further includes:
  • a third cutting process is performed to divide the logic wafer 20 to form multiple vertically distributed structures; wherein the chip stack ST and the logic wafer 20 are vertically stacked from top to bottom. in:
  • the active surface of the logic chip 21 faces away from the chip stack ST.
  • the first chip 11 and the second chip 12 are interconnected on the active surface S1 using a face-to-face hybrid bonding method.
  • the active surface S1 of the first chip 11 and the non-active surface S2 of the second chip 12 are interconnected by a hybrid bonding method.
  • Interconnects may be formed through vias 16 for communication.
  • the through hole 16 may include but is not limited to a through silicon via (TSV) or the like.
  • the method further includes:
  • An encapsulation compound 4 is formed, the encapsulation compound 4 is located over the logic chip 21 and covers the cladding layer 30 .
  • the material of the encapsulating compound 4 may be, for example, epoxy resin, phenolic resin, polyimide, silica gel or spin-coated silicon glass.
  • Packaging compound 4 can protect the packaging structure from external dust, moisture and mechanical impact, improving the reliability of the packaging structure.
  • Embodiments of the present disclosure also provide a semiconductor device, as shown in Figure 7 and Figure 18, including
  • Chip stack ST the chip stack ST includes a plurality of chips C, the plurality of chips C are stacked on the logic chip 21 in a vertical direction, and the adjacent chips C are interconnected with each other; wherein, The chip stack ST is formed by performing a cutting process on a plurality of vertically stacked wafers 10;
  • the coating layer 30 is located above the logic chip 21 and covers the side walls and the upper surface of the chip stack ST.
  • the logic chip 21 may be one or more processors configured to communicate with a plurality of chips C to access data from the chips C and store data in the plurality of chips C.
  • the logic chip 21 includes, but is not limited to, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU) or other known electronic circuits used as processors.
  • the chip C includes but is not limited to a dynamic random access memory (DRAM) memory chip.
  • DRAM dynamic random access memory
  • the plurality of chips C include first chips 11 and second chips 12 interconnected by hybrid bonding members, the hybrid bonding members include:
  • first contact pad 13 and the second contact pad 14 are in contact bonding, and the first dielectric layer L1 and the second dielectric layer L2 are in contact bonding.
  • a hybrid bonding method is used to perform one-to-one bonding between adjacent chips to form
  • the electrical connection method can effectively shorten the wiring distance between adjacent chips, shorten the communication distance between chips, effectively improve signal transmission efficiency, and shorten communication time.
  • the first dielectric layer L1 and the first contact pad 13 are formed on the active surface S1 of the first chip 11
  • the second dielectric layer L2 and The second contact pad 14 is formed on the non-active surface S2 of the second chip 12, and the active surface S1 of the first chip 11 is bonded to the non-active surface S2 of the second chip 12;
  • the active surface S1 is the side of the chip forming the device layer
  • the non-active surface S2 is the opposite side of the active surface S1.
  • hybrid bonding is used to perform one-to-one bonding between adjacent chips to form electrical connections, which can effectively shorten the gap between adjacent chips and improve communication between chips.
  • the shortened distance can effectively improve signal transmission efficiency and shorten communication time.
  • the first dielectric layer L1 and the first contact pad 13 are located on the active surface S1 of the first chip 11
  • the second dielectric layer L2 and The second contact pad 14 is located on the active surface S1 of the second chip 12
  • the first chip 11 and the second chip 12 are bonded and connected at their active surfaces S1; wherein,
  • the active surface S1 is the side of the chip on which a device layer is formed.
  • the second dielectric layer and the first contact pad are formed on the active surface of the second chip.
  • the method of the second contact pad enables hybrid bonding between two chips in a face-to-face manner, that is, face-to-face hybrid bonding between adjacent chips. It can be understood that compared with other embodiments, this hybrid bonding and face-to-face bonding method can further shorten the communication distance between two adjacent chips, further improve communication efficiency, and more effectively shorten communication time. .
  • this disclosure only illustrates a part of the implementation of bonding between chips.
  • the bonding method between the first chip and the second chip, the first dielectric layer and the first contact pad, the second dielectric layer and the second The specific positions where the contact pads are formed on the first chip and the second chip can be flexibly adjusted according to actual conditions.
  • the logic chip 21 and the chip stack ST are interconnected through a first bonding member;
  • the first bonding member includes:
  • the third contact pad 23 located on the surface of the logic chip 21;
  • the fourth contact pad 18 located on the lower surface of the chip C at the lowest layer of the chip stack ST;
  • the logic chip 21 and the chip stack ST are contact-bonded through the third contact pad 23 and the fourth contact pad 18 .
  • the third contact pad 23 is located on the non-active surface S2 of the logic chip 21
  • the fourth contact pad 18 is located on the chip C at the bottom of the chip stack ST.
  • the logic chip 21 and the chip stack ST are bonded and connected at the non-active surface S2 of the two; wherein the active surface S1 is the logic chip 21 or the The device layer is formed on one side of the chip C, and the non-active surface is the side opposite to the active surface S1 of S2.
  • the positions where the third contact pad and the fourth contact pad are formed can also be other possible combinations, and this disclosure does not impose too many limitations.
  • the semiconductor device further includes a through hole 16 , which may be located between a plurality of contact pads on the chip stack ST, The logic chip 21 and a plurality of contact pads located on the lowest chip of the chip stack ST are interconnected with each other for communication.
  • the through hole 16 may include but is not limited to a through silicon via (TSV) or the like.
  • the semiconductor device further includes a copper pillar bump 22 (Copper Pillar Bump).
  • the copper pillar bump 22 (Copper Pillar Bump) is located on the logic chip 21 away from the chip stack. The surface of the body ST.
  • the copper pillar bump 22 (Copper Pillar Bump) can be used to form an electrical connection between the semiconductor device and other devices, such as a PCB board.
  • the coating layer 30 can wrap the particles 5
  • the material of the cladding layer 30 includes metal or a spin-on compound.
  • the metal material may include, but is not limited to, copper, etc.
  • the spin coating compound may include, but is not limited to, spin on glass (SOG), etc.
  • the coating layer 30 may be a layer of material.
  • the material may include but is not limited to materials with relatively good thermal conductivity such as metal.
  • the material of the cladding layer is a conductive material with good thermal conductivity, and the conductive material directly contacts the chip, it is necessary to form a device layer on the active surface of the chip, that is, the chip. One side faces away from the cladding.
  • the coating layer 30 includes a first sub-layer 31 and a second sub-layer 32, and the first sub-layer 31 is located between the second sub-layer 32 and the between the chip stacks ST; wherein the thermal diffusion coefficient of the second sub-layer 32 is greater than the thermal diffusion coefficient of the first sub-layer 31 .
  • the material of the first sub-layer 31 includes a spin coating compound
  • the material of the second sub-layer 32 includes metal
  • the spin coating compound includes but is not limited to spin coating glass (SOG), etc.
  • the spin coating glass (SOG) can be spin coating in a liquid state (similar to the spin coating of photoresist) onto the semiconductor device.
  • the interlayer dielectric material, the raw materials thereof may include but are not limited to hydrogen silsesquioxane polymers and siloxane solvents, etc.; the materials of the second sub-layer may include, but are not limited to, copper, etc. But it is not limited to this, the material of the second sub-layer can also be other materials with relatively good thermal conductivity.
  • an electroplating process is performed, including:
  • the semiconductor device Immersing the semiconductor device in an electroplating copper solution, the semiconductor device including a seed layer;
  • An electroplated copper layer is formed on the seed layer, wherein the electroplated copper solution includes but is not limited to water, copper supply source, electrolyte material, etc.
  • the presence of the coating layer can effectively prevent the above-mentioned substances from being displaced during the subsequent transfer or packaging process, resulting in the risk of tilting or poor contact in the final formed semiconductor device, thereby improving the final formation of the semiconductor device. It improves the stability and reliability of the device and helps to improve the production yield.
  • the information transmission rate is easily affected by the quality of heat dissipation.
  • the information transmission rate of the semiconductor device will be reduced, prolonging the communication time. What's more, when the heat inside the semiconductor device continues to accumulate, the stability and reliability of the semiconductor device will be greatly affected.
  • the semiconductor device when the material of the cladding layer includes a metal material or other material with good thermal conductivity, the heat generated inside the semiconductor device during operation will be conducted to the semiconductor device through the cladding layer. external. Therefore, in the embodiments of the present disclosure, the semiconductor device can avoid the situation where the information transmission rate is slowed down and the stability and reliability are reduced due to the failure to export heat in time, and the stability and reliability problems of the semiconductor device can be effectively improved.
  • the semiconductor device further includes an encapsulation compound 4 located above the above-mentioned logic chip 21 and covering the cladding layer 30 .
  • the material of the encapsulating compound 4 may be, for example, epoxy resin, phenolic resin, polyimide, silica gel or spin-coated silicon glass.
  • Packaging compound 4 can protect the packaging structure from external dust, moisture and mechanical impact, improving the reliability of the packaging structure.
  • the encapsulation compound may be formed in any of the above structures mentioned in the embodiments of the present disclosure.
  • the existence of the coating layer can effectively prevent particles, powders and other substances generated during the cutting process from being displaced during the subsequent transfer or packaging process, causing the finally formed semiconductor device to tilt or exist.
  • the risk of poor contact improves the stability and reliability of the final device and helps improve production yield.
  • the semiconductor device can avoid the situation where the information transmission rate is slowed down and the stability and reliability are reduced due to the failure to export heat in time, and the stability and reliability problems of the semiconductor device can be effectively improved.
  • a hybrid bonding method is used to perform one-to-one correspondence between adjacent chips. Bonding to form electrical connections can effectively shorten the wiring distance between adjacent chips, shorten the communication distance between chips, effectively improve signal transmission efficiency, and shorten communication time.
  • the second dielectric layer and the first contact pad are formed on the active surface of the second chip.
  • the method of the second contact pad enables face-to-face hybrid bonding between two chips, that is, face-to-face hybrid bonding between adjacent chips. It can be understood that compared with other embodiments, this hybrid bonding and face-to-face bonding method can further shorten the communication distance between two adjacent chips, improve communication efficiency, and more effectively shorten communication time.
  • semiconductor device preparation method and semiconductor device can be applied to any integrated circuit including this structure, including but not limited to the vertical integration of processed integrated circuits, and are used for 3D SOC, Micropad packaging, low-cost and high-performance replacement flip-chip bonding, wafer-level packaging, thermal management, unique device structures (e.g., metal-based devices).
  • Applications further include, but are not limited to, integrated circuits (such as back-illuminated image sensors), RF front-ends, micro-electrical mechanical structures (MEMS) (including but not limited to pico-projectors and gyroscopes) ), 3D stacked memory (including but not limited to hybrid memory cubes), high bandwidth memory (High Band width Memory), DIRAM, 2.5D (including but not limited to FPGA tilted on the insert) and products using these circuits (Including but not limited to mobile phones and other mobile devices, laptops, servers).
  • integrated circuits such as back-illuminated image sensors
  • RF front-ends such as back-illuminated image sensors
  • MEMS micro-electrical mechanical structures (MEMS) (including but not limited to pico-projectors and gyroscopes) ), 3D stacked memory (including but not limited to hybrid memory cubes), high bandwidth memory (High Band width Memory), DIRAM, 2.5D (including but not limited to FPGA tilted on the insert) and products using these circuits
  • the method for preparing a semiconductor device can significantly improve the stability and reliability of the finally formed semiconductor device.
  • the embodiment of the present disclosure does not cut off the carrier when performing the first cutting process, which provides the possibility of forming cladding layers on the sidewalls and upper surfaces of multiple chip stacks at the same time, optimizing the process flow. , which can effectively improve production efficiency.

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Abstract

本公开实施例提供了一种半导体器件的制备方法及半导体器件，其中，所述方法包括：提供载片；提供多个晶圆，每一晶圆包括多个芯片；沿竖直方向将多个晶圆依次堆叠在所述载片上，并使分设在相邻的晶圆上的芯片一一对应键合连接；对多个晶圆执行第一切割工艺，形成位于载片上方且贯穿多个晶圆的多条切割槽，多个晶圆基于切割槽被分割为多个芯片堆叠体，芯片堆叠体包括沿竖直方向堆叠的多个芯片，载片使多个芯片堆叠体处于未分离状态；形成包覆层，包覆层覆盖至少一个芯片堆叠体的侧壁及上表面；沿切割槽对包覆层执行第二切割工艺，形成侧壁及上表面覆盖有包覆层的多个芯片堆叠体。

Description

一种半导体器件的制备方法及半导体器件
相关申请的交叉引用
本公开基于申请号为202210459337.3、申请日为2022年04月27日、发明名称为“一种半导体器件的制备方法及半导体器件”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及了一种半导体器件的制备方法及半导体器件。
背景技术
随着半导体器件朝着小型化、高集成度及多功能化的方向发展，其在使用过程中呈现出的稳定性及可靠性的问题也引起了人们的广泛注意。半导体器件的制造过程作为形成半导体器件的必经阶段，其直接关系到最终形成的半导体器件在使用过程中稳定性和可靠性的表现情况。
然而，在目前的半导体器件的制造过程中，仍存在很多不足之处，如何对其进行优化成为现阶段亟需解决的技术问题。
发明内容
本公开实施例提供了一种半导体器件的制备方法，包括：
提供载片；
提供多个晶圆，每一所述晶圆包括多个芯片；
沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接；
对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体，所述芯片堆叠体包括沿竖直方向堆叠的多个芯片，所述载片使所述多个芯片堆叠体处于未分离状态；
形成包覆层，所述包覆层覆盖至少一个所述芯片堆叠体的侧壁及上表面；
沿所述切割槽对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。
上述方案中，执行第二切割工艺后，所述方法还包括：
将所述载片与所述芯片堆叠体进行分离；
提供逻辑晶圆，所述逻辑晶圆包括至少一个逻辑芯片；
将所述芯片堆叠体与所述逻辑芯片进行键合连接。
上述方案中，形成所述包覆层，包括：
在所述芯片堆叠体上形成晶种层，所述晶种层覆盖所述芯片堆叠体的侧壁及上表面；其中，位于所述芯片堆叠体最顶层的所述芯片的有源面朝下，所述有源面为所述晶圆形成有器件层的一侧；
执行电镀工艺以在所述晶种层上形成包覆层，所述包覆层覆盖所述晶种层。
上述方案中，形成所述包覆层，包括：
执行涂布工艺，以在所述芯片堆叠体的侧壁及上表面上形成第一子层；
在所述第一子层上形成晶种层；
执行电镀工艺，以在所述晶种层上形成第二子层，所述第二子层覆盖所述晶种层。
上述方案中，对所述多个晶圆执行第一切割工艺，包括：
采用晶圆切割刀和/或切割线对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体；
沿所述切割槽对所述包覆层执行第二切割工艺，包括：
采用砂轮、晶圆切割刀、切割线和/或激光切割工艺对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。
上述方案中，提供多个晶圆，每一所述晶圆包括多个芯片，包括：
提供第一晶圆和第二晶圆，所述第一晶圆包括多个第一芯片，所述第二晶圆包括多个第二芯片；
沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接，包括：
在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；
将所述第一晶圆和所述第二晶圆依次层叠设置于所述载片上方，使得所述第一接触衬垫和所述第二接触衬垫对接；
进行键合工艺，使得所述第一接触衬垫与所述第二接触衬垫、所述第一介质层与所述第二介质层相互键合形成混合键合件。
上述方案中，在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；包括：
在所述第一晶圆的有源面上形成第一介质层；
在所述第一介质层上形成至少一个第一通孔；
在所述第一通孔内形成第一接触衬垫，所述第一接触衬垫与所述第一芯片一一对应连接；
在所述第二晶圆的有源面上形成第二介质层；
在所述第二介质层上形成至少一个第二通孔；
在所述第二通孔内形成第二接触衬垫，所述第二接触衬垫与所述第二芯片一一对应连接；其中，所述有源面为所述晶圆形成有器件层的一侧。
上述方案中，在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；包括：
在所述第一晶圆的有源面上形成第一介质层；
在所述第一介质层上形成至少一个第一通孔；
在所述第一通孔内形成第一接触衬垫，所述第一接触衬垫与所述第一芯片一一对应连接；
在所述第二晶圆的非有源面上形成第二介质层；
在所述第二介质层上形成至少一个第二通孔；
在所述第二通孔内形成第二接触衬垫，所述第二接触衬垫与所述第二芯片一一对应连接；其中，所述有源面为所述晶圆形成有器件层的一侧；所述非有源面为所述有源面的相对侧。
上述方案中，将所述芯片堆叠体与所述逻辑芯片进行键合连接；包括：
在所述逻辑晶圆的表面形成至少一个第三接触衬垫，所述第三接触衬垫与所述逻辑芯片一一对应连接；
在所述芯片堆叠体最底层的所述芯片的下表面上形成第四接触衬垫；
将所述芯片堆叠体设置于所述逻辑芯片的上方，所述第三接触垫与所述第四接触垫对接；
进行键合工艺，使得所述第三接触衬垫与所述第四接触衬垫相互键合。
上述方案中，在所述芯片堆叠体与所述逻辑芯片进行键合连接之后，所述方法还包括：
形成封装化合物，所述封装化合物位于所述逻辑芯片上方且所述封装化合物覆盖所述包覆层。
本公开实施例还提供了一种半导体器件，包括：
逻辑芯片；
芯片堆叠体，所述芯片堆叠体包括多个芯片，所述多个芯片沿竖直方向堆叠在所述逻辑芯片上，相邻的所述芯片相互互连；其中，所述芯片堆叠体通过对竖直堆叠的多个晶圆执行切割工艺来形成；
包覆层，所述包覆层位于所述逻辑芯片上方并覆盖所述芯片堆叠体的侧壁及上表面。
上述方案中，所述包覆层的材料包括金属或旋涂化合物。
上述方案中，所述包覆层包括第一子层和第二子层，所述第一子层位于所述第二子层与所述芯片堆叠体之间；其中，所述第二子层的热扩散系数大于所述第一子层的热扩散系数。
上述方案中，所述第一子层的材料包括旋涂化合物，所述第二子层的材料包括金属。
上述方案中，所述多个芯片包括通过混合键合件互连的第一芯片和第二芯片，所述混合键合件 包括：
位于所述第一芯片表面的第一接触衬垫，及位于所述第二芯片表面的第二接触衬垫；
位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；
其中，所述第一接触衬垫和所述第二接触衬垫接触键合，所述第一介质层和所述第二介质层接触键合。
上述方案中，所述第一介质层和所述第一接触衬垫位于所述第一芯片的有源面上，所述第二介质层和所述第二接触衬垫位于所述第二芯片的有源面上，所述第一芯片与所述第二芯片在两者的有源面处键合连接；其中，所述有源面为所述芯片形成有器件层的一侧。
上述方案中，所述第一介质层和所述第一接触衬垫形成在所述第一芯片的有源面，所述第二介质层和所述第二接触衬垫形成在所述第二芯片的非有源面，所述第一芯片的有源面与所述第二芯片的非有源面键合；其中，所述有源面为芯片形成器件层的一侧，所述非有源面为所述有源面的相对侧。
上述方案中，所述逻辑芯片与所述芯片堆叠体之间通过第一键合件来实现互连；所述第一键合件包括：
位于所述逻辑芯片表面的第三接触衬垫；
位于所述芯片堆叠体最底层的所述芯片下表面的第四接触衬垫；
其中，所述逻辑芯片与所述芯片堆叠体之间通过所述第三接触衬垫和所述第四接触衬垫接触键合。
上述方案中，所述第三接触衬垫位于所述逻辑芯片的非有源面上，所述第四接触衬垫位于所述芯片堆叠体最底层的所述芯片的非有源面上，所述逻辑芯片与所述芯片堆叠体在两者的非有源面处键合连接；其中，所述有源面为所述逻辑芯片或所述芯片形成有器件层的一侧，所述非有源面为所述有源面的相对侧。
上述方案中，所述半导体器件还包括封装化合物，所述封装化合物位于所述逻辑芯片上方且所述封装化合物覆盖所述包覆层。
本公开实施例所提供的一种半导体器件的制备方法及半导体器件，其中，所述方法包括：提供载片；提供多个晶圆，每一所述晶圆包括多个芯片；沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接；对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体，所述芯片堆叠体包括沿竖直方向堆叠的多个芯片，所述载片使所述多个芯片堆叠体处于未分离状态；形成包覆层，所述包覆层覆盖至少一个所述芯片堆叠体的侧壁及上表面；沿所述切割槽对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。如此，先在载片上将多个晶圆进行堆叠及键合，接着执行第一切割工艺，此时，只切穿多个晶圆而不切断载片，形成了多个处于未分离状态的芯片堆叠体；紧接着在芯片堆叠体上形成包覆层，包覆层的形成可以将执行第一切割工艺时产生的颗粒等物质包裹、固定在芯片堆叠体的侧壁和上表面上，防止其在后续转移或封装过程中产生移位造成最终形成的半导体器件产生倾斜或存在接触不良的风险。最后通过对包覆层执行第二切割工艺之后即可形成多个侧壁及上表面覆盖有包覆层的芯片堆叠体。因此，本公开实施例提供的半导体器件的制备方法，可显著提高最终形成的半导体器件的稳定性和可靠性。另外，本公开实施例在执行第一次切割工艺时未切断载片的做法，提供了可在多个芯片堆叠体的侧壁和上表面上同时形成包覆层的可能性，优化了工艺流程，可有效提高生产效率。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体器件的制备方法的流程框图；
图2、图3、图4a至图4c、图5a至图5c为本公开实施例提供的半导体器件在制备过程中的工艺流程图；
图6为本公开实施例提供的多个晶圆堆叠在载片上的立体结构示意图；
图7为本公开实施例提供的半导体器件执行第一切割工艺的过程示意图；
图8a和图8b分别为本公开实施例提供的半导体器件执行第一切割工艺后的俯视示意图和局部剖视示意图；
图9a至图9b和图10a至图10c为本公开不同实施例提供的半导体器件形成包覆层的工艺流程图；
图11为本公开实施例提供的半导体器件执行第二切割工艺后形成的芯片堆叠体的剖视示意图；
图12至图14为本公开实施例提供的芯片堆叠体与逻辑晶圆进行键合的工艺流程图；
图15为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的一种结构的剖视示意图；
图16为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的另一种结构的剖视示意图；
图17为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的又一种结构的剖视示意图；
图18为本公开实施例提供的半导体器件形成封装化合物后的一种结构的剖视示意图；
图19为本公开实施例提供的半导体器件形成封装化合物后的另一种结构的剖视示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
随着技术的发展和进步，半导体器件的尺寸进一步微缩，集成度日益提高。然而，除上述变化外，半导体器件在使用过程中的稳定性和可靠性的表现情况也成了人们越来越关心的问题，比如在尺寸微缩的同时如何兼顾散热的问题，以及通过增加接触点的高度来解决散热问题之后，又如何兼顾到因接触点高度增加导致的传输速率变慢的问题等等。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体器件的制备方法，如图1所示，所述方法包括了如下步骤：
步骤S101：提供载片；
步骤S102：提供多个晶圆，每一所述晶圆包括多个芯片；
步骤S103：沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接；
步骤S104：对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体，所述芯片堆叠体包括沿竖直方向堆叠的多个芯片，所述载片使所述多个芯片堆叠体处于未分离状态；
步骤S105：形成包覆层，所述包覆层覆盖至少一个所述芯片堆叠体的侧壁及上表面；
步骤S106：沿所述切割槽对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。
本公开实施例中，先在载片上将多个晶圆进行堆叠及键合，接着执行第一切割工艺，此时，只切穿多个晶圆而不切断载片，形成了多个处于未分离状态的芯片堆叠体；紧接着在芯片堆叠体上形成包覆层，包覆层的形成可以将执行第一切割工艺时产生的颗粒等物质包裹、固定在芯片堆叠体的侧壁和上表面上，防止其在后续转移或封装过程中产生移位造成最终形成的半导体器件产生倾斜或存在接触不良的风险。最后通过对包覆层执行第二切割工艺之后即可形成多个侧壁及上表面覆盖有包覆层的芯片堆叠体。因此，本公开实施例提供的半导体器件的制备方法，可显著提高最终形成的半导体器件的稳定性和可靠性。另外，本公开实施例在执行第一次切割工艺时未切断载片的做法，提供了可在多个芯片堆叠体的侧壁和上表面上同时形成包覆层的可能性，优化了工艺流程，可有效提高生产效率。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1为本公开实施例提供的半导体器件的制备方法的流程框图；图2、图3、图4a至图4c、图5a至图5c为本公开实施例提供的半导体器件在制备过程中的工艺流程图；图6为本公开实施例提供的多个晶圆堆叠在载片上的立体结构示意图；图7为本公开实施例提供的半导体器件执行第一切割工艺的过程示意图；图8a和图8b分别为本公开实施例提供的半导体器件执行第一切割工艺后的俯视示意图和局部剖视示意图；图9a至图9b和图10a至图10c为本公开不同实施例提供的半导体器件形成包覆层的工艺流程图；图11为本公开实施例提供的半导体器件执行第二切割工艺后形成的芯片堆叠体的剖视示意图；图12至图14为本公开实施例提供的芯片堆叠体与逻辑晶圆进行键合的工艺流程图；图15为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的一种结构的剖视示意图；图16为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的另一种结构的剖视示意图；图17为本公开实施例提供的芯片堆叠体与逻辑晶圆键合后形成的又一种结构的剖视示意图；图18为本公开实施例提供的半导体器件形成封装化合物后的一种结构的剖视示意图；图19为本公开实施例提供的半导体器件形成封装化合物后的另一种结构的剖视示意图。
下面附图对本公开实施例提供的半导体器件的制备方法再作进一步详细的说明。
首先，执行步骤S101，如图2所示，提供载片1。
在一些实施例中，所述载片1的材料可以包括但不限于废弃晶圆、玻璃基板、半导体基板或者陶瓷基板等。
接着，执行步骤S102，如图3所示，提供多个晶圆10，每一所述晶圆10包括多个芯片C。
接下来，执行步骤S103，如图4a至图4c、图5a至图5c及图6所示，沿竖直方向将所述多个晶圆10依次堆叠在所述载片1上，并使分设在相邻的所述晶圆10上的所述芯片C一一对应键合连接。
其中，图4a至图4c及图5a至图5c为沿竖直方向将所述多个晶圆10依次堆叠在所述载片1上的局部剖视图。
如图4a至图4c及图5a至图5c所示，在一些实施例中，提供多个晶圆10，每一所述晶圆10包括多个芯片C，包括：
提供第一晶圆W1和第二晶圆W2，所述第一晶圆W1包括多个第一芯片11，所述第二晶圆W2包括多个第二芯片12；
沿竖直方向将所述多个晶圆10依次堆叠在所述载片1上，并使分设在相邻的所述晶圆10上的所述芯片C一一对应键合连接，包括：
在所述第一晶圆W1和所述第二晶圆W2的表面分别形成至少一个第一接触衬垫13和至少一个第二接触衬垫14，以及形成位于所述第一接触衬垫13外围的第一介质层L1和位于所述第二接触衬垫14外围的第二介质层L2；
将所述第一晶圆W1和所述第二晶圆W2依次层叠设置于所述载片1上方，使得所述第一接触衬垫13和所述第二接触衬垫14对接；
进行键合工艺，使得所述第一接触衬垫13与所述第二接触衬垫14、所述第一介质层L1与所述第二介质层L2相互键合形成混合键合件。
在实际工艺中，所述第一介质层的材料包括但不限于氧化物、氮化物、氮氧化物等；所述第二介质层的材料也可以包括但不限于氧化物、氮化物、氮氧化物等；所述第一接触衬垫和所述第二接触衬垫的材料包括但不限于铜、金、银、铝、镍、钨、钛、锡、导电性石墨烯或碳纳米管中的一种或多种形成的合金。这里，所述第一介质层和所述第二介质层的材料可以相同。事实上，也可以采用不同的材料来分别形成所述第一介质层和所述第二介质层，在此不做具体限制。类似的，所述第一接触衬垫和所述第二接触衬垫的材料可以相同，也可以不同，在此不做具体限制。
可以理解的，与传统结构中采用较大的微凸块进行电连接的方式相比，在本公开实施例中，采用混合键合的方式在相邻晶圆的各芯片之间进行一一对应键合来形成电连接的方式，可有效缩短位于相邻晶圆上的对应芯片之间的连线距离，使得芯片之间的通信距离变短，可有效提高信号传输效率，缩短通信时间。
在一些实施例中，如图5a至图5c所示，在所述第一晶圆W1和所述第二晶圆W2的表面分别形成至少一个第一接触衬垫13和至少一个第二接触衬垫14，以及形成位于所述第一接触衬垫13外围的第一介质层L1和位于所述第二接触衬垫14外围的第二介质层L2；包括：
在所述第一晶圆W1的有源面S1上形成第一介质层L1；
在所述第一介质层L1上形成至少一个第一通孔H1；
在所述第一通孔H1内形成第一接触衬垫13，所述第一接触衬垫13与所述第一芯片11一一对应连接；
在所述第二晶圆W2的非有源面S2上形成第二介质层L2；
在所述第二介质层L2上形成至少一个第二通孔H2；
在所述第二通孔H2内形成第二接触衬垫14，所述第二接触衬垫14与所述第二芯片12一一对应连接；其中，所述有源面S1为所述晶圆形成有器件层的一侧；所述非有源面S2为所述有源面的相对侧。
在本公开实施例中，采用混合键合的方式在相邻晶圆的各芯片之间进行一一对应键合来形成电连接的方式，可有效缩短位于相邻晶圆上的对应芯片之间的间隙，使得芯片之间的通信距离缩短，可有效提高信号传输效率，缩短通信时间。
在另一些实施例中，如图4a至图4c所示，在另一些实施例中，在所述第一晶圆W1和所述第二晶圆W2的表面分别形成至少一个第一接触衬垫13和至少一个第二接触衬垫14，以及形成位于所述第一接触衬垫13外围的第一介质层L1和位于所述第二接触衬垫14外围的第二介质层L2；包括：
在所述第一晶圆W1的有源面S1上形成第一介质层L1；
在所述第一介质层L1上形成至少一个第一通孔H1；
在所述第一通孔H1内形成第一接触衬垫13，所述第一接触衬垫13与所述第一芯片11一一对应连接；
在所述第二晶圆W2的有源面S1上形成第二介质层L2；
在所述第二介质层L2上形成至少一个第二通孔H2；
在所述第二通孔H2内形成第二接触衬垫14，所述第二接触衬垫14与所述第二芯片12一一对应连接；其中，所述有源面S1为所述晶圆10形成有器件层的一侧。
这里，所述晶圆10包括所述第一晶圆W1和所述第二晶圆W2；所述芯片C包括所述第一芯片11和所述第二芯片12。
在该实施例中，通过在第一晶圆的有源面形成所述第一介质层和所述第一接触衬垫，在第二晶圆的有源面上形成所述第二介质层和所述第二接触衬垫的方式，使得两个晶圆之间以面对面的方式进行混合键合，也即，相邻晶圆中对应位置的芯片为有源面之间面对面的混合键合方式。可以理解的，与其他实施例相比，通过这种混合键合及面对面键合的方式可进一步缩短相邻的两个芯片之间通信距离，进一步提高通信效率，更有效的缩短通信时间。
需要说明的是，本公开仅示例性的示出了晶圆之间进行键合的一部分实施方式。在实际操作中， 所述第一晶圆和所述第二晶圆之间的键合方式，及所述第一介质层和所述第一接触衬垫及所述第二介质层和所述第二接触衬垫具体形成在所述第一晶圆和第二晶圆上的位置可根据实际情况进行灵活调整。
另外，在本公开实施例的附图中，仅示例性的画出了4个晶圆在载片上进行堆叠、键合的示意图，在实际工艺中，所述晶圆的数量还可以为8个、12个，甚至还可以为其他更多或者更少的数量，在此不做具体限制，可根据需要灵活调整晶圆的数量。
接下来，执行步骤S104，如图7、图8a及图8b所示，对所述多个晶圆10执行第一切割工艺，形成位于所述载片1上方且贯穿所述多个晶圆10的多条切割槽101，所述多个晶圆10基于所述切割槽101被分割为多个芯片堆叠体ST，所述芯片堆叠体ST包括沿竖直方向堆叠的多个芯片C，所述载片1使所述多个芯片堆叠体ST处于未分离状态。
继续参考图7、图8a及图8b，在一些实施例中，对所述多个晶圆10执行第一切割工艺，包括：
采用晶圆切割刀4和/或切割线对所述多个晶圆10执行第一切割工艺，形成位于所述载片1上方且贯穿所述多个晶圆10的多条切割槽101，所述多个晶圆10基于所述切割槽101被分割为多个芯片堆叠体ST。
这里，所述切割线包括但不限于金刚石线等。
可以理解的，在该实施例中，执行第一次切割工艺时未切断载片的做法，提供了可在多个芯片堆叠体的侧壁和上表面上同时形成包覆层的可能性，优化了工艺流程，可有效提高生产效率。
然后，继续执行步骤S105，如图9a至图9b及图10a至图10c所示，形成包覆层30，所述包覆层30覆盖至少一个所述芯片堆叠体ST的侧壁及上表面。
在一些实施例中，如图9a至图9b所示，形成所述包覆层30，包括：
在所述芯片堆叠体ST上形成晶种层33，所述晶种层33覆盖所述芯片堆叠体ST的侧壁及上表面；其中，位于所述芯片堆叠体ST最顶层的所述芯片C的有源面S1朝下，所述有源面S1为所述晶圆形成有器件层的一侧；
执行电镀工艺以在所述晶种层33上形成包覆层30，所述包覆层30覆盖所述晶种层33。
在一些实施例中，所述晶种层和所述包覆层的材料包括但不限于铜等。但不限于此，所述包覆层的材料还可以为其他导热性较好的材料。
在另一些实施例中，如图10a至图10c所示，形成所述包覆层，包括：
执行涂布工艺，以在所述芯片堆叠体ST的侧壁及上表面上形成第一子层31；
在所述第一子层31上形成晶种层33；
执行电镀工艺，以在所述晶种层33上形成第二子层32，所述第二子层32覆盖所述晶种层33。
这里，所述第一子层的材料包括但不限于旋涂玻璃(SOG)等，所述旋涂玻璃(SOG)可以是在液态下旋涂(类似于光致抗蚀剂的旋涂)到半导体结构上的层间介电材料，其原材料可以包括但不限于氢倍半硅氧烷聚合物和硅氧烷溶剂等；所述晶种层和所述第二子层的材料包括但不限于铜等。但不限于此，所述第二子层的材料还可以为其他导热性比较好的材料。
在一些实施例中，当所述包覆层及所述第二子层的材料为铜时，执行电镀工艺，包括：
将所述半导体器件浸渍在电镀铜溶液中，所述半导体器件包括晶种层；
在所述晶种层上形成电镀铜层，其中所述电镀铜溶液包含但不限于水、铜供应源、电解质材料等。
在实际工艺中，参考图8b可以看出，执行切割工艺时，比较容易产生一些颗粒5，所述颗粒5可以包括但不限于在生产过程中产生的碎屑或者粉末等物质，即便在切割工艺后执行清洗工艺也很难将所有这些物质彻底去除。
而在本公开实施例中，综合图9b和图10c，可以看出，所述包覆层30可以将执行第一切割工艺过程中产生的颗粒5包裹起来。
可以理解的，在一些没有形成包覆层的结构中，这些颗粒等物质经常会到处移动，特别是在与其他功能芯片进行封装、接合的过程中，当这些物质移动到两者之间时，很容易造成上方芯片的倾斜，甚至造成最终形成的器件存在接触不良等问题，引发芯片故障甚至失效，降低生产良率。
因此，在本公开实施例中，包覆层的存在可以有效的防止上述物质在后续转移或封装过程中产生移位，造成最终形成的半导体器件产生倾斜或存在接触不良的风险，提高了最终形成的器件的稳定性和可靠性，且有助于生产良率的提高。
另外，在传统的采用微凸块结构的半导体器件中，其信息传输速率容易受到散热情况好坏的影响。当半导体器件内部的热量不能及时传导出去时，半导体器件的信息传输速率会降低，延长了通信时间。更甚者，当半导体器件内部的热量继续积累时，半导体器件的稳定性及可靠性会受到较大 的影响。
而在本公开实施例中，当所述包覆层的材料包括导热性比较好的金属材料或其他材料时，半导体器件在工作过程中内部所产生的热量会经由包覆层传导至半导体器件的外部。因此，在本公开实施例中，半导体器件可避免出现因热量不及时导出导致的信息传输速率减慢，稳定性及可靠性降低的情况，可有效改善半导体器件的稳定性和可靠性问题。
需要说明的是，当所述包覆层的材料为散热性较好的导电材料，且导电材料直接接触所述晶圆时，需要将所述晶圆的有源面即所述晶圆形成有器件层的一侧背离所述包覆层。
最后，执行步骤S106，如图9b及图11所示，沿所述切割槽101对所述包覆层30执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层30的多个芯片堆叠体ST。
沿所述切割槽101对所述包覆层30执行第二切割工艺，包括：
采用砂轮、晶圆切割刀4、切割线和/或激光切割工艺对所述包覆层30执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层30的多个芯片堆叠体ST。
在一些实施例中，如图12至图14所示，执行第二切割工艺后，所述方法还包括：
将所述载片1与所述芯片堆叠体ST进行分离；
提供逻辑晶圆20，所述逻辑晶圆20包括至少一个逻辑芯片21；
将所述芯片堆叠体ST与所述逻辑芯片21进行键合连接。
这里，所述逻辑芯片21可以是被配置为与多个芯片C通信以便从芯片C访问数据并且将数据存储在多个芯片C中的一个或多个处理器。所述逻辑芯片21包括但不限于图形处理单元(GPU)、现场可编程门阵列(FPGA)、专用集成电路(ASIC)、中央处理单元(CPU)或用作处理器的其它已知电子电路。所述芯片C包括但不限于动态随机存取存储器(DRAM)存储器芯片。
继续参考图12至图14，可以看出，将所述芯片堆叠体ST与所述逻辑芯片21进行键合连接；包括：
在所述逻辑晶圆20的表面形成至少一个第三接触衬垫23，所述第三接触衬垫23与所述逻辑芯片21一一对应连接；
在所述芯片堆叠体ST最底层的所述芯片C的下表面上形成第四接触衬垫18；
将所述芯片堆叠体ST设置于所述逻辑芯片21的上方，所述第三接触垫23与所述第四接触垫18对接；
进行键合工艺，使得所述第三接触衬垫23与所述第四接触衬垫18相互键合。
在一些实施例中，形成所述第三接触衬垫23和所述第四接触衬垫18，包括：
在所述逻辑晶圆20的表面形成第三介质层L3；
在所述第三介质层L3上形成所述第三接触衬垫23；以及，
在所述芯片堆叠体ST最底层的所述芯片C的下表面上形成第四介质层L4；
在所述第四介质层L4上形成所述第四接触衬垫18。
这里，所述第三接触衬垫23和所述第四接触衬垫18的材料可以与所述第一接触衬垫13和所述第二接触衬垫14的材料相同，在此不做赘述。
可选的，在芯片堆叠体ST与包含所述逻辑芯片21接合后，将所述方法还包括：在所述逻辑晶圆20背离所述芯片堆叠体ST的表面上形成多个铜柱凸块22(Copper Pillar Bump)。所述铜柱凸块22(Copper Pillar Bump)可用于在所述半导体器件与其他器件，如PCB板之间形成电连接的用途。
在一些实施例中，如图15至17所示，将所述芯片堆叠体ST与包含所述逻辑芯片21的逻辑晶圆20键合后，所述方法还包括：
执行第三切割工艺，将所述逻辑晶圆20进行分割，形成多个垂直分布的结构；其中，所述芯片堆叠体ST与所述逻辑晶圆20从上到下垂直堆叠。其中：
在一些结构中，如图15所示，所述逻辑芯片21的有源面背离所述芯片堆叠体ST。
在另一些结构中，如图16所示，所述第一芯片11和所述第二芯片12为有源面S1之间采用面对面的混合键合方式进行互连。
在又一些结构中，如图17所示，所述第一芯片11的有源面S1和所述第二芯片12非有源面S2之间为混合键合方式进行互连。
可选的，在一些实施例中，位于所述芯片堆叠体ST上的多个接触衬垫之间，及逻辑芯片21与位于芯片堆叠体ST最底层芯片上的多个接触衬垫之间均可通过通孔16来形成互连，以进行通信。这里，所述通孔16可以包括但不限于硅通孔(TSV)等。
在一些实施例中，如图18和图19所示，在所述芯片堆叠体ST与所述逻辑芯片21进行键合连 接之后，所述方法还包括：
形成封装化合物4，所述封装化合物4位于所述逻辑芯片21上方且所述封装化合物4覆盖所述包覆层30。
这里，所述封装化合物4的材料例如可以为环氧树脂，酚醛树脂，聚酰亚胺、硅胶或旋涂硅玻璃等。封装化合物4可以保护封装结构不受外界灰尘、潮气和机械冲击的影响，提高封装结构的可靠性。
本公开实施例还提供了一种半导体器件，如图7、图18所示，包括
逻辑芯片21；
芯片堆叠体ST，所述芯片堆叠体ST包括多个芯片C，所述多个芯片C沿竖直方向堆叠在所述逻辑芯片21上，相邻的所述芯片C相互互连；其中，所述芯片堆叠体ST通过对竖直堆叠的多个晶圆10执行切割工艺来形成；
包覆层30，所述包覆层30位于所述逻辑芯片21上方并覆盖所述芯片堆叠体ST的侧壁及上表面。
这里，所述逻辑芯片21可以是被配置为与多个芯片C通信以便从芯片C访问数据并且将数据存储在多个芯片C中的一个或多个处理器。所述逻辑芯片21包括但不限于图形处理单元(GPU)、现场可编程门阵列(FPGA)、专用集成电路(ASIC)、中央处理单元(CPU)或用作处理器的其它已知电子电路。所述芯片C包括但不限于动态随机存取存储器(DRAM)存储器芯片。
在一些实施例中，所述多个芯片C包括通过混合键合件互连的第一芯片11和第二芯片12，所述混合键合件包括：
位于所述第一芯片11表面的第一接触衬垫13，及位于所述第二芯片12表面的第二接触衬垫14；
位于所述第一接触衬垫13外围的第一介质层L1和位于所述第二接触衬垫14外围的第二介质层L2；
其中，所述第一接触衬垫13和所述第二接触衬垫14接触键合，所述第一介质层L1和所述第二介质层L2接触键合。
可以理解的，与传统结构中采用较大的微凸块进行电连接的方式相比，在本公开实施例中，采用混合键合的方式在相邻芯片之间进行一一对应键合来形成电连接的方式，可有效缩短位于相邻芯片之间的连线距离，使得芯片之间的通信距离变短，可有效提高信号传输效率，缩短通信时间。
在一些实施例中，如图17所示，所述第一介质层L1和所述第一接触衬垫13形成在所述第一芯片11的有源面S1，所述第二介质层L2和所述第二接触衬垫14形成在所述第二芯片12的非有源面S2，所述第一芯片11的有源面S1与所述第二芯片12的非有源面S2键合；其中，所述有源面S1为芯片形成器件层的一侧，所述非有源面S2为所述有源面S1的相对侧。
在本公开实施例中，采用混合键合的方式在相邻芯片之间进行一一对应键合来形成电连接的方式，可有效缩短位于相邻芯片之间的间隙，使得芯片之间的通信距离缩短，可有效提高信号传输效率，缩短通信时间。
在一些实施例中，如图16所示，所述第一介质层L1和所述第一接触衬垫13位于所述第一芯片11的有源面S1上，所述第二介质层L2和所述第二接触衬垫14位于所述第二芯片12的有源面S1上，所述第一芯片11与所述第二芯片12在两者的有源面S1处键合连接；其中，所述有源面S1为所述芯片形成有器件层的一侧。
在该实施例中，通过在第一芯片的有源面形成所述第一介质层和所述第一接触衬垫，在第二芯片的有源面上形成所述第二介质层和所述第二接触衬垫的方式，使得两个芯片之间以面对面的方式进行混合键合，也即，相邻芯片之间为面对面的混合键合方式。可以理解的，与其他实施例相比，通过这种混合键合及面对面键合的方式可进一步缩短了相邻的两个芯片之间的通信距离，进一步提高通信效率，更有效的缩短通信时间。
需要说明的是，本公开仅示例性的示出了芯片之间进行键合的一部分实施方式。在实际操作中，所述第一芯片和所述第二芯片之间的键合方式，及所述第一介质层和所述第一接触衬垫及所述第二介质层和所述第二接触衬垫具体形成在所述第一芯片和第二芯片上的位置可根据实际情况进行灵活调整。
另外，在本公开实施例的附图中，仅示例性的画出了4个芯片在逻辑芯片上进行堆叠、键合的示意图，在实际工艺中，所述芯片的数量还可以为8个、12个，甚至还可以为其他更多或者更少的数量，在此不做具体限制，可根据需要灵活调整芯片的数量。
在一些实施例中，继续参考图15，可以看出，所述逻辑芯片21与所述芯片堆叠体ST之间通过 第一键合件来实现互连；所述第一键合件包括：
位于所述逻辑芯片21表面的第三接触衬垫23；
位于所述芯片堆叠体ST最底层的所述芯片C下表面的第四接触衬垫18；
其中，所述逻辑芯片21与所述芯片堆叠体ST之间通过所述第三接触衬垫23和所述第四接触衬垫18接触键合。
在一些实施例中，所述第三接触衬垫23位于所述逻辑芯片21的非有源面S2上，所述第四接触衬垫18位于所述芯片堆叠体ST最底层的所述芯片C的非有源面S2上，所述逻辑芯片21与所述芯片堆叠体ST在两者的非有源面S2处键合连接；其中，所述有源面S1为所述逻辑芯片21或所述芯片C形成有器件层的一侧，所述非有源面为S2所述有源面S1的相对侧。
在本公开实施例中，所述第三接触衬垫和所述第四接触衬垫形成的位置还可以为其他可能的组合方式，本公开不做过多限制。
可以理解的，将所述逻辑芯片的有源面背离所述芯片堆叠体可有效防止热量产生聚集，避免半导体器件的温度过高影响稳定性和可靠性。当该结构搭载的芯片堆叠体为芯片的有源面之间通过面对面的方式混合键合时，所述半导体器件的通信速率和散热效果均可以达到较佳的水平。
可选的，在一些实施例中，如图15所示，所述半导体器件还包括通孔16，所述通孔16可使得位于所述芯片堆叠体ST上的多个接触衬垫之间，及逻辑芯片21与位于芯片堆叠体ST最底层芯片上的多个接触衬垫之间彼此互连，以进行通信。这里，所述通孔16可以包括但不限于硅通孔(TSV)等。
可选的，在一些实施例中，所述半导体器件还包括铜柱凸块22(Copper Pillar Bump)，所述铜柱凸块22(Copper Pillar Bump)位于所述逻辑芯片21背离所述芯片堆叠体ST的表面。所述铜柱凸块22(Copper Pillar Bump)可用于在所述半导体器件与其他器件，如PCB板之间形成电连接的用途。
在半导体器件的制备过程中，常需要对制备好的晶圆执行切割工艺以形成多个芯片，而在切割工艺时容易产生一些颗粒等物质，即便在切割工艺后执行清洗工艺也很难将所有这些物质彻底去除。
而在本公开实施例中，结合图8b及图15至图19，可以看出，所述包覆层30可以将颗粒5包裹起来，
在一些实施例中，所述包覆层30的材料包括金属或旋涂化合物。具体的，所述金属材料可以包括但不限于铜等；所述旋涂化合物可以包括但不限于旋涂玻璃(SOG)等。
如图18所示，所述包覆层30可以为一层材料。具体的，所述材料可以包括但不限于金属等导热性比较好的材料。
在该实施例中，当所述包覆层的材料为导热性较好的导电材料，且导电材料直接接触所述芯片时，需要将所述芯片的有源面即所述芯片形成有器件层的一侧背离所述包覆层。
如图19所示，在另一些实施例中，所述包覆层30包括第一子层31和第二子层32，所述第一子层31位于所述第二子层32与所述芯片堆叠体ST之间；其中，所述第二子层32的热扩散系数大于所述第一子层31的热扩散系数。
可选的，所述第一子层31的材料包括旋涂化合物，所述第二子层32的材料包括金属。
这里，所述旋涂化合物包括但不限于旋涂玻璃(SOG)等，所述旋涂玻璃(SOG)可以是在液态下旋涂(类似于光致抗蚀剂的旋涂)到半导体器件上的层间介电材料，其原材料可以包括但不限于氢倍半硅氧烷聚合物和硅氧烷溶剂等；所述第二子层的材料包括但不限于铜等。但不限于此，所述第二子层的材料还可以为其他导热性比较好的材料。
在实际工艺中，当所述包覆层及所述第二子层的材料为铜时，执行电镀工艺，包括：
将所述半导体器件浸渍在电镀铜溶液中，所述半导体器件包括晶种层；
在所述晶种层上形成电镀铜层，其中所述电镀铜溶液包含但不限于水、铜供应源、电解质材料等。
可以理解的，在一些没有形成包覆层的结构中，这些颗粒等物质经常会到处移动，特别是在与其他功能芯片进行封装、接合的过程中，当这些物质移动到两者之间时，很容易造成上方芯片的倾斜，甚至造成最终形成的器件存在接触不良等问题，引发芯片故障甚至失效，降低生产良率。
因此，在本公开实施例中，包覆层的存在可以有效的防止上述物质在后续转移或封装过程中产生移位，导致最终形成的半导体器件产生倾斜或存在接触不良的风险，提高了最终形成的器件的稳定性和可靠性，且有助于生产良率的提高。
另外，在传统的采用微凸块结构的半导体器件中，其信息传输速率容易受到散热情况好坏的影响。当半导体器件内部的热量不能及时传导出去时，半导体器件的信息传输速率会降低，延长了通 信时间。更甚者，当半导体器件内部的热量继续积累时，半导体器件的稳定性及可靠性会受到较大的影响。
而在本公开实施例中，当所述包覆层的材料包括导热性较好的金属材料或其他材料时，半导体器件在工作过程中内部所产生的热量会经由包覆层传导至半导体器件的外部。因此，在本公开实施例中，半导体器件可避免出现因热量不及时导出导致的信息传输速率减慢，稳定性及可靠性降低的情况，可有效改善半导体器件的稳定性和可靠性问题。
在实际工艺中，继续参考图18和图19，所述半导体器件还包括封装化合物4，所述封装化合物4位于上述所述逻辑芯片21上方且所述封装化合物4覆盖所述包覆层30。
这里，所述封装化合物4的材料例如可以为环氧树脂，酚醛树脂，聚酰亚胺、硅胶或旋涂硅玻璃等。封装化合物4可以保护封装结构不受外界灰尘、潮气和机械冲击的影响，提高封装结构的可靠性。
可以理解的，在本公开实施例中，所述封装化合物可形成在本公开实施例所提及的上述任一种结构中。
综上所述，在本公开实施例中，包覆层的存在可有效防止切割过程中产生的颗粒、粉末等物质在后续转移或封装过程中产生移位造成最终形成的半导体器件产生倾斜或存在接触不良的风险，提高了最终形成的器件的稳定性和可靠性，且有助于生产良率的提高。
且当所述包覆层的材料包括导热性比较好的金属材料或其他材料时，半导体器件在工作过程中内部所产生的热量会经由包覆层传导至半导体器件的外部。因此，在本公开实施例中，半导体器件可避免出现因热量不及时导出导致的信息传输速率减慢，稳定性及可靠性降低的情况，可有效改善半导体器件的稳定性和可靠性问题。
此外，本公开实施例中，与传统结构中采用较大的微凸块进行电连接的方式相比，在本公开实施例中，采用混合键合的方式在相邻芯片之间进行一一对应键合来形成电连接的方式，可有效缩短位于相邻芯片之间的连线距离，使得芯片之间的通信距离变短，可有效提高信号传输效率，缩短通信时间。
且在本公开实施例中，通过在第一芯片的有源面形成所述第一介质层和所述第一接触衬垫，在第二芯片的有源面上形成所述第二介质层和所述第二接触衬垫的方式，使得两个芯片之间以面对面的方式进行混合键合，也即，相邻芯片之间为面对面的混合键合方式。可以理解的，与其他实施例相比，通过这种混合键合及面对面键合的方式可进一步缩短相邻的两个芯片之间的通信距离，提高通信效率，更有效的缩短通信时间。
另外，在所述逻辑芯片的有源面背离所述芯片堆叠体的结构中，可有效防止热量产生聚集，避免半导体器件的温度过高影响稳定性和可靠性。当该结构搭载的芯片堆叠体为芯片的有源面之间通过面对面的方式混合键合时，所述半导体器件的通信速率和散热效果均可以达到较佳的水平。
需要说明的是，本公开实施例提供的半导体器件的制备方法及半导体器件可以应用于任何包括该结构的集成电路中，包括但不限于经处理的集成电路的垂直整合，而用于3D SOC、微衬垫封装、低成本和高效能的取代覆晶接合，晶圆级封装、热管理、独特装置结构(例如金属基底装置)。应用进一步包括但不限于集成电路(像是背面照明的影像传感器)、RF前端、微机电结构(micro-electrical mechanical structure，MEMS)(包括但不限于皮米投影器(pico-projector)和陀螺仪)、3D堆栈内存(包括但不限于混合型记忆方块)、高带宽内存(High Band width Memory)、DIRAM、2.5D(包括但不限于在插置物上倾斜的FPGA)和当中使用这些电路的产品(包括但不限于移动电话和其他行动装置、膝上型计算机、服务器)。
各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。本领域技术人员能够对上述形成方法步骤顺序进行变换而并不离开本公开的保护范围，本公开实施例中的各步骤在不冲突的情况下，部分步骤可以同时执行，也可以调用先后顺序执行。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供的半导体器件的制备方法，可显著提高最终形成的半导体器件的稳定性和可靠性。另外，本公开实施例在执行第一次切割工艺时未切断载片的做法，提供了可在多个芯片堆叠体的侧壁和上表面上同时形成包覆层的可能性，优化了工艺流程，可有效提高生产效率。

Claims (20)

  1. 一种半导体器件的制备方法，包括：
    提供载片；
    提供多个晶圆，每一所述晶圆包括多个芯片；
    沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接；
    对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体，所述芯片堆叠体包括沿竖直方向堆叠的多个芯片，所述载片使所述多个芯片堆叠体处于未分离状态；
    形成包覆层，所述包覆层覆盖至少一个所述芯片堆叠体的侧壁及上表面；
    沿所述切割槽对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。
  2. 根据权利要求1所述的方法，其中，执行第二切割工艺后，所述方法还包括：
    将所述载片与所述芯片堆叠体进行分离；
    提供逻辑晶圆，所述逻辑晶圆包括至少一个逻辑芯片；
    将所述芯片堆叠体与所述逻辑芯片进行键合连接。
  3. 根据权利要求1所述的方法，其中，形成所述包覆层，包括：
    在所述芯片堆叠体上形成晶种层，所述晶种层覆盖所述芯片堆叠体的侧壁及上表面；其中，位于所述芯片堆叠体最顶层的所述芯片的有源面朝下，所述有源面为所述晶圆形成有器件层的一侧；
    执行电镀工艺以在所述晶种层上形成包覆层，所述包覆层覆盖所述晶种层。
  4. 根据权利要求1所述的方法，其中，形成所述包覆层，包括：
    执行涂布工艺，以在所述芯片堆叠体的侧壁及上表面上形成第一子层；
    在所述第一子层上形成晶种层；
    执行电镀工艺，以在所述晶种层上形成第二子层，所述第二子层覆盖所述晶种层。
  5. 根据权利要求1所述的方法，其中，对所述多个晶圆执行第一切割工艺，包括：
    采用晶圆切割刀和/或切割线对所述多个晶圆执行第一切割工艺，形成位于所述载片上方且贯穿所述多个晶圆的多条切割槽，所述多个晶圆基于所述切割槽被分割为多个芯片堆叠体；
    沿所述切割槽对所述包覆层执行第二切割工艺，包括：
    采用砂轮、晶圆切割刀、切割线和/或激光切割工艺对所述包覆层执行第二切割工艺，形成侧壁及上表面覆盖有所述包覆层的多个芯片堆叠体。
  6. 根据权利要求1所述的方法，其中，提供多个晶圆，每一所述晶圆包括多个芯片，包括：
    提供第一晶圆和第二晶圆，所述第一晶圆包括多个第一芯片，所述第二晶圆包括多个第二芯片；
    沿竖直方向将所述多个晶圆依次堆叠在所述载片上，并使分设在相邻的所述晶圆上的所述芯片一一对应键合连接，包括：
    在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；
    将所述第一晶圆和所述第二晶圆依次层叠设置于所述载片上方，使得所述第一接触衬垫和所述第二接触衬垫对接；
    进行键合工艺，使得所述第一接触衬垫与所述第二接触衬垫、所述第一介质层与所述第二介质层相互键合形成混合键合件。
  7. 根据权利要求6所述的方法，其中，在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；包括：
    在所述第一晶圆的有源面上形成第一介质层；
    在所述第一介质层上形成至少一个第一通孔；
    在所述第一通孔内形成第一接触衬垫，所述第一接触衬垫与所述第一芯片一一对应连接；
    在所述第二晶圆的有源面上形成第二介质层；
    在所述第二介质层上形成至少一个第二通孔；
    在所述第二通孔内形成第二接触衬垫，所述第二接触衬垫与所述第二芯片一一对应连接；其中，所述有源面为所述晶圆形成有器件层的一侧。
  8. 根据权利要求6所述的方法，其中，在所述第一晶圆和所述第二晶圆的表面分别形成至少一个第一接触衬垫和至少一个第二接触衬垫，以及形成位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；包括：
    在所述第一晶圆的有源面上形成第一介质层；
    在所述第一介质层上形成至少一个第一通孔；
    在所述第一通孔内形成第一接触衬垫，所述第一接触衬垫与所述第一芯片一一对应连接；
    在所述第二晶圆的非有源面上形成第二介质层；
    在所述第二介质层上形成至少一个第二通孔；
    在所述第二通孔内形成第二接触衬垫，所述第二接触衬垫与所述第二芯片一一对应连接；其中，所述有源面为所述晶圆形成有器件层的一侧；所述非有源面为所述有源面的相对侧。
  9. 根据权利要求2所述的方法，其中，将所述芯片堆叠体与所述逻辑芯片进行键合连接；包括：
    在所述逻辑晶圆的表面形成至少一个第三接触衬垫，所述第三接触衬垫与所述逻辑芯片一一对应连接；
    在所述芯片堆叠体最底层的所述芯片的下表面上形成第四接触衬垫；
    将所述芯片堆叠体设置于所述逻辑芯片的上方，所述第三接触垫与所述第四接触垫对接；
    进行键合工艺，使得所述第三接触衬垫与所述第四接触衬垫相互键合。
  10. 根据权利要求2所述的方法，其中，在所述芯片堆叠体与所述逻辑芯片进行键合连接之后，所述方法还包括：
    形成封装化合物，所述封装化合物位于所述逻辑芯片上方且所述封装化合物覆盖所述包覆层。
  11. 一种半导体器件，包括：
    逻辑芯片；
    芯片堆叠体，所述芯片堆叠体包括多个芯片，所述多个芯片沿竖直方向堆叠在所述逻辑芯片上，相邻的所述芯片相互互连；其中，所述芯片堆叠体通过对竖直堆叠的多个晶圆执行切割工艺来形成；
    包覆层，所述包覆层位于所述逻辑芯片上方并覆盖所述芯片堆叠体的侧壁及上表面。
  12. 根据权利要求11所述的器件，其中，所述包覆层的材料包括金属或旋涂化合物。
  13. 根据权利要求11所述的器件，其中，所述包覆层包括第一子层和第二子层，所述第一子层位于所述第二子层与所述芯片堆叠体之间；其中，所述第二子层的热扩散系数大于所述第一子层的热扩散系数。
  14. 根据权利要求13所述的器件，其中，所述第一子层的材料包括旋涂化合物，所述第二子层的材料包括金属。
  15. 根据权利要求11所述的器件，其中，所述多个芯片包括通过混合键合件互连的第一芯片和第二芯片，所述混合键合件包括：
    位于所述第一芯片表面的第一接触衬垫，及位于所述第二芯片表面的第二接触衬垫；
    位于所述第一接触衬垫外围的第一介质层和位于所述第二接触衬垫外围的第二介质层；
    其中，所述第一接触衬垫和所述第二接触衬垫接触键合，所述第一介质层和所述第二介质层接触键合。
  16. 根据权利要求15所述的器件，其中，所述第一介质层和所述第一接触衬垫位于所述第一芯片的有源面上，所述第二介质层和所述第二接触衬垫位于所述第二芯片的有源面上，所述第一芯片与所述第二芯片在两者的有源面处键合连接；其中，所述有源面为所述芯片形成有器件层的一侧。
  17. 根据权利要求15所述的器件，其中：
    所述第一介质层和所述第一接触衬垫形成在所述第一芯片的有源面，所述第二介质层和所述第二接触衬垫形成在所述第二芯片的非有源面，所述第一芯片的有源面与所述第二芯片的非有源面键合；其中，所述有源面为芯片形成器件层的一侧，所述非有源面为所述有源面的相对侧。
  18. 根据权利要求11所述的器件，其中，所述逻辑芯片与所述芯片堆叠体之间通过第一键合件来实现互连；所述第一键合件包括：
    位于所述逻辑芯片表面的第三接触衬垫；
    位于所述芯片堆叠体最底层的所述芯片下表面的第四接触衬垫；
    其中，所述逻辑芯片与所述芯片堆叠体之间通过所述第三接触衬垫和所述第四接触衬垫接触键合。
  19. 根据权利要求18所述的器件，其中，所述第三接触衬垫位于所述逻辑芯片的非有源面上，所述第四接触衬垫位于所述芯片堆叠体最底层的所述芯片的非有源面上，所述逻辑芯片与所述芯片堆叠体在两者的非有源面处键合连接；其中，所述有源面为所述逻辑芯片或所述芯片形成有器件层的一侧，所述非有源面为所述有源面的相对侧。
  20. 根据权利要求11所述的器件，其中，所述半导体器件还包括封装化合物，所述封装化合物位于所述逻辑芯片上方且所述封装化合物覆盖所述包覆层。
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