WO2024066466A1 - 集成电路封装结构及制备方法 - Google Patents

集成电路封装结构及制备方法 Download PDF

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Publication number
WO2024066466A1
WO2024066466A1 PCT/CN2023/099211 CN2023099211W WO2024066466A1 WO 2024066466 A1 WO2024066466 A1 WO 2024066466A1 CN 2023099211 W CN2023099211 W CN 2023099211W WO 2024066466 A1 WO2024066466 A1 WO 2024066466A1
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Prior art keywords
layer
chip
substrate
rewiring
rewiring layer
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PCT/CN2023/099211
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English (en)
French (fr)
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陈彦亨
林正忠
杨进
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024066466A1 publication Critical patent/WO2024066466A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Definitions

  • the present invention relates to the field of semiconductor packaging, and in particular to an integrated circuit packaging structure and a preparation method thereof.
  • an object of the present invention is to provide an integrated circuit packaging structure and a preparation method for solving the problems of low bandwidth, high inter-chip delay and high packaging cost caused by the existing packaging technology.
  • the present invention provides a method for preparing an integrated circuit packaging structure, comprising the following steps:
  • a photosensitive dry film dielectric layer and a copper dual damascene process are used to form a rewiring layer on the separation layer, wherein the rewiring layer includes a first rewiring layer and a second rewiring layer stacked together, and the rewiring layer includes a first surface in contact with the separation layer and a second surface opposite to the separation layer;
  • packaging layer covers the chip and the rewiring layer
  • a substrate is provided, and the substrate is bonded to the first surface of the rewiring layer and electrically connected to the rewiring layer.
  • the step of forming the first rewiring layer includes:
  • An electroplating layer is formed on the Ti/Cu seed layer through an electroplating process, and a planarization process is performed on the electroplating layer.
  • a first metal wiring portion is formed in the first rewiring layer
  • a second metal wiring portion is formed in the second rewiring layer
  • the first metal wiring portion is electrically connected to the second metal wiring portion in a vertical direction.
  • the method further includes forming a heat dissipation cover plate on the substrate or forming a reinforcement member on the substrate.
  • the chip includes a first chip and a second chip, and the second chip is symmetrically distributed on both sides of the first chip, the first chip includes a logic chip, and the second chip includes a memory chip.
  • the method further includes performing a planarization process on the packaging layer to expose the chip.
  • the present invention also provides an integrated circuit packaging structure, which includes: a substrate; a rewiring layer, the rewiring layer includes a first surface in contact with the substrate and a second surface opposite to the substrate, the rewiring layer uses a photosensitive dry film dielectric layer, the rewiring layer at least includes a first rewiring layer and a second rewiring layer stacked together; a chip, the chip is located on the second surface of the rewiring layer and is electrically connected to the rewiring layer; and a packaging layer, the packaging layer covers the chip and the rewiring layer.
  • the thickness of the first rewiring layer is in the range of 1 to 20 ⁇ m
  • the thickness of the second rewiring layer is in the range of 1 to 20 ⁇ m.
  • a first metal wiring portion is formed in the first rewiring layer
  • a second metal wiring portion is formed in the second rewiring layer
  • the first metal wiring portion is electrically connected to the second metal wiring portion in a vertical direction.
  • it also includes a heat dissipation cover plate formed on the substrate, which covers the packaging layer and is mechanically connected to the substrate; or a reinforcement member formed on the substrate, the height of the reinforcement member is greater than the height of the packaging layer and is mechanically connected to the substrate.
  • the integrated circuit packaging structure and preparation method of the present invention have the following beneficial effects: integrating a variety of chips with different functions into one packaging structure to improve the integration of the packaging structure; using high-resolution dry film polymers to form a more sophisticated rewiring layer structure, thereby increasing the bandwidth of the device and reducing the delay between chips; at the same time, compared with the prior art, high-density wiring capabilities can be achieved without forming an intermediate layer with TSV, so the cost required is lower.
  • FIG. 1 is a flow chart showing a method for preparing an integrated circuit package structure provided in an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a temporary substrate and a separation layer provided in an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a first photosensitive dry film dielectric layer after photolithography provided in an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a second photosensitive dry film dielectric layer after photolithography provided in an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a structure after forming an electroplating layer according to an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view showing a planarization process performed on the electroplating layer according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view showing a second redistribution layer after formation according to an embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view of a chip formed according to an embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view showing a packaging layer after forming the packaging layer according to an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a thinned packaging layer according to an embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view showing a method of removing the temporary substrate and the separation layer according to an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of the substrates after bonding provided in an embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional view showing a heat dissipation cover plate after it is formed according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram showing the structure of another packaging structure provided in an embodiment of the present invention.
  • spatially relative terms such as “under,” “below,” “below,” “below,” “above,” “on,” etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • the present invention provides a method for preparing an integrated circuit packaging structure, comprising the following steps:
  • S6 providing a substrate 108 , bonding the substrate 108 to the first surface 1031 of the rewiring layer, and electrically connecting the substrate 108 to the rewiring layer 103 .
  • step S1 referring to FIG. 1 and FIG. 2 , a temporary substrate 101 is provided, and a separation layer 102 is formed on the temporary substrate 101 .
  • the temporary substrate 101 includes one of a silicon oxide substrate, a glass substrate, a ceramic substrate, and a polymer substrate, and its shape can be circular, square, or any other desired shape.
  • a separation layer 102 is formed on the temporary substrate 101, and the separation layer 102 includes a LTHC light-to-heat conversion material layer, which has the characteristics of being able to adhere to other components and undergoing degeneration and peeling after laser irradiation.
  • the temporary substrate 101 is a glass substrate, which has a low cost, is easy to form a separation layer on its surface, and reduces the difficulty of subsequent separation processes.
  • step S2 a photosensitive dry film dielectric layer and a copper dual damascene process are used to form a rewiring layer 103 on the separation layer 102, and the rewiring layer 103 includes a stacked first rewiring layer 104 and a second rewiring layer 105, and the rewiring layer 103 includes a first surface 1031 in contact with the separation layer 102 and an opposite second surface 1032.
  • the first photosensitive dry film dielectric layer 1041 is formed on the separation layer 102, and the first photosensitive dry film dielectric layer 1041 is used as a mask to etch the temporary substrate 101 to form the first opening 1043;
  • the second photosensitive dry film dielectric layer 1042 is formed on the first photosensitive dry film dielectric layer 1041, and the second photosensitive dry film dielectric layer 1042 is used as a mask to etch the second photosensitive dry film dielectric layer 1042 to form a second opening 1044 that is intersecting with the first opening 1043; and a second photosensitive dry film dielectric layer 1042 is deposited on the temporary substrate 101.
  • a Ti/Cu seed layer (not shown) is formed, wherein the Ti/Cu seed layer must completely cover the surface of the second photosensitive dry film dielectric layer 1042, the first opening 1043 and the second opening 1044; then, the first opening 1043 and the second opening 1044 are overfilled on the Ti/Cu seed layer through an electroplating process to form the electroplated layer as shown in FIG. 5; as shown in FIG. 6, once the second photosensitive dry film dielectric layer 1042, the first opening 1043 and the second opening 1044 have been over-covered, a planarization process may be performed to remove excess electroplated layer.
  • the material of the electroplating layer includes one of copper, aluminum, nickel, gold, silver and titanium.
  • the electroplating layer can be formed by a deposition process such as electroplating.
  • the planarization process may include a combination of one or more processes of a grinding process, a chemical mechanical polishing process, a dry polishing process, an etching process, and a cutting process.
  • the first opening 1043 and the second opening 1044 are The surface of the opening 1044 is substantially flush with the surface of the electroplating layer.
  • a second rewiring layer 105 is formed on the first rewiring layer 104, and the first rewiring layer 104 is electrically connected to the second rewiring layer 105.
  • the steps of forming the second rewiring layer 105 are the same as the steps of forming the first rewiring layer 104, which will not be repeated here.
  • a first metal wiring portion 1045 is formed in the first rewiring layer 104
  • a second metal wiring portion 1046 is formed in the second rewiring layer 105
  • the first metal wiring portion 1045 is electrically connected to the second metal wiring portion 1046 in a vertical direction.
  • step S3 referring to FIG. 1 and FIG. 8 , a chip 106 is bonded on the second surface 1032 of the re-distribution layer, and the chip 106 is electrically connected to the re-distribution layer 103 .
  • the chip 106 includes a first chip 1061 and a second chip 1062 , and the second chip 1062 is symmetrically distributed on both sides of the first chip 1061 , the first chip 1061 includes a logic chip, and the second chip 1062 includes a memory chip.
  • the first chip 1061 and the second chip 1062 can be any existing semiconductor chips suitable for packaging structures, for example, they can be system chips, logic chips, memory chips, or storage chips such as HBM, etc., and can be configured according to actual needs without any special restrictions.
  • the second chip 1062 and the first chip 1061 may be chips of different types and the second chip 1062 is preferably symmetrically distributed on both sides of the first chip 1061 and electrically connected to the first rewiring layer 103 .
  • the first chip 1061 is a logic (SOC) chip
  • the second chip 1062 is a memory (HBM) chip
  • the second chip 1062 is symmetrically distributed on both sides of the first chip 1061.
  • the first chip 1061 and the second chip 1062 can also be chips of other forms, which are not strictly limited in this embodiment.
  • step S4 referring to FIG. 1 and FIG. 9 , a packaging layer 107 is formed, and the packaging layer 107 covers the chip 106 and the rewiring layer 103.
  • the process for forming the encapsulation layer 107 includes one of a compression molding process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process and a spin coating process; the encapsulation layer 107 includes one of an epoxy resin layer, a polyimide layer and a silicone layer.
  • the method further includes performing a planarization process on the encapsulation layer 107 to expose the chip 106 .
  • the planarization process may include a grinding process, a CMP process, a dry grinding process, an etching process, a cutting process, or a combination of processes.
  • the top surface of the encapsulation layer 107 is aligned with the first chip 1061.
  • the top surface of the second chip 1062 is substantially flush.
  • step S5 referring to FIG. 1 and FIG. 11 , the temporary substrate 101 and the separation layer 102 are removed to expose the first surface 1031 of the re-distribution layer.
  • the method further includes forming an array of metal bumps (not shown) distributed on the first surface 1031 of the rewiring layer, wherein the metal bumps are electrically connected to the rewiring layer 103 .
  • the metal bump includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball.
  • the metal bump is a copper-tin solder ball
  • its manufacturing steps include: first forming a copper-tin layer, then using a high-temperature reflow process to reflow the copper-tin layer into a spherical shape, and forming a copper-tin solder ball after cooling; or using a ball planting process to form a copper-tin solder ball.
  • step S6 referring to FIG. 1 and FIG. 12 , a substrate 108 is provided, and the substrate 108 is bonded to the first surface 1031 of the re-distribution layer and electrically connected to the re-distribution layer 103 .
  • the substrate 108 includes one of a silicon oxide substrate, a glass substrate, a ceramic substrate, and a polymer substrate, and the substrate 110 is electrically connected to the rewiring layer 103 through the metal bumps.
  • a heat dissipation cover plate 109 may be formed on the substrate 108 or a reinforcement member 110 may be formed on the substrate 108 .
  • a heat dissipation cover plate 109 is formed on the substrate 108 , and the heat dissipation cover plate 109 covers the packaging layer 107 , the chip 106 and the rewiring layer 103 .
  • the heat dissipation cover plate 109 is made of metal or ceramic, and the heat dissipation cover plate 109 is mechanically connected to the substrate 108 .
  • adhesive members are formed at both ends of the substrate 110 , and the heat dissipation cover plate 109 and the substrate 108 are connected via the adhesive members.
  • a reinforcing member 110 may be further formed on the substrate 108 , the reinforcing member 110 is mechanically connected to the substrate 108 , and the height of the reinforcing member 110 is greater than the height of the encapsulation layer 107 .
  • this embodiment provides an integrated circuit packaging structure, including: a substrate 110; a rewiring layer 103, the rewiring layer 103 including a first surface 1031 in contact with the substrate 108 and an opposite second surface 1032, the rewiring layer 103 uses a photosensitive dry film dielectric layer, and the rewiring layer 103 at least includes a stacked first rewiring layer 104 and a second rewiring layer 105; a chip 106, the chip 106 is located on the second surface 1032 of the rewiring layer and is electrically connected to the rewiring layer 103; a packaging layer 107, the packaging layer 107 covers the chip 106 and the rewiring layer 103.
  • the thickness of the first rewiring layer 104 is in the range of 1 to 20 ⁇ m, for example, 1 ⁇ m, 5 ⁇ m, 10 ⁇ m or 20 ⁇ m.
  • the thickness of the second rewiring layer 105 is in the range of 1 to 20 ⁇ m, for example, 1 ⁇ m, 5 ⁇ m, 10 ⁇ m or 20 ⁇ m.
  • a first metal wiring portion 1045 is formed in the first rewiring layer 104
  • a second metal wiring portion 1046 is formed in the second rewiring layer 105
  • the first metal wiring portion 1045 is electrically connected to the second metal wiring portion 1046 in the vertical direction.
  • it also includes a heat dissipation cover plate 109 formed on the substrate 108, the heat dissipation cover plate 109 covers the packaging layer 107 and is mechanically connected to the substrate 108; or a reinforcement member 110 formed on the substrate 108, the height of the reinforcement member 110 is greater than the height of the packaging layer 107 and is mechanically connected to the substrate 108.
  • the present invention provides an integrated circuit packaging structure and a preparation method, the integrated circuit packaging structure comprising: a substrate; a rewiring layer, the rewiring layer comprising a first surface in contact with the substrate and a second surface opposite thereto, the rewiring layer using a photosensitive dry film dielectric layer, the rewiring layer comprising at least a first rewiring layer and a second rewiring layer stacked together; a packaging layer, the packaging layer covering the chip and the rewiring layer.
  • the present invention improves the integration of the packaging structure by integrating a variety of chips with different functions into a packaging structure; uses a high-resolution dry film polymer to form a more sophisticated rewiring layer structure, thereby increasing the bandwidth of the device and reducing the delay between chips; and at the same time, compared to the prior art, high-density wiring capabilities can be achieved without forming an intermediate layer with TSV, so the required cost is lower. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明的集成电路封装结构及制备方法，包括：基板；重新布线层，所述重新布线层包括与所述基板相接触的第一面及相对的第二面，所述重新布线层采用感光干膜介质层，所述重新布线层至少包括叠置的第一重新布线层和第二重新布线层；封装层，设置在芯片层上且覆盖第一芯片和第二芯片之间的间隙；散热盖板，设置在基板上且覆盖重新布线层、芯片层和封装层。本发明通过将多种具有不同功能的芯片整合在一个封装结构中，提高封装结构的整合性；使用高分辨率干膜聚合物形成更为精细的重新布线层结构，从而实现器件的带宽增加以及减少芯片间的延迟；同时相比于现有技术无须形成带有TSV的中介层即可实现高密度布线能力，所需要的成本更低。

Description

集成电路封装结构及制备方法 技术领域
本发明涉及半导体封装领域，特别是涉及一种集成电路封装结构及制备方法。
背景技术
半导体集成电路(Integrated circuit，IC)产业历经快速发展，封装(Package)作为集成电路制造中非常关键的一环，对芯片自身性能的表现和发挥有重要的影响，它不仅起着安放、固定、密封、保护芯片和增强电热性能的作用，而且还起到集成电路芯片内键合点与外部进行电气连接的作用。
随着用户对先进功能需求的不断增长，对移动通信产品的“带宽”—高速处理信号的能力的需求也越来越高。而影响“带宽”的主要的因素在于封装系统中I/O密度的大小和重新布线层(RDL)中线宽/间距(L/S)。目前，常用的解决方法是通过封装工艺将内存芯片和处理器芯片封装到一起，从而实现器件小型化，而当下针对高密度I/O和低L/S的封装结构，一般需要使用硅通孔(TSV)等核心技术，此类核心技术成本较高，且形成高密度的I/O封装结构工艺比较困难，从而会减少带宽和提高芯片间的延迟。因此，有必要对上述封装工艺进行改进。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种集成电路封装结构及制备方法，用于解决现有封装技术导致的带宽过低、芯片间延迟高且封装成本高的问题。
为实现上述目的，本发明提供一种集成电路封装结构的制备方法，包括以下步骤：
提供临时基板，于所述临时基板上形成分离层；
采用感光干膜介质层并使用铜双镶嵌工艺，于所述分离层上形成重新布线层，所述重新布线层包括叠置的第一重新布线层和第二重新布线层，所述重新布线层包括与所述分离层相接触的第一面及相对的第二面；
于所述重新布线层的第二面上键合芯片，所述芯片与所述重新布线层电连接；
形成封装层，所述封装层覆盖所述芯片及所述重新布线层；
去除所述临时基板及所述分离层显露所述重新布线层的第一面；
提供基板，将所述基板键合于所述重新布线层的第一面上，并与所述重新布线层电连接。
可选地，形成所述第一重新布线层的步骤包括：
于所述分离层上形成第一感光干膜介质层，对所述第一感光干膜介质层光刻蚀形成第一开口；
于所述第一感光干膜介质层上形成第二感光干膜介质层，对所述第二感光干膜介质层光刻蚀形成第二开口，且所述第二开口与所述第一开口相贯通；
于所述第二感光干膜介质层以及相贯通的所述开口处形成Ti/Cu晶种层；
通过电镀工艺在所述Ti/Cu晶种层上形成电镀层，并对所述电镀层执行平坦化工艺。
可选地，所述第一重新布线层中形成有第一金属布线部，所述第二重新布线层中形成有第二金属布线部，且所述第一金属布线部与所述第二金属布线部沿竖向电连接。
可选地，还包括于所述基板上形成散热盖板或于所述基板上形成加强件的步骤。
可选地，所述芯片包括第一芯片和第二芯片，且所述第二芯片对称分布于所述第一芯片的两侧，所述第一芯片包括逻辑芯片，所述第二芯片包括存储芯片。
可选地，形成所述封装层之后还包括对所述封装层执行平坦化工艺，以显露所述芯片的步骤。
本发明还提供一种集成电路封装结构，所述集成电路封装结构包括：基板；重新布线层，所述重新布线层包括与所述基板相接触的第一面及相对的第二面，所述重新布线层采用感光干膜介质层，所述重新布线层至少包括叠置的第一重新布线层和第二重新布线层；芯片，所述芯片位于所述重新布线层的第二面，与所述重新布线层电连接；封装层，所述封装层覆盖所述芯片及所述重新布线层。
可选地，所述第一重新布线层的厚度范围为1～20μm，所述第二重新布线层的厚度范围为1～20μm。
可选地，所述第一重新布线层中形成有第一金属布线部，所述第二重新布线层中形成有第二金属布线部，且所述第一金属布线部与所述第二金属布线部沿竖向电连接。
可选地，还包括于所述基板上形成的散热盖板，所述散热盖板覆盖所述封装层且与所述基板机械连接；或于所述基板上形成的加强件，所述加强件的高度大于所述封装层的高度并与所述基板机械连接。
如上所述，本发明的集成电路封装结构及制备方法，具有以下有益效果：将多种具有不同功能的芯片整合在一个封装结构中，提高封装结构的整合性；使用高分辨率干膜聚合物形成更为精细的重新布线层结构，从而实现器件的带宽增加以及减少芯片间的延迟；同时相比于现有技术无须形成带有TSV的中介层即可实现高密度布线能力，因此所需要的成本更低。
附图说明
图1显示为本发明实施例中提供的集成电路封装结构的制备方法的流程图。
图2显示为本发明实施例中提供的临时基板和分离层后的截面示意图。
图3显示为本发明实施例中提供的光刻第一感光干膜介质层后的截面示意图。
图4显示为本发明实施例中提供的光刻第二感光干膜介质层后的截面示意图。
图5显示为本发明实施例中提供的形成电镀层后的截面示意图。
图6显示为本发明实施例中提供的对电镀层执行平坦化工艺后的截面示意图。
图7显示为本发明实施例中提供的形成第二重新布线层后的截面示意图。
图8显示为本发明实施例中提供的形成芯片后的截面示意图。
图9显示为本发明实施例中提供的形成封装层后的截面示意图。
图10显示为本发明实施例中提供的对封装层减薄后的截面示意图。
图11显示为本发明实施例中提供的去除临时基板和分离层后的截面示意图。
图12显示为本发明实施例中提供的基板键合后的截面示意图。
图13显示为本发明实施例中提供的形成散热盖板后的截面示意图。
图14显示为本发明实施例中提供的另一种封装结构的结构示意图。
元件标号说明
101                    临时基板
102                    分离层
103                    重新布线层
1031                   第一面
1032                   第二面
104                    第一重新布线层
1041                   第一感光干膜介质层
1042                   第二感光干膜介质层
1043                   第一开口
1044                   第二开口
1045                   第一金属布线部
1046                   第二金属布线部
105                    第二重新布线层
106                    芯片
1061                   第一芯片
1062                   第二芯片
107                    封装层
108                 基板
109                    散热盖板
110                    加强件
S1～S6                 步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
需要理解的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对上述零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本发明保护范围的限制。
请参阅图1至图14。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
请参阅图1至图14，本发明提供了一种集成电路封装结构的制备方法，包括以下步骤：
S1：提供临时基板101，于所述临时基板101上形成分离层102；
S2：采用感光干膜介质层并使用铜双镶嵌工艺，于所述分离层102上形成重新布线层103，所述重新布线层103包括叠置的第一重新布线层104和第二重新布线层105，所述重新布线层103包括与所述分离层102相接触的第一面1031及相对的第二面1032；
S3：于所述重新布线层的第二面1032上键合芯片106，所述芯片106与所述重新布线层103电连接；
S4：形成封装层107，所述封装层107覆盖所述芯片106及所述重新布线层103；
S5：去除所述临时基板101及所述分离层102显露所述重新布线层的第一面1031；
S6：提供基板108，将所述基板108键合于所述重新布线层的第一面1031上，并与所述重新布线层103电连接。
以下结合附图对有关所述集成电路封装结构的制备方法做进一步的介绍，具体如下：
在步骤S1中，请参阅图1和图2，提供临时基板101，于所述临时基板101上形成分离层102。
可选地，所述临时基板101包括氧化硅基板、玻璃基板、陶瓷基板、聚合物基板中的一种，其形状可以为圆形、方形或其它任意所需形状。此外，图2中还在所述临时基板101上形成分离层102，所述分离层102包括LTHC光热转换材料层，其具有能够粘附其他部件并在激光照射后发生变性剥离的特性。
具体的，在本实施例中，所述临时基板101选用玻璃衬底，所述玻璃衬底成本较低，容易在其表面形成分离层，并降低后续的分离工艺的难度。
在步骤S2中，请参阅图1、图3至图7，采用感光干膜介质层并使用铜双镶嵌工艺，于所述分离层102上形成重新布线层103，所述重新布线层103包括叠置的第一重新布线层104和第二重新布线层105，所述重新布线层103包括与所述分离层102相接触的第一面1031及相对的第二面1032。
具体的，如图3所示，于所述分离层102上形成所述第一感光干膜介质层1041，以所述第一感光干膜介质层1041为掩膜，对所述临时基底101进行刻蚀形成所述第一开口1043；如图4所示，于所述第一感光干膜介质层1041上形成所述第二感光干膜介质层1042，以所述第二感光干膜介质层1042为掩膜，对所述第二感光干膜介质层1042进行刻蚀形成与所述第一开口1043相贯通的第二开口1044；于所述临时基底101上沉积Ti/Cu晶种层(未图示)，其中，所述Ti/Cu晶种层须完全覆盖所述第二感光干膜介质层1042、所述第一开口1043和所述第二开口1044的表面；然后通过电镀工艺于所述Ti/Cu晶种层上过度填充所述第一开口1043和所述第二开口1044来形成如图5所示的所述电镀层；如图6所示，一旦已经过度覆盖了所述第二感光干膜介质层1042、所述第一开口1043和所述第二开口1044，可通过平坦化工艺以去除多余的电镀层。
可选地，所述电镀层的材质包括铜、铝、镍、金、银及钛中的一种。可通过诸如电镀的沉积工艺形成所述电镀层。
可选地，平坦化工艺可包含磨削工艺、化学机械研磨工艺、干式研磨工艺、蚀刻工艺、切割工艺中的一个或多个工艺的组合，在平坦化工艺之后，所述第一开口1043和所述第二开 口1044的表面与所述电镀层的表面基本上齐平。
可选地，如图7所示，于所述第一重新布线层104上形成第二重新布线层105，所述第一重新布线层104与所述第二重新布线层105电连接，形成所述第二重新布线层105的步骤与形成所述第一重新布线层104的步骤相同，此处不再赘述。
具体的，所述第一重新布线层104中形成有第一金属布线部1045，所述第二重新布线层105中形成有第二金属布线部1046，且所述第一金属布线部1045与所述第二金属布线部1046沿竖向电连接。
在步骤S3中，请参阅图1和图8，于所述重新布线层的第二面1032上键合芯片106，所述芯片106与所述重新布线层103电连接。
可选地，所述芯片106包括第一芯片1061与第二芯片1062，且所述第二芯片1062对称分布于所述第一芯片1061的两侧，所述第一芯片1061包括逻辑芯片，所述第二芯片1062包括存储芯片。
可选地，所述第一芯片1061和所述第二芯片1062可以是现有的任意适用于封装结构的半导体芯片，例如，可以是系统芯片、逻辑芯片、记忆芯片，也可以是存储器芯片，如HBM等，具体根据实际需要进行设置，此处不做特别限制。
可选地，所述第二芯片1062与所述第一芯片1061可以是不同类型的芯片且所述第二芯片1062优选对称分布于所述第一芯片1061两侧并与所述第一重新布线层103电连接。
具体的，在本实施例中，所述第一芯片1061为逻辑(SOC)芯片，所述第二芯片1062为存储(HBM)芯片，且所述第二芯片1062对称分布在所述第一芯片1061的两侧。当然，在其他示例中，所述第一芯片1061和所述第二芯片1062也可以为其它形式的芯片，本实施例中并不严格限定。
在步骤S4中，请参阅图1和图9，形成封装层107，所述封装层107覆盖所述芯片106及所述重新布线层103
可选地，如图9所示，形成所述封装层107的工艺包括压缩成型工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺及旋涂工艺中的一种；所述封装层107包括环氧树脂层、聚酰亚胺层及硅胶层中的一种。
可选地，如图10所示，形成所述封装层107之后还包括对所述封装层107执行平坦化工艺，以显露所述芯片106的步骤。
具体的，平坦化工艺可以包括磨削工艺、CMP工艺、干式研磨工艺、蚀刻工艺、切割工艺中的一个或组合工艺。在平坦化工艺之后，所述封装层107的顶表面与所述第一芯片1061 以及所述第二芯片1062的顶表面基本上齐平。
在步骤S5中，请参阅图1和图11，去除所述临时基板101及所述分离层102显露所述重新布线层的第一面1031。
可选地，还包括于所述重新布线层的第一面1031上形成阵列分布的金属凸块(未图示)的步骤，所述金属凸块与所述重新布线层103电连接。
可选地，所述金属凸块包括金锡焊球、银锡焊球、铜锡焊球中的一种。
具体的，在本实施例中，所述金属凸块为铜锡焊球，其制作步骤包括：首先形成铜锡层，然后采用高温回流工艺使所述铜锡层回流成球状，降温后形成铜锡焊球；或采用植球工艺形成铜锡焊球。
在步骤S6中，请参阅图1和图12，提供基板108，将所述基板108键合于所述重新布线层的第一面1031上，并与所述重新布线层103电连接。
可选地，所述基板108包括氧化硅基板、玻璃基板、陶瓷基板、聚合物基板中的一种，所述基板110与所述重新布线层103通过所述金属凸块实现电连接。
进一步的，请参阅图13和图14，还可于所述基板108上形成散热盖板109或于所述基板108上形成加强件110的步骤。
可选地，如图13所示，于所述基板108上形成散热盖板109，所述散热盖板109覆盖所述封装层107、所述芯片106和所述重新布线层103。
可选地，所述散热盖板109的材质包括金属或陶瓷的一种，所述散热盖板109与所述基板108机械连接。
具体的，在所述基板110的两端分别形成粘接件(未图示)，所述散热盖板109与所述基板108之间通过所述粘接件实现连接。
如图14，在另一实施例中，所述基板110上还可形成加强件110，所述加强件110与所述基板108机械连接且所述加强件110的高度大于所述封装层107的高度。
实施例二
如图13和图14所示，本实施例提供了一种集成电路封装结构，包括：基板110；重新布线层103，所述重新布线层103包括与所述基板108相接触的第一面1031及相对的第二面1032，所述重新布线层103采用感光干膜介质层，所述重新布线层103至少包括叠置的第一重新布线层104和第二重新布线层105；芯片106，所述芯片106位于所述重新布线层的第二面1032，与所述重新布线层103电连接；封装层107，所述封装层107覆盖所述芯片106及所述重新布线层103。
可选地，如图5所示，所述第一重新布线层104的厚度范围为1～20μm，例如，可以为1μm、5μm、10μm或者20μm。
可选地，如图6所示，所述第二重新布线层105的厚度范围为1～20μm，例如，可以为1μm、5μm、10μm或者20μm。
可选地，如图6和图7所示，所述第一重新布线层104中形成有第一金属布线部1045，所述第二重新布线层105中形成有第二金属布线部1046，且所述第一金属布线部1045与所述第二金属布线部1046沿竖向电连接。
可选地，如图13和图14所示，还包括于所述基板108上形成的散热盖板109，所述散热盖板109覆盖所述封装层107且与所述基板108机械连接；或于所述基板108上形成的加强件110，所述加强件110的高度大于所述封装层107的高度并与所述基板108机械连接。
综上所述，本发明提供了一种集成电路封装结构及制备方法，所述集成电路封装结构包括：基板；重新布线层，所述重新布线层包括与所述基板相接触的第一面及相对的第二面，所述重新布线层采用感光干膜介质层，所述重新布线层至少包括叠置的第一重新布线层和第二重新布线层；封装层，所述封装层覆盖所述芯片及所述重新布线层。本发明通过将多种具有不同功能的芯片整合在一个封装结构中，提高封装结构的整合性；使用高分辨率干膜聚合物形成更为精细的重新布线层结构，从而实现器件的带宽增加以及减少芯片间的延迟；同时相比于现有技术无须形成带有TSV的中介层即可实现高密度布线能力，因此所需要的成本更低。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种集成电路封装结构的制备方法，其特征在于，所述制备方法包括以下步骤：
    提供临时基板，于所述临时基板上形成分离层；
    采用感光干膜介质层并使用铜双镶嵌工艺，于所述分离层上形成重新布线层，所述重新布线层包括叠置的第一重新布线层和第二重新布线层，所述重新布线层包括与所述分离层相接触的第一面及相对的第二面；
    于所述重新布线层的第二面上键合芯片，所述芯片与所述重新布线层电连接；
    形成封装层，所述封装层覆盖所述芯片及所述重新布线层；
    去除所述临时基板及所述分离层显露所述重新布线层的第一面；
    提供基板，将所述基板键合于所述重新布线层的第一面上，并与所述重新布线层电连接。
  2. 根据权利要求1所述的制备方法，其特征在于：形成所述第一重新布线层的步骤包括：
    于所述分离层上形成第一感光干膜介质层，对所述第一感光干膜介质层光刻蚀形成第一开口；
    于所述第一感光干膜介质层上形成第二感光干膜介质层，对所述第二感光干膜介质层光刻蚀形成第二开口，且所述第二开口与所述第一开口相贯通；
    于所述第二感光干膜介质层以及相贯通的所述开口处形成Ti/Cu晶种层；
    通过电镀工艺在所述Ti/Cu晶种层上形成电镀层，并对所述电镀层执行平坦化工艺。
  3. 根据权利要求1所述的制备方法，其特征在于：所述第一重新布线层中形成有第一金属布线部，所述第二重新布线层中形成有第二金属布线部，且所述第一金属布线部与所述第二金属布线部沿竖向电连接。
  4. 根据权利要求1所述的制备方法，其特征在于：还包括于所述基板上形成散热盖板或于所述基板上形成加强件的步骤。
  5. 根据权利要求1所述的制备方法，其特征在于：所述芯片包括第一芯片和第二芯片，且所述第二芯片对称分布于所述第一芯片的两侧，所述第一芯片包括逻辑芯片，所述第二芯片包括存储芯片。
  6. 根据权利要求1所述的制备方法，其特征在于：形成所述封装层之后还包括对所述封装层 执行平坦化工艺，以显露所述芯片的步骤。
  7. 一种集成电路封装结构，其特征在于，所述集成电路封装结构包括：
    基板；
    重新布线层，所述重新布线层包括与所述基板相接触的第一面及相对的第二面，所述重新布线层采用感光干膜介质层，所述重新布线层至少包括叠置的第一重新布线层和第二重新布线层；
    芯片，所述芯片位于所述重新布线层的第二面，与所述重新布线层电连接；
    封装层，所述封装层覆盖所述芯片及所述重新布线层。
  8. 根据权利要求7所述的集成电路封装结构，其特征在于：所述第一重新布线层的厚度范围为1～20μm，所述第二重新布线层的厚度范围为1～20μm。
  9. 根据权利要求7所述的集成电路封装结构，其特征在于：所述第一重新布线层中形成有第一金属布线部，所述第二重新布线层中形成有第二金属布线部，且所述第一金属布线部与所述第二金属布线部沿竖向电连接。
  10. 根据权利要求7所述的集成电路封装结构，其特征在于：还包括于所述基板上形成的散热盖板，所述散热盖板覆盖所述封装层且与所述基板机械连接；或于所述基板上形成的加强件，所述加强件的高度大于所述封装层的高度并与所述基板机械连接。
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