TWI806163B - 封裝結構、半導體裝置、及封裝結構的製造方法 - Google Patents

封裝結構、半導體裝置、及封裝結構的製造方法 Download PDF

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TWI806163B
TWI806163B TW110135010A TW110135010A TWI806163B TW I806163 B TWI806163 B TW I806163B TW 110135010 A TW110135010 A TW 110135010A TW 110135010 A TW110135010 A TW 110135010A TW I806163 B TWI806163 B TW I806163B
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layer
conductive
package
metal layer
die
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TW110135010A
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TW202220062A (zh
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張豐願
魯立忠
志純 李
黃博祥
新宇 鮑
山姆 瓦澤里
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台灣積體電路製造股份有限公司
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Abstract

一種封裝結構，包括焊料特徵、位於焊料特徵上的第一重分佈層結構及安裝在第一重分佈層結構上且電耦合第一重分佈層結構的晶粒。第一重分佈層結構包括填充有導熱介電材料的一或多個介電層。

Description

封裝結構、半導體裝置、及封裝結構的製造方法
本揭示內容的一些實施例是關於封裝結構、半導體裝置、及封裝結構的製造方法。
3D積體電路(3D integrated circuit，3D IC)包括半導體裝置，半導體裝置具有垂直堆疊且連接以形成積體電路的兩層或更多層主動電子組件。散熱為3D IC的一大挑戰，因為晶片密度增加的3D IC系統會表現出高熱密度及較差的散熱性能。
在3D IC的內部晶粒中產生的熱量可能會積累於底部堆疊晶粒的內部區域中，且導致局部溫度峰值，有時稱為熱點。由裝置產生的熱量導致的熱點可能會對堆疊晶粒中其他重疊裝置的電氣性能產生負面影響，且通常會導致3D IC封裝的電遷移及可靠性問題。具有解決上述不足 及問題的需要。
本揭示內容的一些實施方式提供一種封裝結構，包含：焊料特徵；第一重分佈層結構，位於焊料特徵上，第一重分佈層結構包含填充有導熱介電材料的一或多個介電層；及晶粒，安裝在第一重分佈層結構上且電耦合第一重分佈層結構。
本揭示內容的一些實施方式提供一種半導體裝置，包含：一或多個電連接器；一或多個晶粒的堆疊；及一或多個重分佈層結構，將一或多個晶粒與一或多個電連接器電耦合，一或多個重分佈層結構中的至少一者包含鄰接一或多個電連接器的導熱水平層。
本揭示內容的一些實施方式提供一種製造封裝結構的方法，包含：將第一晶粒附接至封裝中；施加第一模製材料圍繞第一晶粒；在第一模製材料下方形成一或多個第一導電層且一或多個第一導電層電連接第一晶粒；及形成一或多個第一介電層，一或多個第一介電層包含氮化鋁、氮化硼或其組合，一或多個第一介電層中的任一者設置在相應的第一導電層上。
100:封裝堆疊裝置
110:頂部封裝
112、114、150、160:裝置晶粒
116、126:模製材料
118:頂部封裝基板
120:底部封裝
122:前側重分佈層結構
124:封裝通孔
128:背側RDL結構
130、170:焊料特徵
140:印刷電路板
180:內部區域
190:積體被動裝置
200:封裝
201:載體
202:黏著層
203:聚合物基層
204:背側重分佈層
205:光阻劑
206、210:開口
207:種晶層
208:導電材料
209:導電通孔
211:裝置晶粒
212:模製化合物
213、214、215、216:介電層
217:凸塊下冶金
218A、218B、218C:外部連接器
1282:重分佈層焊墊
Mx、My、Mz:導電層
Vx、Vy、Vz:通孔
結合附圖，根據以下詳細描述可以最好地理解本揭示內容的各態樣。注意，根據行業中的標準實務，各種特 徵未按比例繪製。實際上，為了討論清楚起見，各種特徵的尺寸可任意增加或減小。
第1圖為根據本揭示內容的例示性實施例的封裝堆疊(package-on-packag，PoP)裝置的橫剖面圖。
第2圖至第16圖為根據本揭示內容的例示性實施例的整合式扇出(Integrated Fan-Out，InFO)封裝在IC後段製程(back-end-of-line，BEOL)的不同階段的橫剖面圖。
第17圖為根據本揭示內容的例示性實施例的整合式扇出(InFO)封裝的橫剖面圖。
以下揭示內容提供了用於實現提供之標的的不同特徵的許多不同的實施例或實例。以下描述組件及佈置的特定簡化實例用以描述本揭示內容。當然，此些僅為實例，並不旨在進行限制。例如，在下面的描述中在第二特徵上方或之上形成第一特徵可包括其中第一及第二特徵直接接觸形成的實施例，且亦可包括其中在第一與第二特徵之間形成附加特徵的實施例，以使得第一及第二特徵可以不直接接觸。此外，本揭示內容可以在各個實例中重複元件符號或字母。此重複係出於簡單及清楚的目的，其本身並不指定所討論之各種實施例或組態之間的關係。
在本說明書中使用的術語通常具有本領域及在使用每一術語的特定上下文中的普通意義。在本說明書中使 用示例，包括本文討論的任何術語的示例，僅為說明性的，絕不限制本揭示內容或任何示例性術語的範圍及意義。同樣，本揭示內容不限於本說明書中給定的各種實施例。
儘管本文中可使用術語「第一」、「第二」等來描述各種元件，但這些元件不應受這些術語的限制。這些術語用於區分一個元件與另一元件。例如，在不脫離實施例範疇的情況下，第一元件可稱為第二元件，且類似地，第二元件可稱為第一元件。如本文中所使用，術語「及/或」包括一或多個相關聯的所列項目的任何及所有組合。
此外，為了便於描述，本文中可以使用諸如「在...下方」、「在...下」、「下方」、「在...上方」、「上方」之類的空間相對術語，來描述如圖中所示的一個元件或特徵與另一元件或特徵的關係。除了在附圖中示出的方位之外，空間相對術語意在涵蓋裝置在使用或操作中的不同方位。設備可以其他方式定向(旋轉90度或以其他方位)，且在此使用的空間相對描述語亦可被相應地解釋。
在本文件中，術語「耦合」亦可稱為「電耦合」，且術語「連接」可稱為「電連接」。「耦合」及「連接」亦可用於表示兩個或更多個元件相互協作或交互。
使用特定上下文中的實施例描述本揭示內容的各種實施例，亦即，三維(three-dimensional，3D)整合式扇出(integrated fan-out，InFO)封裝堆疊(package-on-package，PoP)裝置。然而，本揭示內容中的概念亦可應用於其他半導體結構或電路。
第1圖為根據本揭示內容的一些實施例的封裝堆疊(package-on-package，PoP)裝置100的橫剖面圖。如第1圖所示，PoP裝置100包括頂部封裝110，頂部封裝110使用形成在整合式扇出封裝堆疊(Integrated Fan Out Package on Package，InFO PoP)裝置中的一或多個重分佈層電耦合底部封裝120，將在下文中更詳細地描述。在一些實施方式中，頂部封裝110及底部封裝120可包括為了簡潔在本文中省略的各種其他組件、層、電路及結構。
如第1圖所示，頂部封裝110安裝在底部封裝120上方。頂部封裝110可包括一或多個裝置晶粒112、114。在一些實施例中，裝置晶粒112、114為垂直分立的記憶體組件。例如，裝置晶粒112、114可為記憶體組件，諸如動態隨機存取記憶體(dynamic random-access memory，DRAM)或其他合適類型的記憶體裝置。儘管第1圖中描繪了兩個裝置晶粒112、114，但本揭示內容不限於此。在各種實施例中，頂部封裝110可包括任何數量的裝置晶粒112、114。
在一些實施例中，頂部封裝110中的裝置晶粒112、114經由佈線接合以及頂部封裝基板118中的通孔及接觸墊電耦合底部封裝120。頂部封裝110可包括模製材料116或另一種合適的封裝膠以覆蓋裝置晶粒112、114且保護佈線接合連接。
在底部封裝120的前側，底部封裝120包括底部 封裝基板。在一些實施例中，底部封裝基板為聚苯并噁唑(polybenzoxazole，PBO)或其他合適的基板材料。如第1圖所示，一或多個焊料特徵130安裝至底部封裝基板作為電連接器。在一些實施例中，焊料特徵130由來自球柵陣列(ball grid array，BGA)的焊球形成。如圖所示，焊料特徵130允許將底部封裝120安裝且電耦合例如底層印刷電路板(printed circuit board，PCB)140或其他組件。在一些實施例中，一或多個積體被動裝置(integrated passive device，IPD)190可以安裝在底部封裝120下方且位於底部封裝120與底層印刷電路板140之間。
如第1圖所示，底部封裝120包括底部封裝基板中的前側重分佈層(redistribution layer，RDL)結構122。前側RDL結構122將底部封裝120中的裝置晶粒150電耦合例如焊料特徵130及印刷電路板140。在一些實施例中，底部封裝120中的裝置晶粒150及160為邏輯裝置或邏輯組件，例如邏輯積體電路、類比電路等。裝置晶粒150及160可以由模製材料126或任何其他合適的封裝膠來封裝以覆蓋裝置晶粒150及160。在一些實施例中，如第1圖所示，當兩個裝置晶粒150及160垂直堆疊且經由導電特徵彼此連接時，底部封裝120可包括由模製材料126整合及封裝的任意數量的裝置晶粒。
在一些實施例中，裝置晶粒150及160可以使用晶粒附著膜(die attach film，DAF)安裝在鈍化層下方 或鈍化層上。在一些實施例中，鈍化層包括聚苯并噁唑(PBO)、味之素堆積膜(Ajinomoto build-up film，ABF)或其他合適的材料。包括PBO、ABF或其他合適材料的緩衝層可設置在鈍化層上方。視情況，層壓帶可以設置在緩衝層上。層壓帶可包括焊接剝離(solder release，SR)膜、ABF、包括熱固性聚合物或其他合適材料的背側層壓塗層帶(LC帶)。在一些實施例中，底部填充材料可以用於封裝頂部封裝110及底部封裝120的部分。底部填充材料可以自印刷電路板140的頂表面沿著底部封裝120的側面且沿著頂部封裝110的側面的一部分延伸。在一些實施例中，底部填充材料可以設置在頂部封裝基板118與層壓帶或緩衝層之間。
仍參看第1圖，底部封裝120亦包括貫穿模製材料126且在底部封裝120的前側與背側之間延伸的封裝通孔(through package via，TPV)124。在本文中亦可稱為InFO通孔(through InFO via，TIV)或金屬通孔的封裝通孔124嵌入且穿過模製材料126。在一些實施例中，封裝通孔124包括銅、鎳(Ni)、銅合金(銅/鈦)、焊接、包括錫-銀(SnAg)、錫-鉍(SnBi)、錫-銅(SnCu)、錫-銀-銅(SnAgCu)、錫-銀-銅-鎳(SnAgCuNi)或其組合，或其他合適金屬中的一或多者。在一些其他實施例中，儘管第1圖中示出了四個封裝通孔124，但更多或更少的封裝通孔124可包括於底部封裝120中。
在一些實施例中，底部封裝120亦包括背側RDL 結構128。在一些實施方式中，背側RDL結構128的一部分可以在裝置晶粒160的頂表面上方延伸。因此，裝置晶粒160電耦合例如頂部封裝110中的裝置晶粒112及114以及封裝通孔124。此外，背側RDL結構128的另一部分可以在封裝通孔124上方延伸。具體地，來自背側RDL結構128的重分佈層焊墊1282設置在封裝通孔124的上部且以蓋帽或以其他方式覆蓋第1圖中的封裝通孔124的頂部。因此，背側RDL結構128可以經由封裝通孔124電耦合裝置晶粒160及前側RDL結構122。在一些實施例中，重分佈層焊墊1282及封裝通孔124由相同的材料(例如，銅)形成。因此，重分佈層焊墊1282及封裝通孔124可以表現為單一整體結構。
焊料特徵170形成或安裝在重分佈層焊墊1282及封裝通孔124上，且與此些重分佈層焊墊1282及封裝通孔124電耦合。焊料特徵170將頂部封裝110與底部封裝120電耦合。在一些實施例中，焊料特徵170由焊膏、有機可焊性保護層(organic solderability preservative，OSP)或其他合適的導電材料或其任何組合形成。在一些實施例中，金屬間化合物(intermetallic compound，IMC)設置在焊料特徵170與蓋帽於封裝通孔124的底層重分佈層焊墊1282之間。金屬間化合物為用於電耦合焊料特徵170及封裝通孔124的回焊製程的產物。
在一些其他實施例中，三維積體晶片可以不同方式 實現，如第1圖中的封裝堆疊裝置100僅為實例，並不意欲在限制本揭示內容。例如，一些半導體裝置可以實現積體晶片3D系統(「3D System on an Integrated Chip，3D SoIC」)結構，結構為一種非單片式垂直結構，非單片式垂直結構包括兩至八個相互堆疊的具有不同功能的二維(two-dimensional，2D)覆晶，例如邏輯晶片、記憶體晶片、射頻(radio frequency，RF)晶片等。作為實例而非限制，邏輯晶片可包括中央處理單元(central process unit，CPU)，且記憶體晶片可包括靜態存取記憶體(static random-access memory，SRAM)陣列、動態隨機存取記憶體(dynamic random-access memory，DRAM)陣列、磁性隨機存取記憶體(magnetic random-access memory，MRAM)陣列或其他記憶體陣列。在3D SoIC結構中，2D晶片可以經由微凸塊、焊墊、矽通孔(through silicon vias，TSV)或其他互連結構互連。
IC封裝中較差的散熱性能可能導致電遷移及可靠性問題且導致較差的IC性能。不同類型的IC晶片可具有不同的耐熱性。例如，與邏輯晶片相比，諸如SRAM陣列之類的記憶體晶片可具有較低的耐熱性。在一些高級節點中，可能需要降低晶片速度(例如，降低約5%至10%)以滿足溫度要求。
由於晶粒堆疊，3D IC結構的功率密度可以大於高級節點中的單一晶粒晶片。這些3D IC結構增加了晶片 密度及更高的單位面積功率密度/熱密度，且給散熱帶來了更大的挑戰。例如，電遷移會增加互連及TSV的電阻，降低晶片的性能，且降低3D IC結構的使用壽命。由於3D IC結構中所包括的材料可包括具有不同熱膨脹係數(coefficient of thermal expansion，CTE)的材料，因此可能會出現可靠性問題。具有不同CTE的材料會導致積體電路(integrated circui，IC)晶片之間產生熱機械應力。
如第1圖所示，內部晶粒中產生的熱量可能積累底部堆疊裝置晶粒150、160的內部區域180中且造成熱點。在一些實施例中，局部熱點可以出現在任何晶片層上且不限於具有邏輯晶片的晶片層。為了提供傳遞裝置晶粒150、160產生的熱量且散發熱量的散熱路徑，在本揭示內容的一些實施例中，前側RDL結構122可包括填充有導電介電材料的一或多個介電層，例如導熱度實質上等於或大於約2W/(m．K)的材料。
藉由在前側RDL結構122中使用導熱但電絕緣的材料形成介電層，可以有效地傳遞及移除前側RDL結構122中的熱量。作為實例而非限制，用於介電層的導熱介電材料可包括氮化鋁(aluminum nitride，AlN)、諸如六方氮化硼(hexagonal boron nitride，h-BN)的氮化硼(BN)或其任何組合中的一或多者。在某些溫度條件下(例如，在300K下)，氮化鋁提供高達約285至321W/(m．K)的高導熱度，且為具有約8.5的靜態介電常數的 電絕緣體。六方氮化硼提供高達約400W/(m．K)的面內及約6W/(m．K)面外的高導熱度，且為一種電絕緣體，面內靜態介電常數為約6.9，且面外靜態介電常數為約3.5。
在本揭示內容的一些實施例中，前側RDL結構122可包括一或多個導電層，且導電層中的至少一者具有實質上大於4微米的厚度。在一些實施例中，一個導電層的厚度可在約4微米至約10微米內。前側RDL結構122中的厚導電層，例如金屬層，亦可改善前側RDL結構122的導熱度及底部封裝120中不同層之間的散熱。因此，與電連接器相鄰的一或多個導熱水平層可以形成在底部封裝120中以將熱量自局部熱點傳遞出去。
為了說明，底部封裝120的製造方法將參考第2圖至第16圖進行描述。第2圖至第16圖為根據本揭示內容的一些實施例的整合式扇出(Integrated Fan-Out，InFO)封裝200在IC後段製程(back-end-of-line，BEOL)的不同階段的的橫剖面圖。
儘管在本文中將製程圖式及描述為一系列動作或事件，但應理解，這些動作或事件的圖式順序不應解釋為限制意義。例如，一些步驟可以不同的順序及/或與除了在本文中圖式及/或描述的那些步驟或事件之外的其他步驟或事件同時發生。此外，並非所有示出的步驟均可能需要實施本文描述的一或多個態樣或實施例。另外，本文描述的一或多個步驟可以在一或多個單獨的步驟及/或階段中 進行。
在第2圖中，提供載體201、黏著層202及聚合物基層203。在一些實施例中，載體201包括玻璃、陶瓷或其他合適的材料，以在裝置封裝中的各種特徵的形成期間提供結構支撐。在一些實施例中，包括例如膠層、光熱轉換(light-to-heat conversion，LTHC)塗層、紫外線(ultraviolet，UV)膜等的黏著層202設置在載體201之上。聚合物基層203經由黏著層202塗覆在載體201上。在一些實施例中，聚合物基層203由聚苯并噁唑(PolyBenzOxazole，PBO)、味之素堆積膜(Ajinomoto Buildup Film，ABF)、聚醯亞胺、苯并環丁烯(BenzoCycloButene，BCB)、阻焊(Solder Resist，SR)膜、裸晶吸附膜(Die-Attach Film，DAF)等形成，但本揭示內容不限於此。
現參看第3圖，隨後，形成背側重分佈層(backside redistribution layer，RDL)204。在一些實施例中，背側RDL 204包括一或多個重分佈線，一或多個重分佈線為導電特徵，包括例如形成在一或多個介電層之間的導電線及/或通孔。在一些實施例中，介電層由氮化鋁、氮化硼或其組合形成。在一些實施例中，介電層由其他合適材料(包括聚醯亞胺(PI)、PBO、BCB、環氧樹脂、矽酮、丙烯酸酯、奈米填充酚醛樹脂、矽氧烷、氟化聚合物、聚降冰片烯等)使用任何合適方法(包括例如旋塗技術、濺射等)形成。
在一些實施例中，導電特徵/層形成在介電層之間。這些導電特徵的形成包括以下步驟：使用例如微影術及蝕刻製程的組合來圖案化介電層；及藉由例如沉積種晶層及使用罩幕層在圖案化的介電層中形成導電特徵以限定導電特徵的形狀。導電特徵經設計以形成用於隨後附接的裝置晶粒的功能電路及輸入/輸出特徵。
現參看第4圖，在背側RDL 204及聚合物基層203上方形成圖案化光阻劑205。例如，在一些實施例中，將光阻劑205沉積為背側RDL 204上方的毯覆層。接著，使用光罩(未圖式)曝露部分光阻劑205。然後根據是否使用負性光阻劑或正性光阻劑來移除光阻劑205的曝露或未曝露部分。所得圖案化光阻劑205包括設置在載體201的外圍區域處的開口206。在一些實施例中，開口206進一步曝露背側RDL 204中的導電特徵。
現參看第5圖，種晶層207沉積在圖案化光阻劑205上。接著，參看第6圖，開口206填充有包括例如銅、銀、金等的導電材料208以形成導電通孔。在一些實施例中，在電鍍製程期間，用導電材料208電鍍開口206，包括例如電化學電鍍、無電式電鍍等。在一些實施例中，導電材料208過填充開口206。
現參看第7圖，執行研磨製程及化學機械研磨(chemical mechanical polishing，CMP)製程以移除光阻劑205上方的多餘部分的導電材料208。
現參看第8圖，移除光阻劑205。在一些實施例 中，電漿灰化或濕剝離製程用於移除光阻劑205。在一些實施例中，電漿灰化製程之後為在硫酸(H2SO4)溶液中的濕浸以清潔封裝200且移除剩餘的光阻劑材料。
因此，導電通孔209形成在背側RDL 204之上。或者，在一些實施例中，導電通孔209替換為導電柱或導電線，包括例如銅、金或銀線。在一些實施例中，導電通孔209藉由開口210彼此間隔開，且相鄰導電通孔209之間的至少一個開口210足夠大以在其中設置一或多個半導體裝置晶粒。
現參看第9圖，裝置晶粒211安裝且附接至封裝200。在一些實施例中，黏著層用於將裝置晶粒211固定至背側RDL 204。儘管在第9圖中示出了一個裝置晶粒211，在一些其他實施例中，兩個或更多個裝置晶粒211，例如驅動器晶粒及接收器晶粒，可以安裝且附接至封裝200。在一些實施例中，一或多個裝置晶粒(例如，第1圖的裝置晶粒150及160)的堆疊可以安裝且附接至封裝200。
現參看第10圖，在將裝置晶粒211安裝至背側RDL 204及/或開口210中的聚合物基層203之後，在封裝200中形成模製化合物212。分配模製化合物212以填充裝置晶粒211與導電通孔209之間的間隙、相鄰導電通孔209之間的間隙及/或裝置晶粒211中任意兩者之間的間隙。在一些實施例中，模製化合物212包括任何合適材料，包括例如環氧樹脂、模製底部填料等。在一些實 施例中，壓縮模製、傳遞模製及液體封裝膠模製為形成模製化合物212的合適方法，但本揭示內容不限於此。例如，模製化合物212可以液體形式分配在裝置晶粒211與導電通孔209之間。隨後，可以執行固化製程以固化模製化合物212。在一些實施例中，模製化合物212的填充可以溢出裝置晶粒211及導電通孔209，使得模製化合物212覆蓋裝置晶粒211的頂表面及導電通孔209。
現參看第11圖，執行研磨製程及化學機械研磨(chemical mechanical polishing，CMP)製程以移除模製化合物212的多餘部分，且回研磨模製化合物212以減小模製化合物212的整體厚度，且因此曝露導電通孔209。由於所得結構包括延伸穿過模製化合物212的導電通孔209，故導電通孔209亦稱為模製通孔、中間通孔(through inter via，TIV)等。導電通孔209提供封裝200中背側RDL 204的電連接。在一些實施例中，導電通孔209可以與3D矽中介層一起使用。
現參看第12圖，在模製化合物212上形成具有開口的圖案化介電層213。在一些實施例中，介電層213包括氮化鋁、氮化硼或其組合。在一些實施例中，介電層213包括PI、PBO、BCB、環氧樹脂、矽樹脂、丙烯酸酯、奈米填充酚醛樹脂、矽氧烷、氟化聚合物、聚降冰片烯等。在一些實施例中，介電層213選擇性地曝露於蝕刻劑，包括例如CF4、CHF3、C4F8、HF等，蝕刻劑用以蝕刻介電層213以形成開口。如說明性所示，開口曝露導 電柱及導電通孔209。在一些實施例中，開口包括一或多個通孔及上覆的金屬線溝槽。通孔自介電層213的底表面垂直延伸至金屬溝槽的底表面，此些金屬溝槽延伸至介電層213的頂表面。
現參看第13圖，在一些實施例中，開口填充有導電材料以形成具有一或多個導電特徵(例如，重分佈線)的導電層Mx。為了說明，在開口中形成種晶層(未圖式)，且使用例如電化學電鍍製程、無電式電鍍製程等在開口中電鍍導電材料。如說明性所示，在介電層213中產生的通孔Vx電連接導電柱或導電通孔209。在一些實施例中，如上所述，包括由沉積製程、後續電鍍製程及CMP製程沉積例如銅或鋁的導電材料，且因此為了簡潔起見省略了詳細描述。
現參看第14圖，在一些實施例中，在介電層213上方形成具有導電特徵的介電層214。特別地，在介電層214與介電層215之間形成具有一或多個導電特徵(例如，重分佈線)及通孔Vy的導電層My。在一些實施例中，重分佈線包括設置在各種介電層之間的導電特徵。在一些實施例中，介電層215經圖案化以形成開口，且在開口內形成金屬材料以形成重分佈線。
現參看第15圖，在一些實施例中，在介電層215上方形成具有導電特徵的另一附加介電層216。特別地，在介電層215與介電層216之間形成具有一或多個導電特徵(例如，重分佈線)及通孔Vz的導電層Mz。在一些實施 例中，導電層Mx、My或Mz中的一或多者內的導電特徵的寬度可以等於或實質上大於0.8微米。在一些實施例中，在導電層Mx、My或Mz中的一或多者內的相鄰導電部件的間距可以等於或實質上大於0.8微米。在一些實施例中，通孔Vx、Vy或Vz的高度可為約1.5微米。
如說明性所示，在一些實施例中，裝置晶粒211電連接重分佈線的導電特徵。在一些實施例中，形成於介電層之間的重分佈線在組成及形成製程上與背側RDL 204的重分佈線實質上相似，因此為簡潔起見，此處省略對其的詳細描述。
現參看第16圖，然後形成凸塊下冶金(Under Bump Metallurgy，UBM)217以電連接介電層216上的導電層Mz。然而形成用作輸入/輸出(input/output，I/O)墊(包括例如凸塊下冶金217上的焊球)的外部連接器218A、218B及218C。在一些實施例中，外部連接器218A、218B及218C為設置在形成於重分佈線上的凸塊下冶金217上的球柵陣列(ball grid array，BGA)球、受控塌陷晶片連接器凸塊等。在一些實施例中，外部連接器218A、218B及218C用於將封裝200電連接其他封裝組件，包括例如另一晶粒、中介層、封裝基板、印刷電路板、母板等。
在一些實施例中，在此階段執行測試以確保適當地形成封裝200。此後，封裝200自載體部分脫離且翻轉。例如，載體201及可選的黏著層202可以自封裝200移 除。第17圖為根據本揭示內容的一些實施例的整合式扇出(Integrated Fan-Out，InFO)封裝200的橫剖面圖。如第17圖所示，在一些實施例的所得結構中，聚合物基層203作為絕緣層及保護層留在所得封裝200中，但本揭示內容不限於此。在一些實施例中，在移除黏著層202之後沉積帶層。在一些實施例中，執行雷射鑽孔製程以產生凹槽且自背側RDL 204曝露重分佈層焊墊。
在各種實施方式中，可以應用其他封裝技術來製造頂部封裝110及/或底部封裝120。可能的封裝技術包括，例如，基板上晶圓上晶片(Chip on Wafer on Substrate，CoWoS)、晶粒先面朝下InFO(Die first Face Down InFO)、晶粒先面朝上InFO(Die first Face Up InFO)、晶粒後面朝下InFO(Die last Face Down InFO)等。第2圖至第16圖圖式及描繪的製程為簡化實例，並不意在限制本揭示內容。
現參看第17圖，封裝200中的RDL結構包括一或多個介電層及一或多個導電層，一或多個介電層填充有諸如氮化鋁、氮化硼或其組合的導熱介電材料。特別地，RDL結構中的導電層可包括金屬層(例如，導電層Mx、My及Mz)。在一些實施例中，金屬層可包括鋁、銅或其組合，但本揭示內容不限於此。在一些實施例中，金屬層(例如，導電層Mx、My及Mz)中的至少一者具有實質上大於4微米(例如，在約4微米與約10微米之間的範圍內)的厚度。
頂部金屬層(例如，導電層Mz)與焊料特徵(例如，外部連接器218A、218B及218C)相鄰，且內部金屬層(例如，導電層Mx)與裝置晶粒211相鄰。中間金屬層(例如，導電層My)經由相應的通孔電耦合頂部金屬層及內部金屬層。
在一些實施例中，頂部金屬層的厚度實質上大於中間金屬層的厚度，且中間金屬層的厚度實質上大於內部金屬層的厚度。例如，在一些實施例中，內金屬層及內金屬層中的重分佈線的厚度可為約2微米，中間金屬層及中間金屬層的重分佈線的厚度可為約3微米，且頂部金屬層及頂部金屬層中的重分佈線的厚度可以實質上大於4微米(例如，約6微米)，但本揭示內容不限於此。
藉由為功率分佈提供相對較厚且較寬的頂部金屬層，RDL結構可以提供期望的電性能以及散熱。此外，藉由鄰接外部連接器218A、218B及218C佈置的厚頂部金屬層，亦可以減少經常導致延遲增加的電壓降效應(IR-drop effect)。
再次參看第1圖，在製造頂部封裝110及底部封裝120之後，可以將頂部封裝110安裝至底部封裝120上。在一些實施例中，執行晶粒焊接製程以回焊焊料特徵170。頂部封裝110與底部封裝120藉由回焊焊料特徵170電耦合在一起。如第1圖所示，底部填料(或密封材料、封裝膠等)視情況插入或形成在頂部封裝110與底部封裝120之間。此後，PoP結構可以安裝至印刷電路板140。
在一些實施例中，具有填充有諸如AlN或h-BN的導熱介電材料的介電層的一或多個厚金屬層(例如，實質上大於或等於6微米)亦可應用於形成底部封裝120的背側RDL結構128以進一步改善散熱，但本揭示內容不限於此。例如，背側RDL結構128的結構可包括位於模製材料之上且電連接裝置晶粒的一或多個導電層，以及分別設置在對應的一或多個導電層上的一或多個介電層。因此，在模製材料116中模製的裝置晶粒112及114電耦合重分佈層焊墊1282及背側RDL結構128中的導電層，以及佈線接合連接、RDL結構、通孔、頂部封裝基板118中的接觸墊及焊料特徵170。
藉由應用可為一或多個導熱介電層、一或多個厚金屬層或兩者的鄰接電連接器作為散熱結構的導熱水平層，與本文描述的實施例一致的3D IC可以藉由有效地傳遞由堆疊裝置晶粒產生且滯留在封裝內部區域中的熱量，及藉由電連接器移除熱量來改善IC封裝的散熱特性。因此，與本文描述的實施例一致的3D IC能夠將記憶體晶粒或晶片的操作溫度維持在期望範圍內(例如，在約80℃至約100℃內)。優化的散熱性能不僅提高了晶片的速度及性能，而且避免了3D IC封裝的潛在電遷移及可靠性問題。
在一些實施例中，揭示了一種封裝結構，包括焊料特徵、位於焊料特徵上的第一重分佈層結構及安裝在第一重分佈層結構上且電耦合第一重分佈層結構的晶粒。第一重分佈層結構包括填充有導熱介電材料的一或多個介電 層。
在一些實施例中，第一重分佈層結構包含一或多個導電層，一或多個導電層中的至少一者具有實質上大於4微米的厚度。在一些實施例中，第一重分佈層結構包含一或多個介電層，一或多個介電層填充有氮化鋁、氮化硼或其組合。在一些實施例中，第一重分佈層結構包含：頂部金屬層，鄰接焊料特徵；及中間金屬層，電耦合頂部金屬層，頂部金屬層的厚度實質上大於中間金屬層的厚度。在一些實施例中，第一重分佈層結構進一步包含內部金屬層，電耦合中間金屬層且鄰接晶粒，中間金屬層的厚度實質上大於內部金屬層的厚度。在一些實施例中，頂部金屬層包含鋁、銅或其組合。在一些實施例中，頂部金屬層的厚度實質上大於或等於6微米。在一些實施例中，封裝結構進一步包含第二重分佈層結構，電耦合晶粒及第一重分佈層結構。在一些實施例中，第二重分佈層結構包含填充有導熱介電材料的一或多個介電層。在一些實施例中，導熱介電材料的導熱度實質上大於或等於2Wm-1K-1。
在一些實施例中，亦揭示了一種半導體裝置，包括一或多個電連接器、一或多個晶粒的堆疊及一或多個重分佈層結構，一或多個重分佈層結構將一或多個晶粒與一或多個電連接器電耦合，且一或多個重分佈層結構中的至少一者包括鄰接一或多個電連接器相鄰的導熱水平層。
在一些實施例中，導熱水平層包含第一重分佈線，第一重分佈線的厚度實質上大於4微米。在一些實施例中， 導熱水平層進一步包含填充有導熱介電材料的介電層。在一些實施例中，導熱介電材料包含氮化鋁、氮化硼或其組合。在一些實施例中，一或多個重分佈層結構包含背側重分佈層結構或前側重分佈層結構。
在一些實施例中，亦揭示了一種製造封裝結構的方法，包含：將第一晶粒附接至封裝中；施加第一模製材料圍繞第一晶粒；在第一模製材料下方形成一或多個第一導電層且一或多個第一導電層電連接第一晶粒；及形成一或多個第一介電層，一或多個第一介電層包含氮化鋁、氮化硼或其組合，一或多個第一介電層中的任一者設置在相應的第一導電層上。
在一些實施例中，此方法進一步包含：在第一模製材料上形成一或多個第二導電層且一或多個第二導電層電連接第一晶粒；及形成一或多個第二介電層，一或多個第二介電層中的任一者設置在相應的第二導電層上。在一些實施例中，形成一或多個第一導電層包含：形成一或多個第一導電層中的至少一者，一或多個第一導電層的厚度實質上大於4微米。在一些實施例中，形成一或多個第一介電層包含：形成一或多個第一介電層中的至少一者，一或多個第一介電層填充有導熱介電材料，導熱介電材料的導熱度實質上大於或等於2Wm-1K-1。在一些實施例中，此方法進一步包含：形成一或多個電連接器電連接一或多個第一導電層。
上文概述了數個實施例的特徵，使得熟習此項技術 者可以更好地理解本揭示內容的各態樣。熟習此項技術者應理解，熟習此項技術者可以容易地將本揭示內容用作設計或修改其他製程及結構的基礎，以實現與本文介紹的實施例相同的目的及/或實現相同的優點。熟習此項技術者亦應認識到，此些等效構造不脫離本揭示內容的精神及範疇，且在不脫離本揭示內容的精神及範疇的情況下，此些等效構造可以進行各種改變、替代及變更。
200:封裝
201:載體
202:黏著層
203:聚合物基層
204:背側重分佈層
209:導電通孔
211:裝置晶粒
212:模製化合物
213、214、215、216:介電層
217:凸塊下冶金
218A、218B、218C:外部連接器
Mx、My、Mz:導電層
Vx、Vy、Vz:通孔

Claims (10)

  1. 一種封裝結構，包含：一焊料特徵；一第一重分佈層結構，位於該焊料特徵上，該第一重分佈層結構包含填充有一導熱介電材料的一或多個介電層、鄰接該焊料特徵的一頂部金屬層以及電耦合該頂部金屬層的一中間金屬層，該頂部金屬層的一厚度實質上大於該中間金屬層的一厚度；及一晶粒，安裝在該第一重分佈層結構上且電耦合該第一重分佈層結構。
  2. 如請求項1所述之封裝結構，其中該第一重分佈層結構包含一或多個導電層，該一或多個導電層中的至少一者具有實質上大於4微米的一厚度。
  3. 如請求項1所述之封裝結構，其中該第一重分佈層結構包含一或多個介電層，該一或多個介電層填充有氮化鋁、氮化硼或其組合。
  4. 如請求項1所述之封裝結構，其中該第一重分佈層結構進一步包含一內部金屬層，電耦合該中間金屬層且鄰接該晶粒，該中間金屬層的該厚度實質上大於該內部金屬層的一厚度。
  5. 一種半導體裝置，包含：一或多個電連接器；一或多個晶粒的一堆疊；及一或多個重分佈層結構，將該一或多個晶粒與該一或多個電連接器電耦合，該一或多個重分佈層結構中的至少一者包含鄰接該一或多個電連接器的一導熱水平層，其中該一或多個重分佈層結構中的一者包含鄰接該一或多個電連接器的一頂部金屬層以及電耦合該頂部金屬層的一中間金屬層，該頂部金屬層的一厚度實質上大於該中間金屬層的一厚度。
  6. 如請求項5所述之半導體裝置，其中該導熱水平層包含一第一重分佈線，該第一重分佈線的一厚度實質上大於4微米。
  7. 如請求項5所述之半導體裝置，其中該一或多個重分佈層結構包含一背側重分佈層結構或一前側重分佈層結構。
  8. 一種製造封裝結構的方法，包含：將一第一晶粒附接至一封裝中；施加一第一模製材料圍繞該第一晶粒；在該第一模製材料下方形成一或多個第一導電層且該一或多個第一導電層電連接該第一晶粒；及 形成一或多個第一介電層，該一或多個第一介電層包含氮化鋁、氮化硼或其組合，該一或多個第一介電層中的任一者設置在一相應的第一導電層上。
  9. 如請求項8所述之方法，其中形成該一或多個第一介電層包含：形成該一或多個第一介電層中的至少一者，該一或多個第一介電層填充有一導熱介電材料，該導熱介電材料的一導熱度實質上大於或等於2Wm-1K-1。
  10. 如請求項8所述之方法，進一步包含：形成一或多個電連接器電連接該一或多個第一導電層。
TW110135010A 2020-11-10 2021-09-17 封裝結構、半導體裝置、及封裝結構的製造方法 TWI806163B (zh)

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