CN104350593A - 具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装 - Google Patents

具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装 Download PDF

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CN104350593A
CN104350593A CN201280073453.6A CN201280073453A CN104350593A CN 104350593 A CN104350593 A CN 104350593A CN 201280073453 A CN201280073453 A CN 201280073453A CN 104350593 A CN104350593 A CN 104350593A
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vsc
msd
coupled
semiconductor
die
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CN104350593B (zh
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B·E·谢
S·佩雷尔曼
K·C·黄
J·C·P·孔
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Intel Corp
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Intel Corp
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Abstract

本发明描述了具有居间垂直侧边芯片的半导体多管芯结构，及容纳该半导体多管芯结构的封装。在一个示例中，多管芯半导体结构包括具有半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构。还包括具有半导体管芯的第二大致水平排布的第二MSD结构。居间垂直侧边芯片(i-VSC)被置于第一和第二MSD结构之间，并与其电气耦接。

Description

具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装
发明领域
本发明的实施例涉及半导体封装领域，特别是具有居间垂直侧边芯片的多管芯半导体结构,以及容纳该多管芯半导体结构的半导体封装。
发明背景
如今的消费类电子市场经常需要复杂的功能，这就要求有非常复杂的电路。缩放得到越来越小的基础构建块，如晶体管，使得随着每一个进步的世代在单一管芯上纳入更为复杂的电路成为可能。半导体封装用于保护集成电路(IC)芯片或管芯，同时为管芯提供至外围电路的电气接口。随着对更小电子设备日益增长的需求，半导体封装被设计得更为紧凑而又必须支持更高的电路密度。例如，现今的一些半导体封装采用无芯基板，这样的基板不包括通常用于传统基板的厚树脂芯材层。此外，对于更高性能器件的要求致使需要一种改进的半导体封装，其能够实现与随后的装配制程相兼容的薄的封装轮廓和低的整体弯曲度。
另一方面，尽管缩放通常被视为尺寸上的缩减，但在给定空间内纳入额外的半导体管芯也被予以考虑。然而，当试图在同一封装中封装多颗半导体管芯时，结构性问题会随之产生。例如，添加多个管芯堆能增添功能性，但在半导体封装内不断减少的空间可用性可能对增加该功能造成障碍。
附图的简要说明
图1A说明了根据本发明一个实施例的被封装的具有垂直侧边芯片的半导体多管芯结构的剖视图。
图1B是图1A结构中部分的放大图。
图1C是图1A结构的顶视图。
图2A说明了根据本发明另一实施例的被封装的具有居间垂直侧边芯片的半导体多管芯结构的剖视图。
图2B是图2A结构中部分的放大图。
图2C是图2A结构中另一部分的放大图。
图2D是图2A结构根据一个实施例的顶视图。
图2E是图2A结构根据另一实施例的顶视图。
图3A-3I说明了根据本发明的一个实施例，在制造被封装的多管芯结构的方法中的各种操作的各种视图，其中被封装的多管芯结构具有包括居间垂直侧边芯片在内的一个或多个垂直侧边芯片。
图4是根据本发明一个实施例的计算机系统的示意图。
发明的详细说明
描述了含有居间(intermediate)垂直侧边芯片的多管芯半导体结构，以及容纳该多管芯半导体结构的封装。在随后的描述中，公开了许多具体细节，例如管芯排布和封装架构，以提供对本发明实施例的透彻理解。对于本领域的技术人员而言，本发明实施例显然无需这些具体细节亦可实施。在其他的实例中，一些为人熟知的特征，如集成电路设计布局，并没有予以详细地描述以免不必要地模糊本发明的实施例。此外，还应理解，附图中所示的各种实施例是示例性的描绘，且并不一定按比例绘制。
本发明中所描述的一个或多个实施例涉及实现三维(3D)集成封装系统的可控边缘芯片互连的方法。例如，在一个实施例中，多管芯的排布(例如多芯片封装,或MCP)可用于制造3D立方体处理器和封装内系统(SIP)技术。在一个实施例中，为了多管芯结构的组装，进行了可控的边缘芯片塌陷。
如下文中更详尽描述的，本发明的实施例包括通过垂直侧边芯片(VSC)互连制造集成封装系统。VSC互连可允许一个或多个硅器件连接于一个主硅管芯或多个堆叠的管芯的一侧边，以形成高功能性且紧凑的集成系统。此类系统可有益于下一代超移动数字应用，例如，移动互联网设备(MID)，个人数字助理(PDA)，智能手机，以及数字相机。亦如下文中更详尽描述的，在一个实施例中，提供了一种用于形成管芯侧边焊盘(DSP)以实现垂直侧边芯片互连的制造方法和工艺流程。
更普遍地来说，要通过使用多个封装来集成诸如CPU，芯片组，存储器，传感器，光学元件，MEMS等各种功能器件，就需要广阔的平台或主板空间。各种功能器件的集成已由诸如混合堆叠封装、3D堆叠封装和封装体叠层(POP)技术等3D及系统化封装设计技术予以解决。然而，高输入/输出密度，增加的器件功能性和集成复杂度的要求可能约束着封装的外形参数和尺寸。另外，无论是传统引线接合，还是更新的穿硅过孔(TSV)技术的应用，在3D堆叠配置中会存在对于上部或顶部的器件(多个)的最小I/O接收端。此外，对3D堆叠管芯封装中底部器件的热应力可能是源于采用TSV技术的一个不良后果。如今的TSV设计通常需要底部的管芯将整个电源引导至堆叠的硅管芯，导致可能的进一步限制。
相反，根据本发明的一个或多个实施例，一个或多个垂直侧边芯片被用于多管芯结构以显著增加I/O管脚密度，并增加到主堆叠管芯(MSD)中的硅器件的通过直接连接或通道(比如通过利用一个或多个管芯侧边焊盘(DSP)，焊料/金属连接，管芯背面金属化(DBM)，表面活化接合(SAB)和TSV技术)的额外电连接。这样的方法可实现多个器件的集成，例如将CPU，网通/应用/图形处理器，芯片组，闪存等其中一个或多个集成至单一封装内。这样，在一个实施例中，进而可实现主板系统和整体形状因数的进一步小型化。在一个或多个实施例中，本文中描述的3D堆叠集成进一步实现了功能器件间(例如CPU至芯片组通信，或CPU至闪存)的直接通信和短途互连。在系统中功能器件之间，通信速度和效率能因此改善。在一个实施例中，本文所描述的结构布局通过外围的VSC提供了从MSD中的堆叠的硅器件至外部系统的额外散热通道。通过封装冷却系统的散热可由诸如直接的空气通风装置或液冷系统而进一步增强。
在一个实施例中，具有连接至主堆叠管芯(MSD)结构的垂直侧边芯片(VSC)的3D集成封装系统，能实现高功能性和紧凑性的半导体系统设备。例如，图1A说明了根据一个实施例，具有垂直侧边芯片的被封装的半导体多管芯结构的剖视图。图1B是图1A结构中部分的放大图。图1C是图1A结构的顶视图。
参照图1A和1B，3D集成封装系统包括耦接至主堆叠管芯(MSD)结构120的VSC 100。参照图1C，超过一个VSC 100可被耦接至MSD结构120，例如图1C中描绘了四个VSC 100。每个VSC 100包括有源层102，如硅有源层。一个或多个VSC互连104，例如一个或多个焊料凸块，将每个VSC 100耦接至MSD结构120。MSD结构120可包括呈大致水平排布的多个堆叠管芯。例如，MSD结构120包括堆叠的管芯122、124、126、128、130、132和134。还示出了相应的有源层123、125、127、129、131、133和135。可包括MSD结构120中一个或多个堆叠管芯的管芯侧边焊盘结构，如管芯侧边焊盘结构136，以用于与VSC互连耦接，如图1A和1B所示。可选地，或随同管芯侧边焊盘结构136一起，可包括MSD结构120中一个或多个堆叠管芯的管芯背面金属走线138，以用于同VSC互连104耦接，如图1B所示。管芯背面金属走线138可被包括在钝化层140中，作为管芯背面金属化(DBM)层142的一部分，亦如图1B所示。
依然参考图1B，一个或多个堆叠的管芯122、124、126、128、130、132和134的背面可包括一个或多个穿硅过孔(TSV)144。此外，再次参考图1A，VSC 100和MSD结构120被置于封装基板或主板146上，且该配置可包括介于中间的底部填充材料层148。MSD结构120通过诸如焊料互连150电气耦接至封装基板或主板146，亦如图1A所示。封装基板或主板146可为附着的集成电路器件提供机械支撑和信号路径。在一个实施例中，封装基板或主板146是多层有机基板。在另一个实施例中，封装基板或主板146是陶瓷基板。
总体而言，根据一个实施例，图1A-1C中的3D集成系统包括一个或多个VSC 100，其通过VSC互连104，例如采用焊料凸块扩散或表面活化接合(SAB)，耦接至MSD结构120。VSC 100的硅有源层102通过管芯侧边焊盘(DSP)136或管芯背面金属化(DBM)层142的其中一种或两种，并且可能通过穿硅过孔(TSV)结构144，耦接到MSD结构120中的硅器件。在不使用管芯侧边焊盘的情况下，DBM层142中的金属层138可做得比通常更厚，以顺应与VSC互连104间良好的交叠。在一个实施例中，MSD结构120中的管芯通过在相应有源层123/125处的SAB彼此间电气耦接。在一个实施例中，MSD结构120的管芯为硅管芯，例如但不仅限于基于逻辑或存储器的设备，如处理器，芯片组，闪存，传感器，光学元件和MEMS等。
在另一个实施例中，通过采用居间垂直侧边芯片(i-VSC)，实现了更高等级的系统集成。例如，图2A说明了根据一个实施例，具有居间垂直侧边芯片的被封装的半导体多管芯结构的剖视图。图2B是图2A结构中部分的放大图。图2C是图2A结构中另一部分的放大图。
参照图2A，2B和2C，3D集成封装系统包括耦接到两个主堆叠管芯(MSD)结构220和221的居间垂直侧边芯片(i-VSC)201。参照图2D和2E，如下文中更详细的描述，额外的VSC 200或200'(比如，非居间VSC)可被耦接至MSD结构220和221。i-VSC 201包括有源层202，比如硅有源层。一个或多个VSC互连204，例如一个或多个焊料凸块，将i-VSC201的有源层202耦接至MSD结构220。MSD结构220可包括呈大致水平排布的多个堆叠管芯。i-VSC 201还可包括管芯背面金属走线260。一个或多个VSC互连262，例如一个或多个焊料凸块，将i-VSC 201的管芯背面金属走线260耦接至MSD结构221。管芯背面金属走线260可被包括在钝化层264中，作为管芯背面金属化(DBM)层266的一部分，如图2B所示。
可包括MSD结构220中一个或多个堆叠管芯的管芯侧边焊盘结构，如管芯侧边焊盘结构236，以用于同i-VSC互连204相耦接，如图2A和2B所示。可选地，或随同管芯侧边焊盘结构236一起，可包括MSD结构220中一个或多个堆叠管芯的管芯背面金属走线238，以用于同i-VSC互连204相耦接，如图2B所示。管芯背面金属走线238可被包括在钝化层240中，作为管芯背面金属化(DBM)层242的一部分，亦如图2B所示。同样，可包括MSD结构221中一个或多个堆叠管芯的管芯侧边焊盘结构，如管芯侧边焊盘结构236'，以用于同i-VSC互连262相耦接，如图2A和2B所示。可选地，或随同管芯侧边焊盘结构236'一起，可包括MSD结构221中一个或多个堆叠管芯的管芯背面金属走线238'，以用于同VSC互连262相耦接，如图2B所示。管芯背面金属走线238'可被包括在钝化层240'中，作为管芯背面金属化(DBM)层242'的一部分，亦如图2B所示。MSD结构221和220可通过一个或多个包括在i-VSC 201中的穿硅过孔(TSV)270电气耦接至彼此，如图2A，2B和2C所示。
依然参照图2B，MSD结构220或221的堆叠的管芯的其中一个或多个的背面可包括一个或多个穿硅过孔(TSV)244或244'。此外，再次参照图2A，i-VSC 201和MSD结构220和221可被置于封装基板或主板246上，且该配置可包括介于中间的底部填充材料层248。MSD结构220和221可通过诸如焊料互连250或250'电气耦接至封装基板或主板246，亦如图2A所示。封装基板或主板246可为附着的集成电路器件提供机械支撑和信号路径。在一个实施例中，封装基板或主板246是多层有机基板。在另一个实施例中，封装基板或主板246是陶瓷基板。
另外，再次参照图2A和2C，i-VSC 201可包括管芯侧边焊盘结构272。i-VSC 201可通过例如焊料互连274和管芯侧边焊盘结构272电气耦接至封装基板或主板246，如图2A和2C所示。
如上文简要所述，参照图2D和2E，额外的VSC 200或200'(比如，非i-VSC)可被耦接至MSD结构220和221。图2D是图2A结构根据一个实施例的顶视图。图2E是图2A结构根据另一个实施例的顶视图。类似于结合图1C所描述的结构，额外的VSC 200可被包括在内，并被耦接至未被i-VSC 201占据的MSD结构220和221的面。例如，图2D给出了除i-VSC201以外还包括六个VSC 200的示例。与结合图1C所描述的方式类似，VSC 200可通过互连280耦接至MSD结构220或221。在另外一个例子中，图2E给出了除i-VSC 201以外还包括两个常规或小尺寸的VSC 200和两个大尺寸的VSC 200'的示例。与结合图1C所描述的方式类似，VSC 200和200'通过互连280耦接至MSD结构220或221。需要理解的是，图2D和2E的结构是示例性的，并不旨在限制用以构成3D多管芯结构的MSD与i-VSC及VSC的多种可能的组合中的任一种。
在一个实施例中，给出了适用于生产具有DSP以实现VSC和i-VSC互连的结构的工艺流程。例如，图3A-3I说明了根据本发明的一个实施例，在制造被封装的多管芯结构的方法中的各个操作的各种视图，该多管芯结构具有包括居间侧边芯片在内的一个或多个垂直侧边芯片。
参照图3A，晶片钻孔工艺被用于在硅衬底或晶片306中通过诸如激光或机械钻孔工艺形成穿硅通道302和部分穿硅通道304。化学镀(electro-lessplating)工艺随后可被用以在图3A所示的硅通道中形成薄的籽晶层308，如图3B所示。参照图3C，电解电镀工艺可被用于形成穿硅过孔310和部分穿硅过孔312，如图3C所示。
如图3D所示，管芯背面金属化(DBM)工艺被用于在钝化(绝缘)层318中形成DBM层，其包括管芯背面金属走线部分314和管芯背面金属焊盘部分316。参照图3E，晶片制造的前段制程(FEOL)被用于形成硅有源层320，如包括晶体管和金属层及走线的层。通过结合图3A-3E而描述的工艺所形成的各个晶片随后可通过例如表面活化接合(SAB)经由晶片级堆叠工艺而被机械和电气耦接至彼此，从而提供由晶片324，326和328构成的晶片堆322，如图3F所示。
参照图3G，图3F中的晶片堆322通过堆叠晶片切割工艺被分割以形成独立的MSD结构330。例如，高质量和精度的堆叠晶片切割可由激光水射流(water laser-jet)切割技术或机械锯切工艺来实现。一个或多个VSC的管芯332通过垂直侧边芯片连接工艺被电气耦接至MSD结构330，如图3H所示。参照图3I，图3H中的结构然后通过诸如3D芯片至封装/电路板连接，回流焊，底部填充和焊球连接工艺被表面贴装至基板或主板340。需要理解的是，上述流程操作可按不同的顺序进行，且相比前文的描述可包括更多或更少的流程操作。
相应地，一个或多个实施例涉及3D电子半导体封装，该封装包括主硅管芯或多个堆叠管芯结构，其具有与一个或多个垂直侧边芯片进行互连的管芯背面金属化和穿硅过孔。在一个实施例中，一个或多个垂直侧边芯片通过管芯侧边焊盘结构被连接至多个堆叠管芯结构。在一个实施例中，管芯侧边焊盘制造方法包括晶片钻孔，如激光或机械钻孔，以及电镀工艺，如化学镀和电解电镀，以形成部分硅过孔金属化。在一个实施例中，使用晶片堆叠和切割工艺，如激光水射流或机械切割，通过切穿部分硅过孔金属化区域而将堆叠晶片分割成独立的多堆叠管芯结构。在一个实施例中，垂直侧边芯片连接和表面贴装工艺被用于组装一个3D集成封装系统。
本发明的实施例可用于新兴业务市场领域的半导体生产和封装行业，这些新兴业务市场领域例如，但不仅限于，便携式多媒体应用如移动互联网设备(MID)，个人数字助理(PDA)，智能手机，数字相机等。实施例可实现半导体系统设备的生产，这种半导体系统设备满足超移动数字手持应用的需求，例如，系统成本减少的高功能性和紧凑型手持设备。
除上述实施例外，或对其进行补充，其他实施例可包括以众多其他封装选择之一来封装半导体多管芯结构。其中一个选择是将多管芯结构封装在由BBUL工艺形成的无芯基板中。BBUL是一种处理器封装技术，这种技术无焊接凸块，因为它并不使用通常的小焊料凸块来将管芯连接至处理器封装走线。它具有构建(build-up)层，因为其生长或构建在管芯或多管芯结构周围。现今的一些半导体封装采用无芯基板，这样的基板不包括通常用于传统基板的厚树脂芯层。在一个实施例中，作为BBUL工艺的一部分，在半导体管芯的有源侧上利用半加成制程(SAP)形成导电过孔和布线层以完成剩余的层。在一个实施例中，形成有外部的接触层。在一个实施例中，外部导电触点阵列是球栅阵列(BGA)。在另一个实施例中，外部导电触点阵列是例如但不仅限于平面栅格阵列(LGA)或管脚阵列(PGA)的阵列。
在一个实施例中，基板是无芯基板，因为使用面板来支撑半导体多管芯结构的封装直至形成外部导电触点阵列。然后，面板被移除以提供半导体多管芯结构的无芯封装。因此，在一个实施例中，“无芯”(coreless)一词用以表示：在其之上形成封装体用于容纳多管芯结构的支撑件在建造过程的最后会被最终移除。在一个具体的实施例中，无芯基板是在制造过程完成后并不包括厚芯的基板。作为示例，厚芯可为由增强材料(如用于主板中的材料)所构成的芯材，且其中可包括导电过孔。需要理解的是，管芯接合薄膜可被保留或移除。无论哪种情况，在移除面板后，保留或移除管芯接合薄膜都会产生无芯基板。更进一步而言，因为基板不含有厚芯，如纤维增强的玻璃环氧树脂，可将基板视为无芯基板。
在一个实施例中，封装的半导体多管芯结构可为完全嵌入并被包围的半导体多管芯结构。正如本公开中所采用的，“完全嵌入并被包围的”是指半导体多管芯结构的所有表面都与基板的封装薄膜(如介电层)相接触，或者至少与容纳在封装薄膜中的材料相接触。换而言之，“完全嵌入并被包围的”是指半导体多管芯结构的所有裸露面都与基板的封装薄膜相接触。
在一个实施例中，封装的半导体多管芯结构可为完全嵌入的半导体多管芯结构。正如本公开中所采用的，“完全嵌入的”是指半导体多管芯结构的有源表面和整个侧壁都与基板的封装薄膜(如介电层)相接触，或者至少与容纳在封装薄膜中的材料相接触。换而言之，“完全嵌入的”是指有源表面的所有裸露区域和多管芯结构的最后一颗半导体管芯的整个侧壁的裸露部分都与基板的封装薄膜相接触。然而，在这种情况下，半导体多管芯结构并不是“被包围的”，因为最后一颗半导体管芯的背面与基板的封装薄膜或与容纳在封装薄膜中的材料并不相接触。在第一个实施例中，最后一颗半导体管芯的背面突出于基板管芯侧的整体水平表面。在第二个实施例中，最后一颗半导体管芯并无表面突出于基板管芯侧的整体水平表面。
相比于上述“完全嵌入并被包围的”和“完全嵌入的”定义，“部分嵌入的”多管芯结构是这样一种结构，其最后一颗管芯有一个完整表面，但只有一部分侧壁是与基板(如无芯基板)的封装薄膜相接触，或至少与容纳在封装薄膜中的材料相接触。在进一步的对比中，“非嵌入的”多管芯结构的最后一颗管芯有至多一个表面，且没有任何侧壁的部分与基板(如无芯基板)的封装薄膜相接触，或与容纳在封装薄膜中的材料相接触。
在一个实施例中，基板包括包封(encapsulant)层。在一个实施例中，用于容纳具有居间垂直侧边芯片的多管芯半导体结构的半导体封装包括在该基板底面的基础(foundation)基板。例如，其中半导体多管芯结构是诸如智能手机实施例或手持阅读器实施例等手持设备中的一部分时，基础基板可以是主板、外层壳(如个人使用中接触到的部分)、或为主板及外层壳(如个人使用中接触到的部分)二者。
另一方面，用于容纳具有居间垂直侧边芯片的多管芯半导体结构的半导体封装在基板的芯中包括该多管芯结构。在一个这样的实施例中，多管芯半导体结构被嵌入在同样的芯中。在一个实施例中，封装过程可在载体上进行。载体，如面板，含有被置于其中的数个腔体，每个腔体有一尺寸以接纳半导体多管芯结构。在处理过程中，为了处理的实用性，相同的结构会被配对以构造背对背的装置。因此，处理量被有效提高了一倍。
例如，面板可在每一侧都含有1000个凹槽，使得由单个面板可制造2000个独立的封装。该面板可包括黏附剥离层和粘合剂。可在装置的每个末端都提供切割区域，以用于分立处理。利用管芯接合薄膜将多管芯结构的背面接合至面板。包封层可通过层压工艺形成。在另一个实施例中，一个或多个包封层通过在晶片大小的装置阵列上旋涂，并对电介质进行固化而形成。
在一个实施例中，在封装工艺后，一个或多个上述容纳了多管芯结构的半导体封装在与其它封装相配对。例如，在无焊內建层制作后,可利用热压接合(TCB)工艺耦接两个或多个独立封装的多管芯结构。
图4是根据本发明一个实施例的计算机系统400的示意图。根据本公开所提出的任何公开实施例及其等效项，如图所示计算机系统400(也称为电子系统400)，可包含具有居间垂直侧边芯片的半导体多管芯结构。计算机系统400可以是移动设备，如上网本。计算机系统400可以是移动设备，如无线智能手机。计算机系统400可以是台式电脑。计算机系统400可以是手持阅读器。
在一个实施例中，电子系统400是包括了用以电气耦接电子系统400中不同器件的系统总线420的计算机系统。根据不同的实施例，系统总线420是单独的总线或任意总线的组合。电子系统400包括用以给集成电路410供电的电压源430。在一些实施例中，电压源430通过系统总线420向集成电路410提供电流。
根据一个实施例，集成电路410电气耦接至系统总线420，且包括任何电路或电路的组合。在一个实施例中，集成电路410包括可以是任何类型的处理器412。如本文所采用的，处理器412可以表示任何电路，例如但不仅限于，微处理器，微控制器，图形处理器，数字信号处理器，或其它处理器。在一个实施例中，如本文所公开的，处理器412包括具有居间垂直侧边芯片的半导体多管芯结构。在一个实施例中，处理器的记忆高速缓存中使用了SRAM实施方案。可被包括在集成电路410中的其它类型的电路是定制电路或专用集成电路(ASIC),如被用于诸如移动电话、智能手机、传呼机、便携式电脑、对讲机和类似电子系统的无线设备中的通信电路414。在一个实施例中，处理器410包括片上存储器416，如静态随机存取存储器(SRAM)。在一个实施例中，处理器410包括内嵌片上存储器416如内嵌动态随机存取存储器(eDRAM)。
在一个实施例中，集成电路410会同后续集成电路411互补。有用的实施例包括双处理器413和双通信电路415和双片上存储器417，如SRAM。在一个实施例中，双集成电路410包括内嵌片上存储器417，如eDRAM。
在一个实施例中，电子系统400也包括外部存储器440，这又可包括一个或多个适合特定应用的存储器单元，如RAM形式的主存储器442，一个或多个硬盘驱动器444，和/或一个或多个处理可移动介质446，如磁盘，光盘(CD)，数字可变光盘(DVD)，闪存驱动器，和其它本领域中已知的可移动介质的驱动器。根据一个实施例，外部存储器440也可以是内嵌存储器448，如在内嵌TSV管芯堆中的第一颗管芯。
在一个实施例中，电子系统400还包括显示设备450，音频输出460。在一个实施例中，电子系统400包括输入设备，如控制器470，其可以是键盘，鼠标，轨迹球，游戏控制器，麦克风，语音识别设备，或其它任何将信息输入至电子系统400中的输入设备。在一个实施例中，输入设备是摄像头。在一个实施例中，输入设备是数字录音设备。在一个实施例中，输入设备是摄像头和数字录音设备。
如图所示，集成电路410可在多种不同的实施方式中实现，这些实施方式包括根据任何所公开实施例及其等效项的具有居间垂直侧边芯片的半导体多管芯结构、电子系统、计算机系统、一个或多个集成电路制作方法、以及电子装配件的一个或多个制造方法，该电子装配件包括根据本文各个实施例及其本领域所认可的等效项中所阐述的任何公开实施例的具有居间垂直侧边芯片的半导体多管芯结构。对于内嵌在根据任何所公开的具有居间垂直侧边芯片的半导体多管芯结构实施例及其等效项的处理器安装基板上的微电子管芯，元件、材料、几何形状、尺寸和操作顺序都可以改变，以符合包括阵列触点数、阵列触点配置在内的特定的输入/输出耦接要求。如图4中虚线部分所示，还可包括基础基板。亦如图4所描绘，作为任选项，也可包括无源器件。
本发明的实施例包括具有居间垂直侧边芯片的半导体多管芯结构，及含有该半导体多管芯结构的封装。
在一个实施例中，多管芯半导体结构包括具有半导体管芯的第一大致水平排布(arrangement)的第一主堆叠管芯(MSD)结构。另外还包括具有半导体管芯的第二大致水平排布的第二MSD结构。居间垂直侧边芯片(i-VSC)被置于第一和第二MSD结构之间，并与其进行电气耦接。
在一个实施例中，i-VSC通过i-VSC的一个或多个前端互连耦接至第一MSD结构，所述前端互连被置于i-VSC的有源侧。
在一个实施例中，i-VSC的前端互连通过第一MSD结构的管芯侧边焊盘(DSP)耦接到第一MSD结构。
在一个实施例中，i-VSC的前端互连通过第一MSD结构中管芯的金属走线的末端耦接到第一MSD结构。
在一个实施例中，i-VSC通过其管芯背面金属化(DBM)耦接至第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构的DSP耦接到第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构中管芯的金属走线的末端耦接到第二MSD结构。
在一个实施例中，i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接第一和第二MSD结构。
在一个实施例中，i-VSC通过其一个或多个前端互连以及第一MSD结构的DSP耦接至第一MSD结构，i-VSC通过其DBM以及第二MSD结构的DSP耦接至第二MSD结构，并且i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接第一和第二MSD结构。
在一个实施例中，半导体封装包括基板。具有半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构被互连至基板。具有半导体管芯的第二大致水平排布的半导体管芯的第二MSD结构被互连至基板。居间垂直侧边芯片(i-VSC)被置于第一和第二MSD结构之间，并与其进行电气耦接。i-VSC也被互连至基板。底部填充材料被置于基板和第一及第二MSD结构之间，以及基板和i-VSC之间。
在一个实施例中，i-VSC通过其管芯侧边焊盘(DSP)互连至基板。
在一个实施例中，i-VSC通过其一个或多个前端互连耦接至第一MSD结构，前端互连被置于i-VSC的有源侧。
在一个实施例中，i-VSC的前端互连通过第一MSD结构的DSP耦接到第一MSD结构。
在一个实施例中，i-VSC的前端互连通过第一MSD结构中管芯的金属走线的末端耦接到第一MSD结构。
在一个实施例中，i-VSC通过其管芯背面金属化(DBM)耦接至第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构的DSP耦接到第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构中管芯的金属走线的末端耦接到第二MSD结构。
在一个实施例中，i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接第一和第二MSD结构。
在一个实施例中，i-VSC通过其一个或多个前端互连以及第一MSD结构的DSP耦接至第一MSD结构，i-VSC通过其DBM以及第二MSD结构的DSP耦接至第二MSD结构，并且i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接第一和第二MSD结构。
在一个实施例中，半导体封装包括基板。具有半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构被互连至基板。具有半导体管芯的第二大致水平排布的第二MSD结构被互连至基板。居间垂直侧边芯片(i-VSC)被置于第一和第二MSD结构之间，并与其进行电气耦接。i-VSC也被互连至基板。一个或多个垂直侧边芯片(VSC)被安置为与第一和第二MSD结构之一或两者相邻，并与其电气耦接。然而，上述一个或多个VSC被互连至基板。底部填充材料被置于基板和第一及第二MSD结构之间，基板和i-VSC之间，以及基板和一个或多个VSC之间。
在一个实施例中，上述一个或多个VSC包括三个耦接至第一MSD结构，但不耦接至第二MSD结构的VSC，且包括三个耦接至第二MSD结构，但不耦接至第一MSD结构的VSC。
在一个实施例中，上述一个或多个VSC包括一个耦接至第一MSD结构，但不耦接至第二MSD结构的VSC，包括一个耦接至第二MSD结构，但不耦接至第一MSD结构的VSC，还包括两个分别都耦接至第一和第二MSD结构的VSC。
在一个实施例中，i-VSC通过其管芯侧边焊盘(DSP)互连至基板。
在一个实施例中，i-VSC通过其一个或多个前端互连耦接至第一MSD结构，前端互连被置于i-VSC的有源侧。
在一个实施例中，i-VSC的前端互连通过第一MSD结构的DSP耦接到第一MSD结构。
在一个实施例中，i-VSC的前端互连通过第一MSD结构中管芯的金属走线的末端耦接到第一MSD结构。
在一个实施例中，i-VSC通过其管芯背面金属化(DBM)耦接至第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构的DSP耦接到第二MSD结构。
在一个实施例中，i-VSC的DBM通过第二MSD结构中管芯的金属走线的末端耦接到第二MSD结构。
在一个实施例中，i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接第一和第二MSD结构。

Claims (30)

1.一种多管芯半导体结构，包括：
包括半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构；
包括半导体管芯的第二大致水平排布的第二MSD结构；以及
置于所述第一和第二MSD结构之间，并与其电气耦接的居间垂直侧边芯片(i-VSC)。
2.权利要求1中的多管芯半导体结构，其中所述i-VSC通过所述i-VSC的前端互连耦接到所述第一MSD结构，所述前端互连置于所述i-VSC的有源侧。
3.权利要求2中的多管芯半导体结构，其中所述i-VSC的前端互连通过所述第一MSD结构的管芯侧边焊盘(DSP)耦接至所述第一MSD结构。
4.权利要求2中的多管芯半导体结构，其中所述i-VSC的前端互连通过所述第一MSD结构中管芯的金属走线的末端耦接至所述第一MSD结构。
5.权利要求1中的多管芯半导体结构，其中所述i-VSC通过所述i-VSC的管芯背面金属化(DBM)耦接至所述第二MSD结构。
6.权利要求5中的多管芯半导体结构，其中所述i-VSC的DBM通过所述第二MSD结构的DSP耦接至所述第二MSD结构。
7.权利要求5中的多管芯半导体结构，其中所述i-VSC的DBM通过所述第二MSD结构中管芯的金属走线的末端耦接至所述第二MSD结构。
8.权利要求1中的多管芯半导体结构，其中所述i-VSC通过所述i-VSC的一个或多个穿硅过孔(TSV)电气耦接所述第一和第二MSD结构。
9.权利要求1中的多管芯半导体结构，其中所述i-VSC通过其一个或多个前端互连以及所述第一MSD结构的DSP耦接至所述第一MSD结构，所述i-VSC通过其DBM以及所述第二MSD结构的DSP耦接至所述第二MSD结构，并且所述i-VSC通过其一个或多个穿硅过孔(TSV)电气耦接所述第一和第二MSD结构。
10.一种半导体封装，包括：
基板；
包括半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构，所述第一MSD结构互连至所述基板；
包括半导体管芯的第二大致水平排布的第二MSD结构，所述第二MSD结构互连至所述基板；
置于所述第一和第二MSD结构之间，并与其电气耦接的居间垂直侧边芯片(i-VSC)，该i-VSC互连至所述基板；以及
置于所述第一和第二MSD之间，且置于所述基板与所述VSC之间的底部填充材料。
11.权利要求10中的半导体封装，其中所述i-VSC通过所述i-VSC的管芯侧边焊盘(DSP)互连至所述基板。
12.权利要求10中的半导体封装，其中所述i-VSC通过所述i-VSC的一个或多个前端互连耦接到所述第一MSD结构，所述前端互连置于所述i-VSC的有源侧。
13.权利要求12中的半导体封装，其中所述i-VSC的前端互连通过所述第一MSD结构的DSP耦接至所述第一MSD结构。
14.权利要求12中的半导体封装，其中所述i-VSC的前端互连通过所述第一MSD结构中管芯的金属走线的末端耦接至所述第一MSD结构。
15.权利要求10中的半导体封装，其中所述i-VSC通过所述i-VSC的管芯背面金属化(DBM)耦接至所述第二MSD结构。
16.权利要求15中的半导体封装，其中所述i-VSC的DBM通过所述第二MSD结构的DSP耦接至所述第二MSD结构。
17.权利要求15中的半导体封装，其中所述i-VSC的DBM通过所述第二MSD结构中管芯的金属走线的末端耦接至所述第二MSD结构。
18.权利要求10中的半导体封装，其中所述i-VSC通过所述i-VSC的一个或多个穿硅过孔(TSV)电气耦接所述第一和第二MSD结构。
19.权利要求10中的半导体封装，其中所述i-VSC通过所述i-VSC的一个或多个前端互连以及所述第一MSD结构的DSP耦接至所述第一MSD结构，所述i-VSC通过所述i-VSC的DBM以及所述第二MSD结构的DSP耦接至所述第二MSD结构，并且所述i-VSC通过所述i-VSC的一个或多个穿硅过孔(TSV)电气耦接所述第一和第二MSD结构。
20.一种半导体封装，包括：
基板；
包括半导体管芯的第一大致水平排布的第一主堆叠管芯(MSD)结构，所述第一MSD结构互连至所述基板；
包括半导体管芯的第二大致水平排布的第二MSD结构，所述第二MSD结构互连至所述基板；
置于所述第一和第二MSD结构之间，并与其电气耦接的居间垂直侧边芯片(i-VSC)，该i-VSC互连至所述基板；
一个或多个被安置成与所述第一和第二MSD结构之一或两者相邻，并与其电气耦接，但并不互连至所述基板的垂直侧边芯片(VSC)；以及
置于所述基板和所述第一及第二MSD结构之间，且置于所述基板与所述i-VSC之间，且置于所述基板与所述一个或多个VSC之间的底部填充材料。
21.权利要求20中的半导体封装，其中所述一个或多个VSC包括三个耦接至所述第一MSD结构但不耦接至所述第二MSD结构的VSC，还包括三个耦接至所述第二MSD结构但不耦接至所述第一MSD结构的VSC。
22.权利要求20中的半导体封装，其中所述一个或多个VSC包括一个耦接至所述第一MSD结构但不耦接至所述第二MSD结构的VSC，包括一个耦接至所述第二MSD结构但不耦接至所述第一MSD结构的VSC，还包括两个分别都耦接至所述第一和第二MSD结构的VSC。
23.权利要求20中的半导体封装，其中所述i-VSC通过所述i-VSC的管芯侧边焊盘(DSP)互连至所述基板。
24.权利要求20中的半导体封装，其中所述i-VSC通过所述i-VSC的一个或多个前端互连耦接到所述第一MSD结构，所述前端互连置于所述i-VSC的有源侧。
25.权利要求24中的半导体封装，其中所述i-VSC的前端互连通过所述第一MSD结构的DSP耦接至所述第一MSD结构。
26.权利要求24中的半导体封装，其中所述i-VSC的前端互连通过所述第一MSD结构中管芯的金属走线的末端耦接至所述第一MSD结构。
27.权利要求20中的半导体封装，其中所述i-VSC通过所述i-VSC的管芯背面金属化(DBM)耦接至所述第二MSD结构。
28.权利要求27中的半导体封装，其中所述i-VSC的DBM通过所述第二MSD结构的DSP耦接至所述第二MSD结构。
29.权利要求27中的半导体封装，其中所述i-VSC的DBM通过所述第二MSD结构中管芯的金属走线的末端耦接至所述第二MSD结构。
30.权利要求20中的半导体封装，其中所述i-VSC通过所述i-VSC的一个或多个穿硅过孔(TSV)电气耦接所述第一和第二MSD结构。
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