TWI483380B - 在封裝相疊設備中之堆疊晶片封裝、其組裝方法及包含該封裝的系統 - Google Patents

在封裝相疊設備中之堆疊晶片封裝、其組裝方法及包含該封裝的系統 Download PDF

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Publication number
TWI483380B
TWI483380B TW099114527A TW99114527A TWI483380B TW I483380 B TWI483380 B TW I483380B TW 099114527 A TW099114527 A TW 099114527A TW 99114527 A TW99114527 A TW 99114527A TW I483380 B TWI483380 B TW I483380B
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Taiwan
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wafer
stack
disposed
package
interconnect
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TW099114527A
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English (en)
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TW201130105A (en
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Sriram Muthukumar
Charles A Gealer
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Intel Corp
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Description

在封裝相疊設備中之堆疊晶片封裝、其組裝方法及包含該封裝的系統
所揭示的實施例係相關於半導體微電子裝置及其封裝處理。
最近行動電話及其他行動終端具有透過網路下載，例如電子郵件及遊戲的資訊之能力。因此，在所安裝記憶體中需要額外之功能及能力。典型地，多個半導體晶片被堆疊在單一封裝，以完成更大之記憶體容量。
各個方法係可用於堆疊半導體晶片。這些方法係被揭示於US2004/0084760A1、US2007/0029106A1及US2004/0229400A1案中。
 【發明內容及實施方式】
現在將參照相同結構被提供有相同的字尾參照稱號之圖式。為了更清楚圖示各種實施例的結構，此處所包括的圖式為積體電路結構的圖表輪廓表示。因此，儘管仍然包含圖解實施例的申請範圍結構，但是例如在顯微照片中之製成的結構之實際外觀可能看起來不同。而且，圖式僅圖示瞭解圖解實施例所必要的結構。未包括技藝中已知的其他結構，以維持圖式的清晰明瞭。雖然在同一句子中會提及處理器晶片和記憶體晶片，但是不應被理解作它們是同等結構。
此揭示全文所提及的“一實施例”意指連同包括在本發明的至少一實施例中之實施例所說明的特別特徵、結構、 或特性。此揭示全文各處所出現的措辭“在一實施例中”並不一定全都意指同一實施例。而且，可以任何適當方式將特別特徵、結構、或特性組合在一或多個實施例中。
參考X-Z或Y-Z座標可瞭解諸如“上”及“下”等語詞，及參考所圖解的X-Y座標可瞭解諸如“鄰接”等語詞。
圖1a為根據例示實施例之用於堆疊晶片封裝的安裝基板和互連體設備100之橫剖面正視圖。以分解圖垂直(Z方向)描繪設備100，其包括封裝基板110和互連體130。封裝基板110包括晶粒側112，用以接收處理器；和焊墊側114，用以耦合至諸如板等外部通訊。“板”可以是用於諸如無線通訊器等手持裝置的外部或接近外部結構。封裝基板110在晶粒側112上包括底晶片覆蓋區116。可藉由在圖解的安裝基板之各自晶粒側上突出圖解處理器，在此處所揭示的後續圖式中確定底晶片覆蓋區116。
封裝基板110包括焊墊側球柵陣列，以參考號碼118指示其一球墊。在實施例中，球墊118包括表面光製層120。表面光製層120被組配成較球墊118為低的陰電金屬。根據實施例由電鍍形成表面光製層120。另一選擇是，表面光製層120係由無電電鍍所形成。
在例示實施例中，球墊118為銅的，及表面光製層120為電鍍到銅上的鎳鈀金合金。在一實施例中，表面光製層120為電鍍到銅上的鎳金合金。在一實施例中，表面光製層120為電鍍到銅上的銅金合金。
在例示實施例中，球墊118為銅的，及表面光製層120為有機保焊劑(OSP)合成物，諸如芳香基苯基咪唑等。在例示實施例中，表面光製層120具有從1000Å至2000Å的 厚度，及為芳香基苯基咪唑。
同樣地，封裝基板110包括晶粒側球柵陣列，以參考號碼122指示其一球墊，及球墊122包括表面光製層124。球墊122和表面光製層124可以是類似於板側114上所發現的那些。在實施例中，晶粒側球柵陣列122係由防焊劑126來界定。同樣地，防焊劑126可界定在底晶片覆蓋區116內所發現的晶粒凸塊墊，及以參考號碼128指示其一晶粒凸塊墊。封裝基板110被描繪在晶粒側112和焊墊側114之間，具有互連及中間層介電結構(圖解說明但不具限制性)。
設備100被組裝有互連體130，互連體130接合到晶粒側球柵陣列122。互連體130包括晶粒側132和頂側134，及具有抵補高度136，此抵補高度136被組配成與將佔據底晶片覆蓋區116之用於多個晶粒堆疊(MDS)的封裝基板110上方之抵補高度138匹配。互連體130可包括核心140和互連142。在實施例中，晶粒側電凸塊144和頂側電凸塊146耦合至互連142。
圖1b為根據實施例的進一步處理之後的圖1a所描繪之設備的橫剖面正視圖。設備101圖解互連體抵補高度136與封裝基板抵補高度138匹配(圖1a)。底晶片覆蓋區116係被互連體130圍繞，及底晶片覆蓋區116將圍繞將組裝成設備101的一部分之多晶粒堆疊。
圖1c為根據實施例的進一步處理之後的圖1b所描繪之設備的橫剖面正視圖。設備102已由互連體充填材料148加固，互連體充填材料148穩定封裝基板110和互連體130之間的接合。
底晶片150被置放在底晶片覆蓋區116內(圖1b)。在 實施例中，底晶片150為透過晶片球陣列倒裝片接合地之倒裝片150，以參考號碼152指示其一電凸塊。在實施例中，已流動填膠154來加固底晶片150和封裝基板110之間的接合。在處理實施例中，在同時固化填膠154的期間完成電凸塊152的迴焊。在處理實施例中，在同時固化充填材料148的同時，完成電凸塊152的迴焊。
在一實施例中，底晶片150被處理，以迴焊電凸塊152，在凸塊迴焊之後，接著置放填膠154。
圖1d為根據實施例的進一步處理之後的圖1c所描繪之設備的橫剖面正視圖。已進一步處理圖1c所描繪之設備102來達成將成為封裝相疊(PoP)堆疊晶片設備的一部分之混合晶粒設備103。混合晶粒設備103包括已形成於底晶片150上之晶粒間黏著劑156，及頂晶片158已安裝在黏著劑156上。頂晶片158係由底晶片150所支撐。之後，源自於配置在封裝基板110上的底晶片(如晶片150)以及終止於後續晶片(如晶片158)之堆疊晶片亦可被稱作3維(3D)晶片堆疊。
在實施例中，藉由打線結合將頂晶片158耦合於封裝基板110，打線結合的其中之一係由參考號碼160指示。因此，混合堆疊設備103包括倒裝片150，其安裝在封裝基板110上；和打線結合晶片158，其配置在倒裝片150上方。互連體130的抵補高度136因此容納混合堆疊的高度，其包括打線結合160以及頂晶片158、黏著劑156、底晶片150、和電凸塊152所產生的抵補高度(圖1c所見)。
在處理實施例中，堆疊密封162已被充填，以隔離混合晶粒堆疊，以及進一步防止接合引線160移動。堆疊密封162亦可被用於保護混合晶粒堆疊免於環境和處理危險。堆疊密封162亦可被用於幫助熱移轉離開混合晶粒堆疊。在實施例中，未使用堆疊密封。
在實施例中，底晶片150為處理器，及頂晶片158為射頻(RF)裝置。混合晶粒堆疊可被用於無線通訊器(如、行動電話)，諸如智慧型電話等。
圖1e為被組裝有根據例示實施例的進一步處理之後的圖1d所描繪之設備的封裝相疊(PoP)堆疊晶片104之橫剖面正視圖。底晶片150和頂晶片158被置於互連體抵補136內，及頂封裝164已接合至互連體130的頂側134。頂封裝164可具有安裝基板170，用於到底晶片150及/或頂晶片158的通訊。頂封裝164被描繪成給打線結合之方案，諸如用於原始設備製造商等。兩打線結合晶粒被描繪在頂封裝164中。位在頂封裝164中的晶粒可被稱作微電子裝置。在一實施例中，圖1d所描繪的混合堆疊設備103被設置成容納頂封裝164，諸如用於智慧型電話等，其中智慧型電話特有微電子裝置係在頂封裝164中，及支撐微電子裝置係在晶片堆疊中。
在實施例中，頂封裝充填材料172穩定互連體130和頂封裝164之間的接合。
可看出底晶片150和頂晶片158的混合堆疊已被互連體抵補136所容納，使得頂封裝164不干擾混合堆疊。結果，PoP堆疊晶片設備被組裝有足夠的互連體抵補136，以容納可視特定應用而改變之晶片堆疊的抵補高度。
圖2a為根據例示實施例之用於堆疊晶粒封裝的安裝基板和互連體設備200之剖面視圖。設備200類似於圖1d所描繪的設備103，及已同樣藉由將互連體230安裝於封裝基板210上來處理。
描繪出堆疊晶片設備200。堆疊晶片設備200包括底晶片250和頂晶片258。在一實施例中，底晶片250為處理器，及頂晶片258為藉由矽導穿孔(TSV)技術加以耦合之記憶體晶粒。在虛線圈內詳細描繪單一TSV 274。在一實施例中，頂晶片258為二階(L2)記憶體快取(其中L0和L1係在處理器250內)，諸如用於處理器250之靜態隨機存取記憶體(SRAM)。底晶片250和頂晶片258為3D。
結果，堆疊晶片設備200包括倒裝片250，其安裝在封裝基板210上；和TSV耦合晶片258，其配置在倒裝片250上方。互連體230的抵補高度236因此容納堆疊晶片組態的高度。底晶片250的處理係可藉由揭示有關圖1c所描繪之底晶片150或別處的任何實施例來進行。
在一實施例中，頂晶片258為記憶體晶粒，諸如隨機存取記憶體(RAM)晶粒258等。在實施例中，頂晶片258為記憶體晶粒，諸如動態隨機存取記憶體(DRAM)晶粒258。在一實施例中，頂晶片258為記憶體晶粒，諸如靜態隨機存取記憶體(SRAM)晶粒258。在一實施例中，頂晶片258為記憶體晶粒，諸如可拭除可程式化記憶體(EPROM)晶粒258。根據特定應用亦可使用其他記憶體晶粒組態。
在一實施例中，頂晶片258包括射頻裝置(RF)標籤。在實施例中，頂晶片258包括用於無線通訊的射頻裝置。
在一處理實施例中，堆疊密封262已被充填，以隔離晶片堆疊。堆疊密封262亦可被用於保護晶片堆疊免於環境和處理危險。堆疊密封262亦可被用於幫助熱移轉遠離晶粒堆疊。在一實施例中，也可不使用堆疊密封。
圖2b為已從根據例示實施例的進一步處理之後的圖2a所描繪之設備加以組裝的封裝相疊(PoP)堆疊晶片201之剖面視圖。底晶片250和頂晶片258被置於互連體抵補236內，及頂封裝264已接合到互連體230的頂側234。頂封裝264可具有安裝基板270，用於連通到底晶片250及/或頂晶片258。頂封裝264被描繪成TSV賦能方案，諸如用於原始設備製造商。在實施例中，圖2a所描繪的晶片堆疊設備200被設置成容納頂封裝264，諸如用於智慧型電話等。
可看出底晶片250和頂晶片258的晶片堆疊已被互連體抵補236容納，使得頂封裝264不干擾晶片堆疊。
有關圖1e的圖解和說明之細節亦可藉由適當觀察圖2b所描繪之類似結構和空間來推斷。
現在可明白，達成PoP堆疊晶片設備201之處理可類似於達成圖1e所描繪的PoP堆疊晶片設備104之處理。
在例示實施例中，底晶片150和頂晶片158之間的I/O密度在每晶粒128位元(諸如當頂晶片258為DRAM晶粒時)和252位元/晶粒之間的範圍中。在例示實施例中，處理器250和後續晶片258之間的I/O速度在10 Gb/s和1 Tb/s(每秒兆位元)之間。沿著當作DRAM裝置之後續晶片250的10 mm邊緣區段，總頻寬從160 GB/s至320 GB/s。作為封裝，根據一實施例，PoP設備201具有640 GB/s至6400 GB/s之間的總封裝頻寬，其中處理器250和後續晶片258各個可以256位元或以上來操作。I/O速度可操作的較慢，在10 Gb/s以下(諸如7 Gb/s以下等)，其中給定應用在此範圍是有用的。
圖3a為根據一例示實施例之處理期間的混合晶粒設備300之剖面視圖。底晶片350被置放在類似於圖1c所描繪的封裝基板110之封裝基板310上。在一實施例中，底晶片350為已經由晶片球陣列倒裝片地接合的倒裝片350，以參考號碼352指示其一電凸塊。在一實施例中，已經流入填膠354來加固底晶片350和封裝基板310之間的接合。在處理實施例中，在同時固化填膠354的期間完成電凸塊352的迴焊。
底晶片350的處理係可藉由有關底晶片150、250所揭示的任何實施例或此揭示所描繪的其他實施例來進行。
圖3b為根據實施例的進一步處理之後的圖3a所描繪之設備的剖面視圖。已進一步處理圖3b所描繪之設備301來達成將成為PoP堆疊晶片設備的一部分之混合堆疊設備301。混合堆疊設備301包括已形成底晶片350上之晶粒間黏著劑356，及頂晶片358已安裝在黏著劑356上。頂晶片358係由底晶片350所支撐。
在一實施例中，藉由打線結合將頂晶片358耦合於封裝基板310，打線結合的其中之一係由參考號碼360指示。結果，混合堆疊設備301包括倒裝片350，其安裝在封裝基板310上；和打線結合晶片358，其配置在倒裝片350上方。在進一步處理中，抵補高度336將與互連體的抵補高度匹配。現在將明白，混合堆疊的組裝在組裝互連體到封裝基板310之前。
類似於圖1d所描繪之混合晶粒堆疊設備實施例，欲組裝之互連體將容納混合晶粒堆疊的高度，堆疊包括打線結合360以及頂晶片358、黏著劑356、底晶片350、及電凸塊352所產生的抵補。在一實施例中，則未使用堆疊密封。
在一實施例中，底晶片350為一處理器，及頂晶片358為RF裝置。混合晶粒堆疊可被用於無線通訊器，諸如智慧型電話等。有關先前揭示的實施例所圖解和說明之細節亦可藉由適當觀察圖3b所描繪之類似結構和空間來推斷。此外，先前揭示的I/O及頻寬容量亦可由圖3b所說明和描繪之PoP堆疊晶片實施例來推斷。
圖4為根據例示實施例之用於堆疊晶粒封裝的互連體設備400之剖面視圖。除了在組裝堆疊晶粒450及458之後完成互連體的組裝之外，設備400類似於圖2a所描繪之設備200。
描繪堆疊晶片設備400。堆疊晶片設備400包括底晶片450和頂晶片458。在一實施例中，底晶片450為一處理器，及頂晶片458為藉由矽導穿孔(TSV)技術加以耦合之記憶體晶粒。在虛線圈內詳細描繪單一TSV 474。在一實施例中，頂晶片558為二階(L2)記憶體快取(其中L0和L1係在處理器450內)，諸如用於處理器450的靜態隨機存取記憶體(SRAM)等。底晶片450的處理係可藉由揭示有關此揭示所描繪之底晶片150、250、350、及別處的任何實施例來進行。
結果，堆疊晶片設備400包括倒裝片450，其安裝在封裝基板410上；和TSV耦合晶片458，其配置在倒裝片450上方。堆疊晶片450及458的抵補高度436將與欲組裝的互連體匹配。互連體因此將容納堆疊晶片組態的高度。
在實施例中，頂晶片458為記憶體晶粒，諸如隨機存取記憶體(RAM)晶粒458。在一實施例中，頂晶片458為記憶體晶粒，諸如動態隨機存取記憶體(DRAM)晶粒458。在一實施例中，頂晶片458為記憶體晶粒，諸如靜態隨機存取記憶體(SRAM)晶粒458。在一實施例中，頂晶片458為記憶體晶粒，諸如可拭除可程式化記憶體(EPROM)晶粒458等。根據特定應用亦可使用其他記憶體晶粒組態。
在實施例中，頂晶片458包括射頻裝置(RF)標籤。在實施例中，頂晶片458包括用於無線通訊的射頻裝置。在處理實施例中，堆疊密封將被充填到互連體將形成在晶片堆疊四周的凹處內。
有關先前揭示的實施例所圖解和說明之細節亦可藉由適當觀察圖4所描繪之類似結構和空間來推斷。此外，先前揭示的I/O及頻寬容量亦可由圖4所說明和描繪之PoP堆疊晶片實施例來推斷。
圖5為根據實施例之將支撐封裝相疊設備的混合晶粒設備500之剖面視圖。混合晶粒設備500包括底晶片550、頂晶片558、和中間晶片551。頂晶片558和中間晶片551係由底晶片550所支撐。底晶片550為可被稱作第一晶片之倒裝片，中間晶片551為可被稱作第二晶片551之TSV耦合晶片，及頂晶片558為可被稱作後續晶片558之打線結合晶片。在實施例中，緊接在底晶片550上方所配置之TSV耦合晶片的數目在2至8的範圍中，接著頂晶片558。底晶片550的處理係可藉由有關此揭示所描繪的底晶片所揭示之任何實施例來進行。
在實施例中，藉由打線結合將頂晶片558耦合於封裝基板510，打線結合的其中之一係由參考號碼560指示。互連體530的抵補高度536因此容納混合堆晶粒疊的高度，其包括打線結合560以及頂晶片558、中間晶片551、底晶片550、和電凸塊以及晶片內黏著劑以及間隔物所產生的抵補，如圖解。
在處理實施例中，堆疊密封562已被充填，以隔離混合晶粒堆疊，以及進一步防止接合引線560移動。堆疊密封562亦可被用於保護混合晶粒堆疊免於環境和處理危險。堆疊密封562亦可被用於幫助熱移轉遠離混合晶粒堆疊。在一實施例中，未使用堆疊密封。
在實施例中，第一晶片550為處理器，中間晶片551為TSV RAM晶片，及頂晶片558為RF裝置。混合晶粒堆疊可被用於無線通訊器，諸如智慧型手機等。
有關先前揭示的實施例所圖解和說明之細節亦可藉由適當觀察圖5所描繪之類似結構和空間來推斷。此外，先前揭示的I/O及頻寬容量亦可由圖5所說明和描繪之PoP堆疊晶片實施例來推斷。
圖6為根據實施例之將支撐PoP混合晶粒設備的混合晶粒設備600之剖面視圖。混合晶粒設備600包括底晶片650，頂晶片659，及幾個中間晶片651、653、及658。頂晶片659和中間晶片651、653、及658係由底晶片650支撐。底晶片650的處理係可藉由揭示有關此揭示所描繪之底晶片的任何實施例來進行。
混合晶粒設備600為具有多個TSV晶片和多個打線結合晶片之實施例。底晶片650為可被稱作第一晶片之倒裝片。中間晶片651為可被稱作第二晶片651之TSV耦合晶片。中間晶片653為可被稱作第三晶片653之TSV耦合晶片。中間晶片658為可被稱作第四晶片658之打線結合晶片。及頂晶片659為可被稱作後續晶片659之打線結合晶片。在實施例中，緊接在底晶片550上方以及打線結合晶片658下方所配置之TSV耦合晶片的數目在2至8的範圍中。
在實施例中，打線結合晶片658和打線結合晶片659二者分別藉由打線結合660及661皆耦合至封裝基板610。互連體630的抵補高度636因此容納混合晶粒堆疊的高度，其包括打線結合660及661與整個晶片堆疊和電凸塊和晶片間黏著劑和間隔物，如圖解。
在處理實施例中，堆疊密封662已被充填，以隔離混合晶粒堆疊，以及進一步防止接合引線660及661移動。堆疊密封662亦可被用於保護混合晶粒堆疊免於環境和處理危險。堆疊密封662亦可被用於幫助熱移轉遠離混合晶粒堆疊。在一實施例中，未使用堆疊密封。
有關先前揭示的實施例所圖解和說明之細節亦可藉由適當觀察圖6所描繪之類似結構和空間來推斷。此外，先前揭示的I/O及頻寬容量亦可由圖6所說明和描繪之PoP堆疊晶片實施例來推斷。
圖7為根據實施例之將支撐封裝相疊設備的混合晶粒設備700之剖面視圖。混合晶粒設備700包括底晶片750、頂晶片759、及幾個中間晶片751、753、及758。頂晶片759和中間晶片751、753、及758係由底晶片750支撐。混合晶粒設備700為具有多個TSV晶片和多個打線結合晶片之實施例，其中打線結合晶片在TSV晶片下方。
底晶片750為可被稱作第一晶片之倒裝片。中間晶片751為可被稱作第二晶片751之TSV耦合晶片。中間晶片758為可被稱作第三晶片758之打線結合晶片。中間晶片753為可被稱作第四晶片753之TSV耦合晶片。及頂晶片759為可被稱作後續晶片759之打線結合晶片。在一實施例中，第二晶片751為支撐底晶片750之記憶體快取晶片。底晶片750的處理係可藉由揭示有關此揭示所描繪之底晶片的任何實施例來進行。
在一實施例中，第四晶片753為支撐後續晶片759之TSV記憶體快取晶片。在例示實施例中，混合晶粒設備700為諸如超智慧型電話等PoP堆疊晶片設備的一部分。此實施例中的底晶片750為處理器，及第二晶片751為記憶體快取。中間晶片758為用以處理線上通訊之打線結合裝置。頂晶片759為由第四晶片753所支撐的全球定位系統(GPS)晶片，第四晶片753充作用於GPS晶片759的快取記憶體。另外，在例示實施例中，頂封裝。
在一實施例中，第四晶片753被使用當作中間晶片758和頂晶片759之間的支撐和介面。例如，第四晶片753具有使頂晶片759和中間晶片758之間能夠直接通訊的TSV。
在一實施例中，打線結合晶片758和打線結合晶片759二者分別藉由打線結合760及761皆耦合至封裝基板710。互連體730的抵補高度736因此容納混合晶粒堆疊的高度，其包括打線結合760及761與整個晶片堆疊和電凸塊和晶片間黏著劑和間隔物，如圖解。
在處理實施例中，堆疊密封762已被充填，以隔離混合晶粒堆疊，以及進一步防止接合引線760及761移動。堆.疊密封762亦可被用於保護混合晶粒堆疊免於環境和處理危險。堆疊密封762亦可被用於幫助熱移轉遠離混合晶粒堆疊。在一實施例中，未使用堆疊密封。
有關先前揭示的實施例所圖解和說明之細節亦可藉由適當觀察圖6所描繪之類似結構和空間來推斷。此外，先前揭示的I/O及頻寬容量亦可由圖6所說明和描繪之PoP堆疊晶片實施例來推斷。
圖8為根據例示實施例之處理和方法流程圖800。
在810中，處理包括在封裝基板上形成互連體。互連體被組配成具有將與欲置放在封裝基板上之晶片堆疊匹配的抵補。
在820中，處理包括在封裝基板上形成晶片堆疊。處理820在處理810之前時，在形成晶片堆疊之後將互連體置放在封裝基板上。處理820在處理810之後時，晶片堆疊被形成在互連體所遺留的凹處內。在一實施例中，處理開始於810，而終止於820。
在830中，處理包括充填堆疊密封，以隔離晶片堆疊。在一實施例中，處理開始於810，而終止於830。
在840中，處理包括在互連體上形成頂封裝。在一實施例中，處理開始和終止於840。
圖9為根據實施例之電腦系統900的概要圖。如所描繪之電腦系統900(又稱作電子系統900)可利用本揭示所陳述之根據幾個揭示的實施例任一個之PoP堆疊晶片設備及其同等物。在實施例中，電子系統900是電腦系統，其包括系統匯流排920，以電耦合電子系統900的各種組件。根據各種實施例，系統匯流排920為單一匯流排或匯流排的任何組合。電子系統900包括提供電力到積體電路910之電壓源930。在一些實施例中，電壓源930經由系統匯流排920將電流供應到積體電路910。
積體電路910電耦合到系統匯流排920，及包括根據實施例之任何電路，或電路的組合。在實施例中，積體電路910包括可以是任何類型的處理器912。如此處所使用一般，處理器912可意謂任何類型的電路，諸如但並不侷限於，微處理器、微控制器、圖形處理器、數位信號處理器、或另一處理器等。在實施例中，在處理器的記憶體快取中發現SRAM實施例。可包括在積體電路910中之其他類型的電路為諸如通訊電路914等客製化電路或應用特定積體電路(ASIC)，以用於諸如行動電話、呼叫器、可攜式電腦、雙向無線電、和類似的電子系統等無線裝置。在實施例中，處理器910包括晶粒上記憶體916，諸如靜態隨機存取記憶體(SRAM)等，SRAM可包括具有存取和下拉區的獨立S/D區段之6T SRAM單元。在實施例中，處理器910包括嵌入式晶粒上記憶體916，諸如嵌入式動態隨機存取記憶體(eDRAM)等。
在實施例中，電子系統900亦包括外部記憶體940，外部記憶體940可包括適用於諸如RAM形式的主記憶體942等特定應用的一或多個記憶體元件；一或多個硬碟機944；及/或處理諸如磁盤、小型碟(CD)、數位可變碟(DVD)、快閃記憶體驅動器、及技藝中已知的其他可卸除媒體等可卸除媒體946之一或多個驅動器。外部記憶體940亦可以是嵌入式記憶體948，諸如嵌入於根據實施例之處理器安裝基板中之微電子晶粒等。
在實施例中，電子系統900亦包括顯示裝置950、聲頻輸出960。在實施例中，電子系統900包括輸入裝置，諸如可以是鍵盤、滑鼠、軌跡球、遊戲控制器、麥克風、聲音辨識裝置等控制器970，或輸入資訊到電子系統900之任何其他輸入裝置。
如此處所示一般，積體電路910可以一些不同實施例來實施，包括根據幾個揭示的實施例任一個及其同等物之PoP堆疊晶片設備、電子系統、電腦系統、製造積體電路之一或多個方法、和製造包括根據此處各種實施例中所陳述之幾個揭示的實施例任一個及其技藝認可的同等物之PoP堆疊晶片設備的電子組裝之一或多個方法。元件、材料、幾何形狀、尺寸、和操作順序都可改變，以配合特定I/O耦合要求，其包括用於嵌入在根據幾個揭示的PoP堆疊晶片設備實施例及其同等物任一個之處理器安裝基板中的微電子晶粒之陣列接觸總計、陣列接觸組態。
提供摘要以遵守37 C. F. R.§1.72(b)，其要求讓讀者能夠快速明白技術揭示的性質和主旨。應明白摘要並不用於解釋或限制申請專利範圍的範疇和意義。
在上述詳細說明中，為了簡化揭示，在單一實施例中將各種特徵群聚在一起。揭示的此方法並不應被闡釋作反映本發明申請範圍實施例需要比各個申請專利範圍所明確陳述的特徵更多的特徵之意涵。而是，如下面申請專利範圍反映一般，發明標的少於單一揭示的實施例之所有特徵。如此，下面的申請專利範圍併入到詳細說明內，各個申請專利範圍獨立成為分開的較佳實施例。
精於本技藝之人士應容易明白，只要不違背增補於後的申請專利範圍所陳述之本發明的原則和範疇，可對為了說明本發明的性質所說明和圖解之部件和方法階段的細節、材料、配置進行各種其他變化。
100．．．安裝基板和互連體設備
101．．．設備
102．．．設備
103．．．混合晶粒設備
110．．．封裝基板
112．．．晶粒側
114．．．焊墊側
116．．．底晶片覆蓋區
118．．．球墊
120．．．表面光製層
122．．．球墊
124．．．表面光製層
126．．．防焊劑
128．．．晶粒凸塊墊
130．．．互連體
132．．．晶粒側
134．．．頂側
136．．．抵補高度
138．．．抵補高度
140．．．核心
142．．．互連
144．．．晶粒側電凸塊
146．．．頂側電凸塊
148．．．互連體充填材
150．．．底晶片
152．．．電凸塊
154．．．填膠
156．．．晶粒內膠黏劑
158．．．頂晶片
160．．．打線結合
162．．．堆疊密封
164．．．頂封裝
170．．．安裝基板
172．．．頂封裝充填材料
200．．．堆疊晶片設備
201．．．封裝相疊設備
210．．．封裝設備
230．．．互連體
234．．．頂側
236．．．抵補高度
250．．．底晶片
258．．．頂晶片
262．．．堆疊密封
264．．．頂封裝
270．．．安裝基板
274．．．矽導穿孔
300．．．混合晶粒設備
301．．．混合堆疊設備
310．．．封裝基板
336．．．抵補高度
350．．．底晶片
352．．．電凸塊
354．．．填膠
356．．．晶粒內黏著劑
358．．．頂晶片
360．．．打線結合
400．．．互連體設備
410．．．封裝基板
436．．．抵補高度
450．．．底晶片
458．．．頂晶片
474．．．矽導穿孔
500．．．混合晶粒設備
510．．．封裝基板
530．．．互連體
536．．．抵補高度
550．．．底晶片
551．．．中間晶片
558．．．頂晶片
559．．．打線結合晶片
560．．．打線結合
562．．．堆疊密封
600．．．混合晶粒設備
610．．．封裝基板
630．．．互連體
636．．．抵補高度
650．．．底晶片
651．．．中間晶片
653．．．中間晶片
658．．．中間晶片
659．．．頂晶片
660．．．打線結合
661．．．打線結合
662．．．堆疊密封
700．．．混合晶粒設備
710．．．封裝基板
730．．．互連體
736．．．抵補高度
750．．．底晶片
751．．．中間晶片
753．．．中間晶片
758．．．中間晶片
759．．．頂晶片
760．．．打線結合
761．．．打線結合
762．．．堆疊密封
900．．．電腦系統
910．．．積體電路
912．．．處理器
914．．．通訊電路
916．．．晶粒上記憶體
920．．．系統匯流排
930．．．電壓源
940．．．外部記憶體
942．．．主記憶體
944．．．硬碟機
946．．．可卸除媒體
948．．．嵌入式記憶體
950．．．顯示裝置
960．．．聲頻輸出
970．．．控制器
104．．．堆疊晶片設備
為了瞭解獲得實施例之方式，參考附錄圖式將提供上面簡要說明之各種實施例更特別的說明。這些圖式描繪不一定按比例畫出且不視作侷限範圍之實施例。經由使用附圖將更具體和詳細說明和解釋一些實施例，其中：
圖1a為根據例示實施例之用於堆疊晶粒封裝的安裝基板和互連體設備之橫剖面正視圖；
圖1b為根據實施例的進一步處理之後的圖1a所描繪之設備的橫剖面正視圖；
圖1c為根據實施例的進一步處理之後的圖1b所描繪之設備的橫剖面正視圖；
圖1d為根據實施例的進一步處理之後的圖1c所描繪之設備的橫剖面正視圖；
圖1e為被組裝有根據例示實施例的進一步處理之後的圖1d所描繪之設備的封裝相疊堆疊晶片之橫剖面正視圖；
圖2a為根據例示實施例之用於堆疊晶粒封裝的安裝基板和互連體設備之橫剖面正視圖；
圖2b為已從根據例示實施例的進一步處理之後的圖2a所描繪之設備加以組裝的封裝相疊堆疊晶片之橫剖面正視圖；
圖3a為根據例示實施例的處理期間之混合晶粒設備的橫剖面正視圖；
圖3b為根據實施例的進一步處理之後的圖3a所描繪之設備的橫剖面正視圖；
圖4為根據例示實施例之用於堆疊晶粒封裝的互連體設備之橫剖面正視圖；
圖5為根據實施例之將支援封裝相疊設備的混合晶粒設備之橫剖面正視圖；
圖6為根據實施例之將支援封裝相疊混合晶粒設備的混合晶粒設備之橫剖面正視圖；
圖7為根據實施例之將支援封裝相疊設備的混合晶粒設備之橫剖面正視圖；
圖8為根據例示實施例之處理和方法流程圖；及
圖9為根據實施例之電腦系統的概要圖。
104．．．堆疊晶片設備
110．．．封裝基板
130．．．互連體
134．．．頂側
136．．．抵補高度
148．．．互連體充填材
150．．．底晶片
158．．．頂晶片
164．．．頂封裝
170．．．安裝基板
172．．．頂封裝充填材料

Claims (16)

  1. 一種封裝相疊設備，包含：封裝基板，其包括晶粒側和焊墊側；晶片堆疊，其配置在該晶粒側上，其中該晶片堆疊包括配置在該晶粒側上之包含倒裝片的底晶片、配置在該底晶片上之包含矽導穿孔(TSV)耦合晶片的第二晶片和配置在該第二晶片和該底晶片上方之包含打線結合晶片的頂晶片，該倒裝片包含矽導穿孔，其中該頂晶片係由該第二晶片和該底晶片支撐，及其中該晶片堆疊具有抵補高度；以及互連體，其配置在該晶粒側上，且圍繞該晶片堆疊，其中該互連體容納該抵補高度。
  2. 根據申請專利範圍第1項之設備，其中該互連體具有球柵陣列，該設備另外包括：頂封裝，其中該頂封裝包括至少一微電子裝置，及其中該頂封裝接合到該互連體球柵陣列。
  3. 根據申請專利範圍第1項之設備，其中該頂晶片具有寬度為大於該倒裝片之寬度。
  4. 根據申請專利範圍第1項之設備，其中該晶片堆疊包括：安裝在該基板晶粒側上之該倒裝片；包含矽導穿孔的該第二晶片，其配置在該倒裝片上；包含TSV耦合晶片的第三晶片，其配置在該第二晶片上；以及 該頂晶片為配置在該TSV第三晶片上之打線結合第四晶片。
  5. 根據申請專利範圍第1項之設備，其中該晶片堆疊包括：安裝在該基板晶粒側上之該倒裝片；包含矽導穿孔的該第二晶片，其配置在該倒裝片上；包含TSV耦合晶片的第三晶片，其配置在該第二晶片上，其中該第三晶片為範圍從1至7 TSV耦合晶片的複數個TSV耦合晶片；以及該頂晶片為配置在該第三晶片上方之打線結合後續晶片。
  6. 根據申請專利範圍第1項之設備，其中該晶片堆疊包括：安裝在該基板晶粒側上之倒裝片；包含矽導穿孔的該第二晶片，其配置在該倒裝片上；包含TSV耦合晶片的第三晶片，其配置在該TSV第二晶片上方；包含打線結合晶片的第四晶片，其配置在該TSV第二晶片上方；以及該頂晶片為配置在該第四晶片上方之打線結合後續晶片。
  7. 一種封裝相疊堆疊晶片設備，包含：封裝基板，其包括晶粒側和焊墊側；晶片堆疊，其配置在該晶粒側上，其中該晶片堆疊包 括配置在該晶粒側上之包含倒裝片的底晶片、配置在該底晶片上之包含TSV耦合晶片的第二晶片和配置在該第二晶片和該底晶片上方之包含打線結合晶片的頂晶片，該倒裝片包含矽導穿孔，其中該頂晶片係由該第二晶片和該底晶片支撐，及其中該晶片堆疊具有抵補高度；互連體，其配置在該晶粒側上，且圍繞該晶片堆疊，其中該互連體容納該抵補高度；以及頂封裝，其配置在該互連體上以及該晶片堆疊上，其中該頂封裝包括至少一微電子裝置。
  8. 根據申請專利範圍第7項之設備，其中該頂晶片具有寬度為大於該倒裝片之寬度。
  9. 根據申請專利範圍第7項之設備，其中該晶片堆疊包括：包含打線結合晶片的第三晶片，其配置在該第二晶片上；以及該頂晶片為配置在該第三晶片上方之包含打線結合晶片的第四晶片。
  10. 一種組裝封裝相疊堆疊晶片設備之方法，包含：將具有球柵陣列的頂封裝組裝至3維(3D)堆疊晶片設備的匹配球柵陣列，該3D堆疊晶片設備包括：封裝基板，其包括晶粒側和焊墊側；晶片堆疊，其配置在該晶粒側上，其中該晶片堆疊具有堆疊高度，其中該晶片堆疊係使用包括倒裝片地安裝底晶片在該基板晶粒側上、矽導穿孔(TSV)地安裝第二 晶片在該倒裝片上方和打線結合地安裝作為頂晶片的後續晶片在該第二晶片上方的方法所形成；以及互連體，其包括晶粒側和頂側，其中該互連體產生容納該堆疊高度的抵補高度，及其中組裝包括將該頂封裝接合到該互連體。
  11. 根據申請專利範圍第10項之方法，其中在組裝該互連體到該封裝基板之前，將該晶片堆疊組裝在該封裝基板上。
  12. 根據申請專利範圍第10項之方法，其中在組裝該晶片堆疊到該封裝基板之前，將該互連體組裝在該封裝基板上。
  13. 根據申請專利範圍第10項之方法，其中另外包括在該晶片堆疊上形成堆疊密封。
  14. 根據申請專利範圍第10項之方法，其中該晶片堆疊被形成包括：倒裝片地安裝底晶片在該基板晶粒側上；打線結合地安裝後續晶片在該第二晶片上方和該頂晶片下方。
  15. 一種計算系統，包含：封裝基板，其包括晶粒側和焊墊側；晶片堆疊，其配置在該晶粒側上，其中該晶片堆疊包括配置在該晶粒側上之包含倒裝片的底晶片、配置在該底晶片上之包含矽導穿孔(TSV)耦合晶片的第二晶片和配置在該第二晶片和該底晶片上方之包含打線結合晶片的頂晶 片，該倒裝片包含矽導穿孔，其中該頂晶片係由該第二晶片和該底晶片支撐，及其中該晶片堆疊具有抵補高度；互連體，其配置在該晶粒側上，且圍繞該晶片堆疊，其中該互連體容納該抵補高度；以及頂封裝，其配置在該互連體上，其中該頂封裝包括至少一微電子裝置；以及裝置外殼，其容納該頂封裝。
  16. 根據申請專利範圍第15項之計算系統，其中該計算系統為行動電話、呼叫器、可攜式電腦、桌上型電腦、和雙向無線電的其中之一的部分。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI740733B (zh) * 2020-09-30 2021-09-21 創意電子股份有限公司 半導體器件的介面及用於排列結合半導體器件的介面的方法

Families Citing this family (158)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP5714564B2 (ja) 2009-03-30 2015-05-07 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8987896B2 (en) * 2009-12-16 2015-03-24 Intel Corporation High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101678539B1 (ko) * 2010-07-21 2016-11-23 삼성전자 주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
US20120020040A1 (en) * 2010-07-26 2012-01-26 Lin Paul T Package-to-package stacking by using interposer with traces, and or standoffs and solder balls
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
TWI462200B (zh) * 2011-03-03 2014-11-21 Advanced Semiconductor Eng 半導體封裝結構及其製作方法
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
CN103748678B (zh) * 2011-08-16 2016-09-14 英特尔公司 用于大底座封装和大管芯层叠封装结构的偏移中介层
US9000577B2 (en) 2011-09-30 2015-04-07 Intel Corporation Interlayer communications for 3D integrated circuit stack
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9412689B2 (en) 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
US9691636B2 (en) * 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
US8946072B2 (en) * 2012-02-02 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. No-flow underfill for package with interposer frame
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
JP5959097B2 (ja) 2012-07-03 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US9086452B2 (en) * 2012-08-10 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit and method for wireless information access thereof
US9431064B2 (en) * 2012-11-02 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and cache circuit configuration
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US10714378B2 (en) 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US9472284B2 (en) * 2012-11-19 2016-10-18 Silicon Storage Technology, Inc. Three-dimensional flash memory system
US9704780B2 (en) * 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
US9768048B2 (en) 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure
US9484327B2 (en) 2013-03-15 2016-11-01 Qualcomm Incorporated Package-on-package structure with reduced height
CN104051411B (zh) * 2013-03-15 2018-08-28 台湾积体电路制造股份有限公司 叠层封装结构
KR20140119522A (ko) 2013-04-01 2014-10-10 삼성전자주식회사 패키지-온-패키지 구조를 갖는 반도체 패키지
US8941225B2 (en) * 2013-04-18 2015-01-27 Sts Semiconductor & Telecommunications Co., Ltd. Integrated circuit package and method for manufacturing the same
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
KR101550496B1 (ko) * 2013-07-24 2015-09-04 에스티에스반도체통신 주식회사 적층형 반도체패키지 및 그 제조방법
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9305853B2 (en) * 2013-08-30 2016-04-05 Apple Inc. Ultra fine pitch PoP coreless package
US9455211B2 (en) 2013-09-11 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with openings in buffer layer
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9018040B2 (en) 2013-09-30 2015-04-28 International Business Machines Corporation Power distribution for 3D semiconductor package
US10153180B2 (en) 2013-10-02 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bonding structures and methods
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9691693B2 (en) 2013-12-04 2017-06-27 Invensas Corporation Carrier-less silicon interposer using photo patterned polymer as substrate
EP3087599A4 (en) 2013-12-23 2017-12-13 Intel Corporation Package on package architecture and method for making
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) * 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9230936B2 (en) 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
CN106462788B (zh) * 2014-03-18 2020-07-07 惠普发展公司，有限责任合伙企业 安全元件
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9881859B2 (en) * 2014-05-09 2018-01-30 Qualcomm Incorporated Substrate block for PoP package
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
TWI660476B (zh) * 2014-07-11 2019-05-21 矽品精密工業股份有限公司 封裝結構及其製法
KR102240704B1 (ko) * 2014-07-15 2021-04-15 삼성전기주식회사 패키지 기판, 패키지 기판의 제조 방법 및 이를 이용한 적층형 패키지
KR102198858B1 (ko) 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
US10354974B2 (en) * 2014-12-11 2019-07-16 Mediatek Inc. Structure and formation method of chip package structure
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
WO2016099446A1 (en) * 2014-12-15 2016-06-23 Intel Corporation Opossum-die package-on-package apparatus
KR20160090241A (ko) * 2014-12-16 2016-07-29 인텔 코포레이션 스택형 전자 디바이스를 포함하는 전자 어셈블리
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US9418926B1 (en) * 2015-05-18 2016-08-16 Micron Technology, Inc. Package-on-package semiconductor assemblies and methods of manufacturing the same
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US20170092618A1 (en) * 2015-09-24 2017-03-30 Intel Corporation Package topside ball grid array for ultra low z-height
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
KR102372300B1 (ko) * 2015-11-26 2022-03-08 삼성전자주식회사 스택 패키지 및 그 제조 방법
US9576942B1 (en) 2015-12-18 2017-02-21 Intel Corporation Integrated circuit assembly that includes stacked dice
US10388636B2 (en) * 2015-12-21 2019-08-20 Intel Corporation Integrating system in package (SIP) with input/output (IO) board for platform miniaturization
KR102556052B1 (ko) 2015-12-23 2023-07-14 삼성전자주식회사 시스템 모듈과 이를 포함하는 모바일 컴퓨팅 장치
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9576933B1 (en) * 2016-01-06 2017-02-21 Inotera Memories, Inc. Fan-out wafer level packaging and manufacturing method thereof
KR102595276B1 (ko) * 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
CN106971993B (zh) * 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
US10177131B2 (en) * 2016-03-02 2019-01-08 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
CN106098676A (zh) * 2016-08-15 2016-11-09 黄卫东 多通道堆叠封装结构及封装方法
EP3503091A4 (en) * 2016-08-17 2019-08-07 Sony Corporation DIALOGUE CONTROL DEVICE AND METHOD
RU168167U1 (ru) * 2016-08-18 2017-01-23 Общество с ограниченной ответственностью "ТЭК электроникс" Печатная плата с массивным компонентом
US20200066701A1 (en) * 2016-09-28 2020-02-27 Intel Corporation Stacked chip package having substrate interposer and wirebonds
US10729000B2 (en) * 2016-09-28 2020-07-28 Intel Corporation Thermal conductivity for integrated circuit packaging
KR101973431B1 (ko) * 2016-09-29 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
CN110088884A (zh) * 2016-11-30 2019-08-02 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
WO2018125170A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Semiconductor package having wafer-level active die and external die mount
TWI637536B (zh) * 2017-02-24 2018-10-01 矽品精密工業股份有限公司 電子封裝結構及其製法
US20180315725A1 (en) * 2017-04-26 2018-11-01 Nanya Technology Corporation Package structure having bump with protective anti-oxidation coating
US10950535B2 (en) * 2017-05-09 2021-03-16 Unimicron Technology Corp. Package structure and method of manufacturing the same
US10685922B2 (en) 2017-05-09 2020-06-16 Unimicron Technology Corp. Package structure with structure reinforcing element and manufacturing method thereof
US10178755B2 (en) 2017-05-09 2019-01-08 Unimicron Technology Corp. Circuit board stacked structure and method for forming the same
US10714448B2 (en) 2017-05-09 2020-07-14 Unimicron Technology Corp. Chip module with porous bonding layer and stacked structure with porous bonding layer
US10757800B1 (en) 2017-06-22 2020-08-25 Flex Ltd. Stripline transmission lines with cross-hatched pattern return plane, where the striplines do not overlap any intersections in the cross-hatched pattern
KR102468765B1 (ko) * 2017-11-29 2022-11-22 삼성전자주식회사 반도체 패키지 구조체 및 이를 포함하는 반도체 모듈
US10700028B2 (en) 2018-02-09 2020-06-30 Sandisk Technologies Llc Vertical chip interposer and method of making a chip assembly containing the vertical chip interposer
KR102586794B1 (ko) 2018-06-08 2023-10-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10903155B2 (en) * 2018-06-20 2021-01-26 Intel Corporation Vertical modular stiffeners for stacked multi-device packages
US11224117B1 (en) 2018-07-05 2022-01-11 Flex Ltd. Heat transfer in the printed circuit board of an SMPS by an integrated heat exchanger
KR102568705B1 (ko) 2018-10-05 2023-08-22 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR102540829B1 (ko) 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
CN111092062B (zh) * 2018-10-24 2021-06-08 欣兴电子股份有限公司 晶片封装结构及其制造方法
US10964660B1 (en) 2018-11-20 2021-03-30 Flex Ltd. Use of adhesive films for 3D pick and place assembly of electronic components
CN111312665B (zh) * 2018-12-12 2022-02-22 欣兴电子股份有限公司 封装结构及其制造方法
US10896877B1 (en) * 2018-12-14 2021-01-19 Flex Ltd. System in package with double side mounted board
US10879260B2 (en) 2019-02-28 2020-12-29 Sandisk Technologies Llc Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same
KR102431331B1 (ko) * 2019-04-04 2022-08-11 주식회사 네패스 반도체 패키지 및 그 제조 방법
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法
JP6930793B2 (ja) * 2019-10-28 2021-09-01 Ｎｅｃスペーステクノロジー株式会社 モジュール構造およびモジュールの製造方法
US11599299B2 (en) * 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit
KR102643424B1 (ko) * 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
US11735538B2 (en) * 2020-02-17 2023-08-22 Wolfspeed, Inc. Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same
KR20210104364A (ko) * 2020-02-17 2021-08-25 삼성전자주식회사 반도체 패키지
TW202201673A (zh) * 2020-03-17 2022-01-01 新加坡商安靠科技新加坡控股私人有限公司 半導體裝置和製造半導體裝置的方法
US11715699B2 (en) 2020-03-17 2023-08-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11764179B2 (en) * 2020-08-14 2023-09-19 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US11942386B2 (en) * 2020-08-24 2024-03-26 Texas Instruments Incorporated Electronic devices in semiconductor package cavities

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175695A1 (en) * 2005-02-10 2006-08-10 Stats Chippac Ltd. Integrated circuit package system using interposer
CN1893053A (zh) * 2005-07-08 2007-01-10 三星电子株式会社 插件结构及其制造方法、晶片级堆叠结构和封装结构
TWI290365B (en) * 2002-10-15 2007-11-21 United Test Ct Inc Stacked flip-chip package

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
KR100533673B1 (ko) * 1999-09-03 2005-12-05 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
JP3854054B2 (ja) * 2000-10-10 2006-12-06 株式会社東芝 半導体装置
US20020074637A1 (en) 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies
JP2002359346A (ja) * 2001-05-30 2002-12-13 Sharp Corp 半導体装置および半導体チップの積層方法
JP4633971B2 (ja) * 2001-07-11 2011-02-16 ルネサスエレクトロニクス株式会社 半導体装置
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
TW546795B (en) * 2002-06-04 2003-08-11 Siliconware Precision Industries Co Ltd Multichip module and manufacturing method thereof
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP2004273706A (ja) * 2003-03-07 2004-09-30 Sony Corp 電子回路装置
KR20050112122A (ko) * 2003-04-07 2005-11-29 이비덴 가부시키가이샤 다층프린트배선판
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
JP3939707B2 (ja) * 2004-03-29 2007-07-04 シャープ株式会社 樹脂封止型半導体パッケージおよびその製造方法
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
KR100639701B1 (ko) 2004-11-17 2006-10-30 삼성전자주식회사 멀티칩 패키지
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
US7429786B2 (en) 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
JP4322844B2 (ja) * 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
KR100661297B1 (ko) * 2005-09-14 2006-12-26 삼성전기주식회사 리지드-플렉시블 패키지 온 패키지용 인쇄회로기판 및 그제조방법
JP2007123705A (ja) * 2005-10-31 2007-05-17 Elpida Memory Inc 積層型半導体装置及びその製造方法
KR100697553B1 (ko) * 2005-12-19 2007-03-21 삼성전자주식회사 멀티 스택 패키지 및 이의 제조 방법
JP4753725B2 (ja) 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
KR100836663B1 (ko) * 2006-02-16 2008-06-10 삼성전기주식회사 캐비티가 형성된 패키지 온 패키지 및 그 제조 방법
JP2007234881A (ja) * 2006-03-01 2007-09-13 Oki Electric Ind Co Ltd 半導体チップを積層した半導体装置及びその製造方法
DE102006033702B3 (de) * 2006-07-20 2007-12-20 Infineon Technologies Ag Herstellungsverfahren für eine elektronische Schaltung in einer Package-on-Package-Konfiguration und elektronisches Bauelement in einer solchen Konfiguration
KR100809696B1 (ko) * 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
KR100817075B1 (ko) * 2006-11-09 2008-03-26 삼성전자주식회사 멀티스택 패키지 및 그 제조 방법
KR100843214B1 (ko) * 2006-12-05 2008-07-02 삼성전자주식회사 메모리 칩과 프로세서 칩이 관통전극을 통해 연결된 플래너멀티 반도체 칩 패키지 및 그 제조방법
JP2008166527A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
KR101332861B1 (ko) * 2007-01-03 2013-11-22 삼성전자주식회사 아이씨 패키지 및 그 제조방법
US7829990B1 (en) * 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
RU2335822C1 (ru) * 2007-01-25 2008-10-10 Закрытое акционерное общество "Научно-производственное объединение "НИИТАЛ" Многокристальный модуль
US20080258286A1 (en) * 2007-04-23 2008-10-23 Texas Instruments Incorporated High Input/Output, Low Profile Package-On-Package Semiconductor System
KR100923562B1 (ko) * 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US8852986B2 (en) 2007-05-16 2014-10-07 Stats Chippac Ltd. Integrated circuit package system employing resilient member mold system technology
US7872356B2 (en) 2007-05-16 2011-01-18 Qualcomm Incorporated Die stacking system and method
US7888798B2 (en) 2007-05-16 2011-02-15 Samsung Electronics Co., Ltd. Semiconductor devices including interlayer conductive contacts and methods of forming the same
US7635914B2 (en) * 2007-05-17 2009-12-22 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
US7824960B2 (en) * 2007-05-22 2010-11-02 United Test And Assembly Center Ltd. Method of assembling a silicon stack semiconductor package
US7841080B2 (en) * 2007-05-30 2010-11-30 Intel Corporation Multi-chip packaging using an interposer with through-vias
US8586465B2 (en) * 2007-06-07 2013-11-19 United Test And Assembly Center Ltd Through silicon via dies and packages
KR100871381B1 (ko) 2007-06-20 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 칩 스택 패키지
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7800212B2 (en) * 2007-12-27 2010-09-21 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
US8334170B2 (en) * 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
US9818680B2 (en) * 2011-07-27 2017-11-14 Broadpak Corporation Scalable semiconductor interposer integration
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI290365B (en) * 2002-10-15 2007-11-21 United Test Ct Inc Stacked flip-chip package
US20060175695A1 (en) * 2005-02-10 2006-08-10 Stats Chippac Ltd. Integrated circuit package system using interposer
CN1893053A (zh) * 2005-07-08 2007-01-10 三星电子株式会社 插件结构及其制造方法、晶片级堆叠结构和封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI740733B (zh) * 2020-09-30 2021-09-21 創意電子股份有限公司 半導體器件的介面及用於排列結合半導體器件的介面的方法

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