CN103748678B - 用于大底座封装和大管芯层叠封装结构的偏移中介层 - Google Patents

用于大底座封装和大管芯层叠封装结构的偏移中介层 Download PDF

Info

Publication number
CN103748678B
CN103748678B CN201180072839.0A CN201180072839A CN103748678B CN 103748678 B CN103748678 B CN 103748678B CN 201180072839 A CN201180072839 A CN 201180072839A CN 103748678 B CN103748678 B CN 103748678B
Authority
CN
China
Prior art keywords
pop
weld pad
land side
bga
spacing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180072839.0A
Other languages
English (en)
Other versions
CN103748678A (zh
Inventor
R·莫腾森
R·尼克森
N·沃茨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN103748678A publication Critical patent/CN103748678A/zh
Application granted granted Critical
Publication of CN103748678B publication Critical patent/CN103748678B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1511—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

一种偏移中介层包括：焊盘侧，其包括焊盘侧球栅阵列（BGA）；以及层叠封装（POP）侧，其包括POP侧BGA。焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，并且POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其通过该偏移中介层耦接到相应的两个焊盘侧BGA。焊盘侧BGA被配置为与第一级互连相连接。POP侧BGA被配置为与POP基板相连接。两个焊盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹。

Description

用于大底座封装和大管芯层叠封装结构的偏移中介层
技术领域
所公开的实施例涉及层叠封装中介层。
附图说明
为了理解获得实施例的方式，将参考附图来呈现上面简要描述的各种实施例的更具体的描述。这些附图描绘了不一定按比例绘制的实施例，并且不应该被认为是对范围的限制。将通过使用附图以附加特征和细节来描述和解释一些实施例，在附图中：
图1a是根据示例实施例的偏移中介层的截面正视图；
图1b是根据示例实施例的被置于第一级互连上的偏移中介层的截面正视图；
图2是根据示例实施例的在图1a中描绘的偏移中介层的俯视图；
图3是根据示例实施例的偏移中介层的截面正视图；
图4是根据示例实施例的具有偏移中介层的芯片封装的截面正视图；
图5是根据示例实施例的在图4中描绘的偏移中介层的俯视剖面图；
图6a是根据示例实施例的具有偏移中介层的芯片封装的截面正视图；
图6b是根据示例实施例的具有偏移中介层的芯片封装的截面正视图；
图7是根据示例实施例的具有偏移中介层的芯片封装的截面正视图；
图8是根据示例实施例的具有偏移中介层的芯片封装的截面正视图；
图9是根据示例实施例的过程和方法的流程图；以及
图10是根据示例实施例的计算机系统的示意图。
具体实施方式
公开了偏移中介层（offset interposer）与微电子设备组装和耦接为芯片封装的过程。偏移中介层实施例允许芯片封装设计者在封装过程中减轻诸如逻辑器件和存储器件之间的连接任务。
现在将参考附图，在附图中可以给相似的结构提供相似的后缀参考标记。为了更清楚地示出各个实施例的结构，本文中包括的附图是组装到偏移中介层实施例的集成电路芯片的示意图表示。因此，所制造的芯片基板（不管是单独的还是在芯片封装中的）的实际外观，例如在显微照片中，可能会显示的不同，但仍然纳入所示实施例的所要求保护的结构。此外，附图可能仅示出了对理解图示的实施例有用的结构。为了保持附图的清晰，可能没有包括本领域中已知的额外结构。
图1a是根据示例实施例的偏移中介层100的横截面正视图。偏移中介层100包括中央通孔108（也被称为内边缘108），提供该中央通孔是为了允许第一级设备（例如处理器）的间隙。类似地，中介层侧边缘106（也被称为外边缘106）定义偏移中介层100的外侧表面和周界。
偏移中介层100还包括焊盘侧（land-side）112，焊盘侧112被配置成与第一级互连（例如处理器的封装）连接。与焊盘侧112相对的是层叠封装（POP）侧110，诸如存储器模块之类的POP结构被组装到层叠封装侧110上。
两个相邻的、分隔开的焊盘侧焊垫114和116（在横截面中使用每一侧出现两次来指示）置于焊盘侧112上。焊盘侧焊垫114和116是被配置为与第一级互连连接的焊盘侧球栅阵列（BGA）的一部分。类似地，两个相邻的、分隔开的POP侧焊垫118和120（在横截面中使用每一侧出现两次来指示）置于POP侧110上。可以看到，对于两个焊盘侧焊垫114和116来说，它们具有与两个POP侧焊垫118和120不同的X-Y朝向（其中Y方向与该图的平面正交）。这意味着虽然POP侧焊垫118和120通过中介层耦接到相应的焊盘侧焊垫114和116，但是它们在X或Y方向中的至少一个方向上（在这些图示的实施例中，是在X方向上）是偏移的或“平移的”。
给定的POP侧焊垫118通过第一迹线124和有用的过孔125耦接到给定的焊盘侧焊垫114。类似地，给定的相邻的且分隔开的POP侧焊垫120通过第二迹线126和有用的过孔127耦接到相应的给定的焊盘侧焊垫116。
在偏移中介层100上如其右侧所指示的，焊盘侧焊垫间距128和POP侧焊垫间距130定义了相应侧的焊垫中心到中心间距。在一个实施例中，焊盘侧焊垫间距128被配置为与连接常规的第一级球栅阵列（BGA）互连的常规的焊垫间距相匹配。在一个实施例中，POP侧焊垫间距130等于焊盘侧焊垫间距128。在一个实施例中，POP侧焊垫间距130为0.5mm。在一个实施例中，焊盘侧焊垫间距128为0.5mm。在一个实施例中，POP侧焊垫间距130为0.5mm，并且焊盘侧焊垫间距128小于0.5mm。在一个实施例中，POP侧焊垫间距130为单位距离，并且焊盘侧焊垫间距128小于单位距离（例如为单位距离的80%）。在一个实施例中，POP侧焊垫间距130为0.5mm，并且焊盘侧焊垫间距128为0.4mm。
POP侧焊垫118和120分别相对于焊盘侧焊垫114和116在X方向偏移或平移。如图所示，焊盘侧焊垫114和116具有焊盘侧的周界特征尺寸134，并且POP侧焊垫118和120具有POP侧的周界特征尺寸132。在该实施例中看到，焊盘侧的周界特征尺寸134大于POP侧的周界特征尺寸134。当在俯视图（见图2）中观察时，POP侧焊垫以小于焊盘侧焊垫的周界但与之同心的周界进行排列。
在一个实施例中，POP侧焊垫118和120的偏移使得POP侧的周界特征尺寸132小于焊盘侧的周界特征尺寸134，从而使得迹线124和126的X长度小于图1a中所描绘的。在一个实施例中，POP侧焊垫118和120的偏移使得POP侧的周界特征尺寸132小于焊盘侧的周界特征尺寸134，从而使得不需要图1a中所描绘的迹线124和126。例如，当不需要迹线124时，POP侧焊垫118的足迹（footprint）与焊盘侧焊垫114的足迹重叠。过孔125通过中介层100借由直接接触来对两个相应的焊垫118和114进行互连（见图3）。换句话说，POP侧焊垫118具有与其相应的焊盘侧焊垫114不同的足迹。类似地，例如，当不需要迹线126时，POP侧焊垫120的足迹与焊盘侧焊垫116的足迹重叠，并且过孔127通过中介层100借由直接接触来对两个相应的焊垫120和116进行互连。
图2是根据示例实施例的在图1a中描绘的偏移中介层100的俯视图。用虚线来指示间隔开的但相邻的焊盘侧焊垫114和116中的每一个的两次出现，这是因为它们在POP侧栅格阵列（LGA）中在POP侧110的下面。类似地，间隔开但相邻的POP侧焊垫118和120中的每一个的两次出现被指示在焊盘侧BGA中置于POP侧110上。
如同在剖面线1a处所看到的，POP侧焊垫118和120分别相对于焊盘侧焊垫114和116在X方向进行了偏移。如图所示，焊盘侧焊垫114和116具有焊盘侧的周界特征尺寸134，并且POP侧焊垫118和120具有POP侧的周界特征尺寸132。在该实施例中看到，焊盘侧的周界特征尺寸134大于POP侧的周界特征尺寸134。还可以看到，没有发生POP侧焊垫118和120与焊盘侧焊垫114和116的足迹重叠。然而，在一个实施例中，发生了POP侧焊垫118和120与焊盘侧焊垫114和116的某些足迹重叠（参见图3）。
因为在耦接到焊盘侧焊垫的POP侧焊垫之间可能存在一一对应的关系，所以可能出现若干虚的焊盘侧焊垫，然而这些虚的焊盘侧焊垫可能用于增加的热和物理冲击增强以及用于额外的功率和/或地电流。作为图示的实施例，在POP侧110上描绘了56个POP侧焊垫，但是当中心到中心距和焊垫尺寸在POP侧110与焊盘侧112之间相匹配时，多达88个焊盘侧焊垫位于焊盘侧112上。
图1b是根据示例实施例的具有偏移中介层100的芯片封装101的截面正视图。图1a中示出的偏移中介层100被描绘为安装在第一级互连136（诸如电子设备138的安装基板）上。由于POP侧的周界特征尺寸132小于焊盘侧的特征尺寸134，因此第一级互连136可以被称为大底座封装。
在一个实施例中，电子设备138是处理器（诸如由加利福尼亚州圣克拉拉的英特尔公司制造的处理器）。在一个实施例中，处理器是Atom处理器。在一个实施例中，处理器是来自英特尔公司的代号为PenwellTM的类型。电子设备138以倒装芯片的方式安装到第一级互连136上，并且其具有活动表面140和背面表面142。第一级互连136上的芯片的其它配置可以包括丝焊芯片，其活动表面背向第一级互连136。第一级互连136还被配置为：通过电阵列（诸如使用若干电凸块146示出的球栅阵列）与基本基板144（诸如智能电话主板）通信。用于连接第一级互连的其它方式包括代替电凸块的焊盘栅格阵列。
偏移中介层100通过与图1a和图2中描绘的焊盘侧焊垫114和116相对应的一系列电凸块115和117耦接到第一级互连136。电凸块115和117被置于焊盘侧112上。类似地，一系列电凸块119和121被置于POP侧110上。所述一系列电凸块119和121分别与图1a和图2中描绘的POP侧焊垫118和120相对应。所述一系列电凸块119和121是POP侧的互连。出于说明的目的描述了电凸块119和121，这是因为它们可能是POP封装的一部分，从而使得POP侧焊垫118和120是POP LGA的一部分。
因为偏移中介层100的平移效果，可以保持底部填充材料152的有用的排除区域（KOZ）150，并且较大的逻辑管芯138具有有用的底部填充量，而所述一系列凸块115和117仍然被保护免于受到底部填充材料152的污染。
在一个实施例中，芯片封装101被组装到具有智能电话形式因子的计算系统。在一个实施例中，芯片封装101被组装到具有平板形式因子的计算系统。
图3是根据示例实施例的偏移中介层300的截面正视图。偏移中介层300包括中央通孔308，提供该中央通孔以便为第一级设备（例如处理器）提供间隙。类似地，中介层侧边缘306定义偏移中介层300的外侧表面。偏移中介层300还包括焊盘侧312，焊盘侧312被配置成与第一级互连（诸如处理器的封装）连接。与焊盘侧312相对的是POP侧310。
两个相邻的、间隔开的焊盘侧焊垫314和316置于焊盘侧312上。类似地，两个相邻的、间隔开的POP侧焊垫318和320置于POP侧310上。给定的POP侧焊垫318通过有用的过孔325耦接到给定的焊盘侧焊垫314。类似地，给定的相邻且分隔开的POP侧焊垫320通过有用的过孔327耦接到相应的给定的焊盘侧焊垫316。
在偏移中介层300上如同其右侧所指示的，焊盘侧焊垫间距328和POP侧焊垫间距330定义了相应侧的中心到中心焊垫间距。在一个实施例中，焊盘侧焊垫间距328被配置为与连接常规的第一级互连的常规的焊垫间距相匹配。在一个实施例中，POP侧焊垫间距330等于焊盘侧焊垫间距328。在一个实施例中，POP侧焊垫间距330为0.5mm。在一个实施例中，焊盘侧焊垫间距328为0.5mm。在一个实施例中，POP侧焊垫间距330为0.5mm，并且焊盘侧焊垫间距328小于0.5mm。在一个实施例中，POP侧焊垫间距330为单位距离，并且焊盘侧焊垫间距328小于单位距离（例如为单位距离的80%）。在一个实施例中，POP侧焊垫间距330为0.5mm，并且焊盘侧焊垫间距328为0.4mm。
POP侧焊垫318和320分别相对于焊盘侧焊垫314和316在X方向上进行了偏移或平移。如图所示，焊盘侧焊垫314和316具有焊盘侧的周界特征尺寸334，并且POP侧焊垫318和320具有POP侧的周界特征尺寸332。在该实施例中看到，焊盘侧的周界特征尺寸334大于POP侧的周界特征尺寸334。当在俯视图中观察时，POP侧焊垫以小于焊盘侧焊垫的周界但与之同心的周界进行排列。
如同根据实施例所示出的，POP侧焊垫318和320的偏移使得POP侧的周界特征尺寸332小于焊盘侧的周界特征尺寸334，从而使得不需要图1a中所描绘的迹线124和126。例如，POP侧焊垫318的足迹与焊盘侧焊垫314的足迹（当在Z方向上投影时在X方向上）重叠，并且过孔325通过直接接触来对两个相应的焊垫318和314进行互连。类似地，例如，POP侧焊垫320的足迹与焊盘侧焊垫316的足迹重叠，并且过孔327通过直接接触来对两个相应的焊垫320和318进行互连。在一个实施例中，POP侧焊垫与焊盘侧焊垫的重叠是百分之百的。在一个实施例中，POP侧焊垫与焊盘侧焊垫的重叠的范围从百分之一到小于百分之百。在一个实施例中，POP侧焊垫与焊盘侧焊垫的重叠小于百分之50。图3中示出了该实施例。在一个实施例中，POP侧焊垫与焊盘侧焊垫的重叠大于百分之50。现在可以明白的是，一个实施例包括POP侧焊垫114和116的X-Y足迹不包括两个相应的焊盘侧焊垫118和120的X-Y足迹投影。这意味着任何POP侧焊垫的X-Y足迹与其焊盘侧焊垫的投影没有重叠。可以在图1a和图2中看到该实施例。
现在可以明白的是，与由焊盘侧的周界特征尺寸134定义的周界相比，由POP侧的周界特征尺寸132定义的周界更接近内边缘108。如图所示，与POP侧的周界特征尺寸132相比，焊盘侧的周界特征尺寸134更接近外边缘106。在一个实施例中，两个特征尺寸132和134是相同的。在所有其它的实施例中，焊盘侧的周界特征尺寸134更接近外边缘106，并且POP侧的周界特征尺寸132更接近内边缘108。
图4是根据示例实施例的具有偏移中介层400的芯片封装401的截面正视图。在一个实施例中，芯片封装401被组装到具有平板形式因子的计算系统。在一个实施例中，芯片封装401被组装到具有智能电话形式因子的计算系统。
图4中示出的偏移中介层400被描绘为安装在第一级互连436（诸如电设备438的安装基板）上。电子设备438以倒装芯片的方式安装到第一级互连436上，并且其具有活动表面440和背面表面442。第一级互连436上的芯片的其它配置可以包括丝焊芯片，其活动表面背向第一级互连436。第一级互连436还被配置为与基本基板（诸如图1a中描绘的基本基板144）通信。基本基板可以是通过电阵列（诸如使用几个电凸块446示出的球栅阵列）通信的平板主板。
偏移中介层400通过与焊盘侧表面410上的焊盘侧焊垫相对应的一系列电凸块415和417耦接到第一级互连436。电凸块415和417置于焊盘侧412上。类似地，一系列电凸块419、421和453置于POP侧410上。出于说明的目的描述了电凸块419、421和453，这是因为它们可能是POP封装的一部分，从而使得POP侧焊垫（诸如图1a中描绘的POP侧焊垫118和120）是POP LGA的一部分。
根据一个实施例，在剖面图的左侧看到三个电凸块419、421和453，但是在其右侧，在该剖面图中仅看到两个电凸块419和421。对图示的实施例进一步说明，POP侧焊垫间距430大于焊盘侧焊垫间距428。在焊盘侧412和POP侧410二者上，凸块计数可以是相同的，然而，由于焊盘侧间距428较小，这允许焊盘侧412上的凸块阵列比POP侧410上的凸块阵列更密集。在一个示例实施例中，POP侧410上的凸块计数与焊盘侧412上的凸块计数是相同的。在一个示例实施例中，焊盘侧412上的凸块计数是88，并且其在POP侧410上与在焊盘侧412上是相同的。
在一个实施例中，POP侧的凸块419、421和453容纳具有与偏移中介层400相同的X-Y维度的POP封装（没有示出，例如参见图6、7和8）。然而，区别在于：与电连接的焊盘侧的凸块415和417相比，POP侧410上的电连接的POP侧凸块419、421和453以较大的间隙设置。
在偏移中介层400上如同其左侧所指示的，焊盘侧焊垫间距428和POP侧焊垫间距430定义了相应侧的焊垫间距。在一个实施例中，POP侧焊垫间距430为0.5mm，并且焊盘侧焊垫间距428为0.4mm。在本公开内容中阐述的其它相当的POP到焊盘侧焊垫间距实施例可以应用于该实例。
在一个实施例中，焊盘侧焊垫间距428被配置为与连接常规的第一级互连的常规的焊垫间距相匹配。在一个实施例中，POP侧焊垫间距430等于焊盘侧焊垫间距428。在一个实施例中，POP侧焊垫间距430为0.5mm。在一个实施例中，焊盘侧焊垫间距428为0.5mm。在一个实施例中，POP侧焊垫间距430为0.5mm，并且焊盘侧焊垫间距428小于0.5mm。在一个实施例中，POP侧焊垫间距430为单位距离，并且焊盘侧焊垫间距428小于单位距离（例如为单位距离的80%）。
现在可以明白的是，偏移中介层400可以具有容纳两凸块的电连接行的焊盘侧焊垫，而POP侧焊垫容纳三凸块的电连接行。在示例实施例中，通过使用被配置为两凸块的电连接行的更紧间隙焊盘侧凸块415和417阵列，使将要安装到POP凸块419、421和453上的存储器模块容纳并且适于较大的逻辑管芯438。在一个实施例中，芯片封装401被组装到具有平板形式因子的计算系统。
图5是根据示例实施例的在图4中描绘的偏移中介层400的俯视剖面图500。在剖面线4处示出了图4中描绘的偏移中介层400。当沿X方向从左向右看时，可以看到在左侧，一系列电凸块419、421和453混合成具有三个凸块的行，其位于交替的具有两个凸块的行之间。类似地，根据一个实施例，在右侧，一系列电凸块419和421混合成具有两个凸块的行，其位于交替的具有三个凸块的行之间。在一个实施例中，可以混合和匹配两凸块的行、三凸块的行的配置。可以看到，在底部右侧，两个三凸块的行间隔开并且彼此相邻。
如图所示，一系列电凸块419、421、453（以及从左到右连续）421和419有助于定义POP侧的周界特征尺寸432。
图6a是根据示例实施例的具有偏移中介层600的芯片封装601的截面正视图。图6中示出的偏移中介层600被描绘为安装在第一级互连636（诸如电设备638的安装基板）上。根据本公开内容中阐述的实施例中的任意一个，第一级互连636也被描绘为安装在基本基板644上。电子设备638以倒装芯片的方式安装在第一级互连636上。
POP基板654安装在偏移中介层600的POP侧上的电凸块上。POP基板654被描绘为具有诸如存储器管芯656之类的POP设备658。
现在可以明白的是，偏移中介层600可以具有容纳例如第一级互连636上的12x12mm大小的焊接点（landing）的焊盘侧焊垫，并且POP侧焊垫容纳小于12x12大小示例的POP基板654。因此，当偏移中介层600在第一级互连636上的足迹是例如12x12mm时，并且当POP设备656较小时，偏移中介层600容纳较小尺寸的POP设备656，而不破坏可能是中介层600在第一级互连636上的足迹的有用的12x12mm尺寸。
现在可以明白的是，偏移中介层600可以具有容纳给定的电子设备638所需要的例如14x14mm大小的焊接点的焊盘侧焊垫，同时第一级互连636上的焊接点的尺寸需要是14x14mm，POP侧焊垫容纳较小但可能有用的POP基板654，例如，12x12mm的足迹。在示例实施例中，需要较大的处理器638，但是POP基板654具有偏移中介层600上的12x12mm的足迹。现在可以明白的是，所有相当的焊垫盘间距的实施例可以应用到该实例。
图6b是根据示例实施例的具有偏移中介层400的芯片封装603的截面正视图。图6中示出的偏移中介层400被描绘为安装在第一级互连636（诸如电子设备638的安装基板）上。根据本公开内容中阐述的实施例中的任意一个，第一级互连636也被描绘为安装在基本基板644上。电子设备638以倒装芯片的方式安装在第一级互连636上。
POP基板654安装在偏移中介层600的POP侧上的电凸块上。POP基板654被描绘为具有诸如存储器管芯656之类的POP设备658。
现在可以明白的是，偏移中介层400和POP基板654可以具有类似的X-Y形式因子。现在可以明白的是，所有相当的焊垫间距的实施例可以应用到该实例。
图7是根据示例实施例的具有偏移中介层700的芯片封装701的截面正视图。图7中示出的偏移中介层700被描绘为安装在第一级互连736（诸如电子设备738的安装基板）上。根据本公开内容中阐述的实施例中的任意一个，第一级互连736也被描绘为安装在基本基板744上。电子设备738以倒装芯片的方式安装在第一级互连736上。根据一个实施例，堆叠管芯758安装在电子设备738上。堆叠管芯754是通过芯片封装701中描绘的第一级互连736与其它设备进行电通信的丝焊设备。
POP基板754安装在偏移中介层700的POP侧上的电凸块上。POP基板754被描绘为具有诸如存储器管芯756之类的POP设备。在一个实施例中，堆叠设备758是射频（RF）管芯，并且POP设备756是存储器管芯。
现在可以明白的是，偏移中介层700可以具有容纳例如第一级互连736上的12x12mm大小的焊接点的焊盘侧焊垫，并且POP侧焊垫容纳小于12x12尺寸示例的POP基板754，但是在第一级互连636与POP基板754之间提供了足够的间隙以容纳电子设备738和堆叠管芯758二者。因此，当偏移中介层700在第一级互连736上的足迹是例如12x12mm时，并且当POP设备756较小时，偏移中介层700容纳较小尺寸的POP设备756，而不破坏可能是中介层700在第一级互连736上的足迹的有用的尺寸。
现在可以明白的是，偏移中介层700可以具有容纳给定的电子设备738所需要的例如14x14mm大小的焊接点的焊盘侧焊垫，同时第一级互连736上的焊接点的尺寸需要是14x14mm，POP侧焊垫容纳较小但可能有用的POP基板754，例如，12x12mm大小的足迹。在示例实施例中，需要较大的处理器738，但是POP基板754在偏移中介层700上具有12x12mm大小的足迹。现在可以明白的是，所有相当的焊垫间距的实施例可以应用到该实例。
现在可以明白的是，诸如图4中描绘的偏移中介层400之类的偏移中介层可以用在图7中来替代偏移中介层700，其中，三球计数行配置从POP侧转换成焊盘侧上的两球计数行配置。
图8是根据示例实施例的具有偏移中介层800的芯片封装801的截面正视图。图8中示出的偏移中介层800被描绘为安装在第一级互连836（诸如电设备838的安装基板）上。根据本公开内容中阐述的实施例中的任意一个，第一级互连836也被描绘为安装在基本基板844上。电子设备838以倒装芯片的方式安装在第一级互连836上。根据一个实施例，电子设备838被描绘为硅通（管芯通）孔（TSV）839设备838，并且堆叠管芯858以倒装芯片的方式安装在TSV电子设备838上。堆叠管芯854是经由芯片封装801中描绘的TSV839通过第一级互连836与其它设备进行电通信的倒装芯片设备。
POP基板854安装在偏移中介层800的POP侧上的电凸块上。POP基板854被描绘为具有诸如存储器管芯756之类的POP设备。在一个实施例中，堆叠设备858是存储器管芯，并且POP设备856是丝焊RF设备856。
现在可以明白的是，偏移中介层800可以具有容纳例如第一级互连836上的12x12mm大小的焊接点的焊盘侧焊垫，并且POP侧焊垫容纳小于12x12尺寸示例的POP基板854，但是在第一级互连836与POP基板854之间提供了足够的间隙以容纳TSV电子设备838和堆叠管芯858二者。因此，当偏移中介层800在第一级互连836上的足迹是例如12x12mm时，并且当POP设备856较小时，偏移中介层800容纳较小尺寸的POP设备856，而不破坏可能是中介层800在第一级互连836上的足迹的有用的尺寸。
现在可以明白的是，偏移中介层800可以具有容纳给定的TSV电子设备838所需要的例如14x14mm大小的焊接点的焊盘侧焊垫，同时第一级互连836上的焊接点的尺寸需要是14x14mm，POP侧焊垫容纳的POP基板854较小但可能是有用的12x12mm足迹。在示例实施例中，需要较大的TSV处理器838，但是POP基板854在偏移中介层800上具有12x12mm的足迹。现在可以明白的是，所有相当的焊垫间距的实施例可以应用到该实例。
现在可以明白的是，诸如图4中描绘的偏移中介层400之类的偏移中介层可以用在图8中以替代偏移中介层800，其中，三球计数行配置从POP侧转换成焊盘侧上的两球计数行配置。
图9是根据示例实施例的过程和方法的流程图。
在910处，过程实施例包括：形成偏移中介层。偏移中介层由已知技术来构造以实现几个公开的实施例。例如，偏移中介层的形成包括：当将POP侧焊垫布局与焊盘侧焊垫布局进行比较时，使用有用的平移焊垫配置将迹线和BGA焊垫层压到核心上。
在912处，构造偏移中介层的实施例包括：使POP侧的球焊垫间距（pitch）与焊盘侧的球焊垫间距相同。现在可以理解的是：一侧上的球焊垫间距与另一侧相比可以不同。
在914处，构造偏移中介层的实施例包括：使POP侧焊垫与焊盘侧焊垫重叠。在非限制性的示例实施例中，POP侧焊垫318和320分别与其相对应的焊盘侧焊垫314和316重叠。
在915处，构造偏移中介层的实施例包括：通过仅与过孔直接接触将POP侧焊垫与其相对应的焊盘侧焊垫耦接。
在920处，将偏移中介层组装到第一级互连的方法包括：使焊盘侧焊垫与置于第一级互连上的电凸块配对。
在930处，方法实施例包括：将偏移中介层组装到POP基板。
在940处，方法实施例包括：将偏移中介层组装到计算系统。
图10是根据实施例的计算机系统的示意图。所描绘的计算机系统1000（也被称为电子系统1000）可以根据在本公开内容中阐述的几个所公开的实施例及其等同形式中的任意一种来实现偏移中介层。一种包括被组装到计算机系统的偏移中介层的装置。计算机系统1000可以是智能电话。计算机系统1000可以是平板电脑。计算机系统1000可以是诸如上网本计算机之类的移动设备。计算机系统1000可以是台式计算机。计算机系统1000可以是汽车的组成部分。计算机系统1000可以是电视机的组成部分。计算机系统1000可以是DVD播放器的组成部分。计算机系统1000可以是数码摄像机的组成部分。
在一个实施例中，电子系统1000是计算机系统，其包括系统总线1020以便电耦接电子系统1000的各个组件。根据各个实施例，系统总线1020是单个总线或总线的任意组合。电子系统1000包括向集成电路1010提供功率的电压源1030。在一些实施例中，电压源1030通过系统总线1020向集成电路1010提供电流。
根据实施例，集成电路1010电耦接到系统总线1020，并且包括任意电路或电路的组合。在一个实施例中，集成电路1010包括处理器1012，处理器1012可以是包括偏移中介层实施例的任何类型的装置。如本文中所使用的，处理器1012可以是指任何类型的电路，例如但不限于微处理器、微控制器、图形处理器、数字信号处理器或其它处理器。在一个实施例中，在处理器1012的存储器高速缓存中发现SRAM实施例。可以包括在集成电路1010中的其它类型的电路是定制电路或专用集成电路（ASIC），例如用于非等同无线设备（诸如蜂窝电话、智能电话、寻呼机、便携式计算机、双向无线电和其它电子系统）的通信电路1014。在一个实施例中，处理器1010包括诸如静态随机存取存储器（SRAM）之类的管芯上存储器1016。在一个实施例中，处理器1010包括诸如嵌入式动态随机存取存储器（eSRAM）之类的嵌入式管芯上存储器1016。
在一个实施例中，集成电路1010与随后的集成电路1011（诸如本公开内容中阐述的图形处理器或射频集成电路或者二者）互补。在一个实施例中，双集成电路1010包括诸如eDRAM之类的嵌入式管芯上存储器1017。双集成电路1011包括RFIC双处理器1013和双通信电路1015和诸如SRAM之类的双管芯上存储器1017。在一个实施例中，双通信电路1015被特定地配置为用于RF处理。
在一个实施例中，至少一个无源器件1080耦接到随后的集成电路1011，从而使得集成电路1011和至少一个无源器件是包括偏移中介层（其包括集成电路1010和集成电路1011）的任意装置实施例的一部分。在一个实施例中，至少一个无源器件是传感器（诸如用于平板电脑或智能手机的加速计）。
在一个实施例中，电子系统1000包括天线单元1082（诸如本公开内容中阐述的任何无芯针栅阵列基板实施例）。通过使用天线单元1082，可以通过无线链路由装置实施例来远程操作远程设备1084（诸如电视机）。例如，通过无线链路操作的智能电话上的应用向距离远达约30米的电视机广播指令（诸如通过蓝牙技术）。在一个实施例中，远程设备包括天线单元被配置为接收机的全球卫星定位系统。
在一个实施例中，电子系统1000还包括外部存储器1040，其进而可以包括适合于特定应用的一个或多个存储器单元（诸如RAM形式的主存储器1042）、一个或多个硬盘驱动器1044和/或一个或多个处理可移动介质1046（诸如软盘、光盘（CD）、数字可变光盘（DVD）、闪存驱动器和本领域中已知的其它可移动介质）的驱动器。在一个实施例中，外部存储器1040是根据任意公开实施例堆叠在偏移中介层上的POP封装的一部分。在一个实施例中，外部存储器1040是嵌入式存储器1048，这种装置包括根据任意公开实施例与第一级互连和POP存储器模块基板配对的偏移中介层。
在一个实施例中，电子系统1000还包括显示设备1050和音频输出1060。在一个实施例中，电子系统1000包括诸如控制器1070的输入设备，其可以是键盘、鼠标、触摸板、小键盘、轨迹球、游戏控制器、麦克风、语音识别设备、或者将信息输入到电子系统1000的任何其它输入设备。在一个实施例中，输入设备1070包括照相机。在一个实施例中，输入设备1070包括数字录音机。在一个实施例中，输入设备1070包括照相机和数字录音机。
基本基板1090可以是计算系统1000的一部分。在一个实施例中，基本基板1090是主板，其支持包括偏移中介层的装置。在一个实施例中，基本基板1090是支持包括偏移中介层的装置的板。在一个实施例中，基本基板1090包括虚线1090内所包含的功能体中的至少一个，并且其是诸如无线通信装置的用户外壳之类的基板。
如本文中所示，可以在多种不同的实施例、包括根据若干公开的实施例及其等价物中的任意一个的偏移中介层的装置、电子系统、计算机系统、制造集成电路的一种或多种方法、以及制造和组装包括根据如本文在各个实施例及其本领域公认的等价物中阐述的若干公开的实施例中的任意一个的偏移中介层的装置的一种或多种方法中实现集成电路1010。元件、材料、几何形状、尺寸和操作顺序都可以改变，以适应包括偏移中介层实施例及其等同物的特定的I/O耦合的要求。
尽管管芯可以指处理器芯片、RF芯片、RFIC芯片、IPD芯片，或者可以在同一句子中提到存储器芯片，但不应当被解释为它们是等同的结构。贯穿本公开内容提及“一个实施例”或“实施例”意指结合该实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。在贯穿本公开内容的各个地方出现短语“在一个实施例中”或“在实施例中”并不一定全部指的是相同的实施例。此外，特定的特征、结构或特性可以以任何适当的方式组合在一个或多个实施例中。
可以参照图示的X-Z坐标来理解诸如“上部”和“下部”“以上”和“以下”之类的术语，可以参照X-Y坐标或参照非Z坐标来理解诸如“相邻”之类的术语。
提供摘要以符合37C.F.R.§1.72（b），其要求将允许读者快速确定本技术公开的本质和要旨的摘要。提交摘要，并且理解其将不会被用来解释或限制权利要求的范围或含义。
在前面的具体实施方式中，出于精简本公开内容的目的，在单个实施例中将各种特征组合在一起。本公开内容的方法不应当被解释为反映了以下意图，即：本发明所要求保护的实施例需要比每一项权利要求中明确陈述的更多的特征。相反，如同后面的权利要求所反映的，发明主题在于少于单个所公开的实施例的所有特征。因此，在此将后面的权利要求并入具体实施方式中，其中每个权利要求作为单独的优选实施例代表其自己。
本领域技术人员将很容易理解的是：可以在不背离所附权利要求书中所表达的本发明的原则和范围的前提下，在为了解释本发明的性质而描述和示出的部件和方法步骤的细节、材料和布置上进行各种其它变化。

Claims (38)

1.一种中介层，包括：
焊盘侧，其包括焊盘侧球栅阵列(BGA)，所述焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，其中，所述焊盘侧BGA被配置为与第一级互连相连接；以及
层叠封装(POP)侧，其包括POP侧BGA，所述POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其中，所述POP侧BGA被配置为与POP互连相连接，其中，所述两个焊盘侧焊垫中的每一个通过所述中介层分别耦接到所述两个POP侧焊垫，并且其中，所述两个焊盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹。
2.根据权利要求1所述的中介层，其中，给定的焊盘侧焊垫通过与过孔直接接触耦接到相应的POP侧焊垫。
3.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹。
4.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
5.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是小于百分之50的重叠。
6.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是小于百分之50的重叠，并且其中，给定的焊盘侧焊垫通过与过孔直接接触耦接到相应的POP侧焊垫。
7.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是小于百分之50的重叠，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
8.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是大于百分之50的重叠。
9.根据权利要求1所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是大于百分之50的重叠，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
10.根据权利要求1所述的中介层，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
11.根据权利要求1所述的中介层，其中，所述两个相邻的、分隔开的焊盘侧焊垫是全部以第一间距配置的焊盘侧焊垫阵列的一部分，其中，所述两个相邻的、分隔开的POP侧焊垫是全部以第二间距配置的POP侧焊垫阵列的一部分，并且其中，所述第一间距小于所述第二间距。
12.根据权利要求1所述的中介层，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距与所述第二间距相同。
13.根据权利要求1所述的中介层，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距是0.5mm的中心距，并且所述第二间距是0.4mm的中心距。
14.一种中介层，包括：
焊盘侧，其包括焊盘侧球栅阵列(BGA)，所述焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，其中，所述焊盘侧BGA被配置为与第一级互连相连接；以及
层叠封装(POP)侧，其包括POP侧BGA，所述POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其中，所述POP侧BGA被配置为与POP互连相连接，其中，所述两个焊盘侧焊垫中的每一个通过所述中介层分别耦接到所述两个POP侧焊垫，并且其中，所述两个焊盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，还包括：所述POP侧BGA被布置得具有交替的两焊垫和三焊垫出现，并且所述焊盘侧BGA被布置得仅具有两焊垫出现。
15.根据权利要求14所述的中介层，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，还包括：所述POP侧BGA被布置得具有交替的两焊垫和三焊垫出现，并且所述焊盘侧BGA被布置得仅具有两焊垫出现，并且其中，所述第一间距是0.5mm的中心距，并且所述第二间距是0.4mm的中心距。
16.根据权利要求14所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹。
17.根据权利要求14所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距布置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
18.根据权利要求14所述的中介层，其中，所述两个焊盘侧焊垫的不同足迹是小于百分之50的重叠。
19.一种层叠封装(POP)芯片封装，其包括：
偏移中介层，其包括：
焊盘侧，其包括焊盘侧球栅阵列(BGA)，所述焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，其中，所述焊盘侧BGA被配置为与第一级互连相连接；以及
层叠封装(POP)侧，其包括POP侧BGA，所述POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其中，所述POP侧BGA被配置为与POP互连相连接，其中，所述两个焊盘侧焊垫中的每一个通过所述中介层分别耦接到所述两个POP侧焊垫，并且其中，所述两个焊盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹；
所述POP侧BGA上的耦接到POP互连的POP基板；以及
微电子设备，其置于所述POP基板上，其中，所述微电子设备通过所述POP基板电耦接到所述偏移中介层。
20.根据权利要求19所述的层叠封装(POP)芯片封装，其中，给定的焊盘侧焊垫通过与过孔直接接触耦接到相应的POP侧焊垫。
21.根据权利要求19所述的层叠封装(POP)芯片封装，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹。
22.根据权利要求19所述的层叠封装(POP)芯片封装，其中，所述两个焊盘侧焊垫的不同足迹不包括所述两个POP侧焊垫的足迹，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
23.根据权利要求19所述的层叠封装(POP)芯片封装，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，还包括：所述POP侧BGA被布置得具有交替的两焊垫和三焊垫出现，并且所述焊盘侧BGA被布置得仅具有两焊垫出现。
24.根据权利要求19所述的层叠封装(POP)芯片封装，其中，所述微电子设备以倒装芯片的方式置于所述POP基板上。
25.根据权利要求19所述的层叠封装(POP)芯片封装，还包括：
耦接到所述偏移中介层的所述焊盘侧的第一级互连；以及安装在所述第一级互连上的电子设备。
26.根据权利要求19所述的层叠封装(POP)芯片封装，还包括：
耦接到所述偏移中介层的所述焊盘侧的第一级互连；
安装在所述第一级互连上的电子设备；以及
安装在所述电子设备上的堆叠管芯。
27.根据权利要求19所述的层叠封装(POP)芯片封装，还包括：
耦接到所述偏移中介层的所述焊盘侧的第一级互连；
安装在所述第一级互连上的电子设备；以及
安装在所述电子设备上的丝焊堆叠管芯。
28.根据权利要求19所述的层叠封装(POP)芯片封装，还包括：
耦接到所述偏移中介层的所述焊盘侧的第一级互连；
安装在所述第一级互连上的电子设备；以及
安装在所述电子设备上的硅通孔堆叠管芯。
29.一种构造偏移中介层的过程，包括：
形成焊盘侧，所述焊盘侧包括焊盘侧球栅阵列(BGA)，所述焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，其中，所述焊盘侧BGA被配置为与第一级互连相连接；以及
形成层叠封装(POP)侧，所述POP侧包括POP侧BGA，所述POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其中，所述POP侧BGA被配置为与POP互连相连接，其中，所述两个焊盘侧焊垫中的每一个通过所述中介层分别耦接到所述两个POP侧焊垫，并且其中，所述两个焊盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹。
30.根据权利要求29所述的过程，其中，所述两个焊盘侧焊垫的不同足迹被形成为不包括所述两个POP侧焊垫的足迹，其中，所述两个相邻的、分隔开的焊盘侧焊垫是以第一间距配置的，其中，所述两个相邻的、分隔开的POP侧焊垫是以第二间距配置的，并且其中，所述第一间距小于所述第二间距。
31.根据权利要求29所述的过程，还包括：将所述偏移中介层组装到第一级互连的方法。
32.根据权利要求29所述的过程，还包括：将所述偏移中介层组装到POP基板的方法。
33.一种计算机系统，包括：
偏移中介层，其包括：
焊盘侧，其包括焊盘侧球栅阵列(BGA)，所述焊盘侧BGA包括两个相邻的、分隔开的焊盘侧焊垫，其中，所述焊盘侧BGA被配置为与第一级互连相连接；以及
层叠封装(POP)侧，其包括POP侧BGA，所述POP侧BGA包括两个相邻的、分隔开的POP侧焊垫，其中，所述POP侧BGA被配置为与POP互连相连接，其中，所述两个焊盘侧焊垫中的每一个通过所述中介层分别耦接到所述两个POP侧焊垫，并且其中，所述两个焊
盘侧焊垫中的每一个均具有与相应的两个POP侧焊垫不同的足迹；
所述POP侧BGA上的耦接到POP互连的POP基板；
微电子设备，其置于所述POP基板上，其中，所述微电子设备通过所述POP基板电耦接到所述偏移中介层；
在所述焊盘侧耦接到所述偏移中介层的第一级互连；
置于所述第一级互连上的电子设备；以及
支撑所述第一级互连的基本基板。
34.根据权利要求33所述的计算机系统，其中，所述基本基板是移动设备的一部分。
35.根据权利要求33所述的计算机系统，其中，所述基本基板是智能电话设备的一部分。
36.根据权利要求33所述的计算机系统，其中，所述基本基板是平板计算机设备的一部分。
37.根据权利要求33所述的计算机系统，其中，所述基本基板是车辆的一部分。
38.根据权利要求33所述的计算机系统，其中，所述基本基板是电视机的一部分。
CN201180072839.0A 2011-08-16 2011-08-16 用于大底座封装和大管芯层叠封装结构的偏移中介层 Active CN103748678B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/047948 WO2013025205A1 (en) 2011-08-16 2011-08-16 Offset interposers for large-bottom packages and large-die package-on-package structures

Publications (2)

Publication Number Publication Date
CN103748678A CN103748678A (zh) 2014-04-23
CN103748678B true CN103748678B (zh) 2016-09-14

Family

ID=47715330

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180072839.0A Active CN103748678B (zh) 2011-08-16 2011-08-16 用于大底座封装和大管芯层叠封装结构的偏移中介层

Country Status (5)

Country Link
US (7) US10446530B2 (zh)
EP (4) EP4050649A1 (zh)
KR (2) KR101681269B1 (zh)
CN (1) CN103748678B (zh)
WO (1) WO2013025205A1 (zh)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171824B2 (en) 2009-05-26 2015-10-27 Rambus Inc. Stacked semiconductor device assembly
US9142262B2 (en) 2009-10-23 2015-09-22 Rambus Inc. Stacked semiconductor device
EP4050649A1 (en) 2011-08-16 2022-08-31 Intel Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
WO2013095339A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Pin grid interposer
JP2015041647A (ja) * 2013-08-20 2015-03-02 船井電機株式会社 半導体パッケージ
US9305853B2 (en) 2013-08-30 2016-04-05 Apple Inc. Ultra fine pitch PoP coreless package
US10026666B2 (en) 2013-10-18 2018-07-17 Rambus Inc. Stacked die package with aligned active and passive through-silicon vias
US9209154B2 (en) * 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
KR102298728B1 (ko) * 2014-08-19 2021-09-08 삼성전자주식회사 반도체 패키지
KR102287754B1 (ko) 2014-08-22 2021-08-09 삼성전자주식회사 칩 적층 반도체 패키지
TWI562687B (en) * 2014-09-24 2016-12-11 Wistron Corp Circuit board assembly
US10982736B2 (en) 2015-02-17 2021-04-20 Oshkosh Corporation Multi-mode electromechanical variable transmission
US10578195B2 (en) 2015-02-17 2020-03-03 Oshkosh Corporation Inline electromechanical variable transmission system
US10584775B2 (en) 2015-02-17 2020-03-10 Oshkosh Corporation Inline electromechanical variable transmission system
US11701959B2 (en) 2015-02-17 2023-07-18 Oshkosh Corporation Inline electromechanical variable transmission system
US10421350B2 (en) 2015-10-20 2019-09-24 Oshkosh Corporation Inline electromechanical variable transmission system
US9656659B2 (en) 2015-02-17 2017-05-23 Oshkosh Corporation Multi-mode electromechanical variable transmission
US9650032B2 (en) 2015-02-17 2017-05-16 Oshkosh Corporation Multi-mode electromechanical variable transmission
US9651120B2 (en) 2015-02-17 2017-05-16 Oshkosh Corporation Multi-mode electromechanical variable transmission
US20180053753A1 (en) * 2016-08-16 2018-02-22 Freescale Semiconductor, Inc. Stackable molded packages and methods of manufacture thereof
US10199353B2 (en) * 2016-09-12 2019-02-05 Intel Corporation Microelectronic interposer for a microelectronic package
US10681817B2 (en) * 2016-09-27 2020-06-09 Intel Corporation Frame embedded components
US11201066B2 (en) 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
JP6679528B2 (ja) * 2017-03-22 2020-04-15 キオクシア株式会社 半導体装置
KR102086364B1 (ko) * 2018-03-05 2020-03-09 삼성전자주식회사 반도체 패키지
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
US11581287B2 (en) * 2018-06-29 2023-02-14 Intel Corporation Chip scale thin 3D die stacked package
KR102540829B1 (ko) 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR102568705B1 (ko) 2018-10-05 2023-08-22 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
US11443993B2 (en) * 2019-09-09 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with cavity in interposer
CN112466861A (zh) 2019-09-09 2021-03-09 台湾积体电路制造股份有限公司 封装结构及其形成方法
KR20220001311A (ko) 2020-06-29 2022-01-05 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
CN114397786A (zh) * 2022-01-25 2022-04-26 北京京东方显示技术有限公司 一种显示基板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532930A (zh) * 2003-03-18 2004-09-29 ������������ʽ���� 半导体装置、电子设备及它们的制造方法，以及电子仪器
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
TW200939362A (en) * 2007-12-27 2009-09-16 Stats Chippac Ltd Mountable integrated circuit package system with stacking interposer
JP2010010288A (ja) * 2008-06-25 2010-01-14 Renesas Technology Corp 積層型半導体装置

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US6618267B1 (en) * 1998-09-22 2003-09-09 International Business Machines Corporation Multi-level electronic package and method for making same
US6396136B2 (en) 1998-12-31 2002-05-28 Texas Instruments Incorporated Ball grid package with multiple power/ground planes
JP3792445B2 (ja) 1999-03-30 2006-07-05 日本特殊陶業株式会社 コンデンサ付属配線基板
JP3597754B2 (ja) 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2002204053A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 回路実装方法、回路実装基板及び半導体装置
US20030042587A1 (en) * 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
JP3917946B2 (ja) * 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
US7327554B2 (en) 2003-03-19 2008-02-05 Ngk Spark Plug Co., Ltd. Assembly of semiconductor device, interposer and substrate
JP4771808B2 (ja) * 2003-09-24 2011-09-14 イビデン株式会社 半導体装置
WO2005045925A1 (ja) * 2003-11-07 2005-05-19 Shinko Electric Industries Co., Ltd. 電子装置及びその製造方法
US20060000641A1 (en) * 2004-06-30 2006-01-05 Salama Islam A Laser metallization for ceramic device
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US7358444B2 (en) * 2004-10-13 2008-04-15 Intel Corporation Folded substrate with interposer package for integrated circuit devices
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
US7151010B2 (en) * 2004-12-01 2006-12-19 Kyocera Wireless Corp. Methods for assembling a stack package for high density integrated circuits
US8089143B2 (en) 2005-02-10 2012-01-03 Stats Chippac Ltd. Integrated circuit package system using interposer
US7501839B2 (en) 2005-04-21 2009-03-10 Endicott Interconnect Technologies, Inc. Interposer and test assembly for testing electronic devices
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US8643163B2 (en) * 2005-08-08 2014-02-04 Stats Chippac Ltd. Integrated circuit package-on-package stacking system and method of manufacture thereof
KR100697553B1 (ko) 2005-12-19 2007-03-21 삼성전자주식회사 멀티 스택 패키지 및 이의 제조 방법
KR101332861B1 (ko) 2007-01-03 2013-11-22 삼성전자주식회사 아이씨 패키지 및 그 제조방법
KR100865125B1 (ko) * 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US20090016683A1 (en) * 2007-07-10 2009-01-15 Applied Optoelectronics, Inc. Angled fiber ferrule having off-axis fiber through-hole and method of coupling an optical fiber at an off-axis angle
US8247893B2 (en) 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US8618669B2 (en) * 2008-01-09 2013-12-31 Ibiden Co., Ltd. Combination substrate
US7901987B2 (en) * 2008-03-19 2011-03-08 Stats Chippac Ltd. Package-on-package system with internal stacking module interposer
US7977780B2 (en) 2008-08-01 2011-07-12 Stats Chippac Ltd. Multi-layer package-on-package system
US9559046B2 (en) * 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US8531043B2 (en) 2008-09-23 2013-09-10 Stats Chippac Ltd. Planar encapsulation and mold cavity package in package system
US8169059B2 (en) * 2008-09-30 2012-05-01 Infineon Technologies Ag On-chip RF shields with through substrate conductors
US7993941B2 (en) 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US8723302B2 (en) * 2008-12-11 2014-05-13 Stats Chippac Ltd. Integrated circuit package system with input/output expansion
US8513792B2 (en) 2009-04-10 2013-08-20 Intel Corporation Package-on-package interconnect stiffener
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8034660B2 (en) 2009-07-24 2011-10-11 Texas Instruments Incorporated PoP precursor with interposer for top package bond pad pitch compensation
US8452926B2 (en) * 2009-09-02 2013-05-28 Texas Instruments Incorporated Memory sharing arrangement
JP5425584B2 (ja) * 2009-10-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8653654B2 (en) * 2009-12-16 2014-02-18 Stats Chippac Ltd. Integrated circuit packaging system with a stackable package and method of manufacture thereof
US8987896B2 (en) 2009-12-16 2015-03-24 Intel Corporation High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US20120015344A1 (en) * 2010-05-14 2012-01-19 1. Board of Trustees of MICHIGAN STATE UNIVERSITY Methods, compositions, and apparatus for the detection of viral strains
US8217502B2 (en) * 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8304296B2 (en) * 2010-06-23 2012-11-06 Stats Chippac Ltd. Semiconductor packaging system with multipart conductive pillars and method of manufacture thereof
KR101767108B1 (ko) * 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
US20120159118A1 (en) 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
US8409917B2 (en) * 2011-03-22 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with an interposer substrate and method of manufacture thereof
US20120319295A1 (en) 2011-06-17 2012-12-20 Chi Heejo Integrated circuit packaging system with pads and method of manufacture thereof
US20120324305A1 (en) * 2011-06-20 2012-12-20 Texas Instruments Incorporated Testing interposer method and apparatus
EP4050649A1 (en) 2011-08-16 2022-08-31 Intel Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
US9105483B2 (en) * 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9041171B2 (en) * 2011-12-29 2015-05-26 Broadcom Corporation Programmable interposer with conductive particles
KR102245770B1 (ko) 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532930A (zh) * 2003-03-18 2004-09-29 ������������ʽ���� 半导体装置、电子设备及它们的制造方法，以及电子仪器
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
TW200939362A (en) * 2007-12-27 2009-09-16 Stats Chippac Ltd Mountable integrated circuit package system with stacking interposer
JP2010010288A (ja) * 2008-06-25 2010-01-14 Renesas Technology Corp 積層型半導体装置

Also Published As

Publication number Publication date
KR20160138323A (ko) 2016-12-02
WO2013025205A1 (en) 2013-02-21
US20160133557A1 (en) 2016-05-12
US11798932B2 (en) 2023-10-24
KR101681269B1 (ko) 2016-12-01
EP4050649A1 (en) 2022-08-31
KR20140054143A (ko) 2014-05-08
US10607976B2 (en) 2020-03-31
CN103748678A (zh) 2014-04-23
EP2745317A1 (en) 2014-06-25
US20200251462A1 (en) 2020-08-06
EP2745317A4 (en) 2015-08-12
KR101808478B1 (ko) 2017-12-12
US20240006401A1 (en) 2024-01-04
US10446530B2 (en) 2019-10-15
EP3751604A1 (en) 2020-12-16
US20220157799A1 (en) 2022-05-19
US20130271907A1 (en) 2013-10-17
US20160218093A1 (en) 2016-07-28
EP4113597A1 (en) 2023-01-04
US20220344318A1 (en) 2022-10-27

Similar Documents

Publication Publication Date Title
CN103748678B (zh) 用于大底座封装和大管芯层叠封装结构的偏移中介层
US10719465B2 (en) Stacked semiconductor device assembly in computer system
US8604626B2 (en) Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly
CN103597593B (zh) 包括具有垂直集成相控阵天线和低频功率传递衬底的穿硅过孔管芯的芯片封装
EP2731134A1 (en) Multi-chip module connection by way of bridging blocks
US20080122113A1 (en) Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device and methods for forming the same
CN104350595A (zh) 克服分划板区域限制的大型硅中介板
CN103165555A (zh) 层叠封装的封装结构及其制法
JP2009508324A (ja) マイクロ電子デバイス、積み重ねられたマイクロ電子デバイス、およびマイクロ電子デバイスを製造する方法
CN103620766B (zh) 用于无芯基板的原位建立针栅阵列及其制造方法
JP5394603B2 (ja) 非対称に配置されたダイとモールド体とを具備するスタックされたパッケージを備えるマルチパッケージモジュール。
CN104685624B (zh) 重组晶圆级微电子封装
US20220271013A1 (en) Stacked semiconductor dies for semiconductor device assemblies
CN100585850C (zh) 具晶粒三维堆叠结构的影像感测模块
JP3574004B2 (ja) 半導体装置
CN104718619A (zh) 用于两个或更多个裸片的多裸片倒装堆叠

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant