TWI814050B - 具有用於晶粒堆疊信號路由之再分配結構之半導體總成 - Google Patents

具有用於晶粒堆疊信號路由之再分配結構之半導體總成 Download PDF

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TWI814050B
TWI814050B TW110129080A TW110129080A TWI814050B TW I814050 B TWI814050 B TW I814050B TW 110129080 A TW110129080 A TW 110129080A TW 110129080 A TW110129080 A TW 110129080A TW I814050 B TWI814050 B TW I814050B
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die
redistribution structure
semiconductor
substrate
routing
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TW110129080A
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TW202211393A (zh
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歐文 Ｒ 菲
麥迪遜 Ｅ 瓦勒
詹姆士 Ｌ 弗爾茨
戴倫 Ｗ 索森
達斯汀 Ｌ 霍洛威
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美商美光科技公司
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Abstract

本文中揭示具有再分配結構之半導體裝置，及相關聯系統及方法。在一些實施例中，一種半導體總成包括：一晶粒堆疊，其包含複數個半導體晶粒；及一路由(routing)基板，其經安裝於該晶粒堆疊上。該路由基板包含具有一再分配結構之一上表面。該半導體總成亦包含將該再分配結構耦合至該等半導體晶粒之至少一些之複數個電連接器。該半導體總成進一步包含安裝於該路由基板上之一控制器晶粒。該控制器晶粒包含面向該路由基板之該上表面且電耦合至該再分配結構之一主動表面，使得該路由基板及該等半導體晶粒經由該再分配結構電耦合至該控制器晶粒。

Description

具有用於晶粒堆疊信號路由之再分配結構之半導體總成
本技術大體上係關於半導體裝置，且更特定而言，係關於具有經組態以在垂直堆疊的半導體晶粒之間路由(選路傳送)信號之再分配結構之半導體裝置。
封裝的半導體晶粒，包含記憶體晶片、微處理器晶片及成像器晶片，通常包含安裝於一基板上且圍封於一保護性覆蓋物中之一半導體晶粒。半導體晶粒可包含功能特徵，諸如記憶體胞元、處理器電路及成像器裝置，以及電連接至功能特徵之接合墊。接合墊可電連接至保護性覆蓋物外部之端子以允許半導體晶粒連接至更高級電路系統。
市場壓力不斷地驅使半導體製造商減小晶粒封裝之大小以適應電子裝置之空間約束，同時亦驅使其等增加各封裝之功能容量以滿足操作參數。一種用於增加一半導體封裝之處理能力而不會大幅增加被該封裝覆蓋之表面積(該封裝之「佔用面積」)之方法係在單一封裝中將多個半導體晶粒垂直地彼此上下堆疊。此等垂直堆疊封裝中之晶粒可經由電線、互連件或其他導電結構彼此電耦合及/或電耦合至一基板。然而，用於將信號路由至垂直堆疊的半導體晶粒及自垂直堆疊的半導體晶粒路由信號之習知技術可依賴於封裝基板內之複雜多層路由結構，此可能導致降低的信號完整性、更大的封裝大小及增加的製造成本。
相關申請案之交叉參考
本申請案主張2020年8月17日申請之美國臨時申請案第63/066,436號之權益，該申請案之全文以引用的方式併入本文中。
下文描述半導體裝置以及相關聯系統及方法之若干實施例之特定細節。在一些實施例中，例如，一半導體總成包含各具有複數個半導體晶粒之一或多個晶粒堆疊，及安裝於該(等)晶粒堆疊上之一路由基板(例如，另一半導體晶粒或一中介層)。路由基板包含具有一再分配結構之一上表面及耦合至該(等)晶粒堆疊之(若干)最上半導體晶粒之一下表面。再分配結構可經由複數個電連接器(例如，引線接合)耦合至一些或所有半導體晶粒。半導體總成可進一步包含安裝於路由基板上(例如，經由一覆晶程序)之一控制器晶粒。控制器晶粒可包含面向路由基板之上表面且電耦合至再分配結構之一主動表面，使得路由基板及半導體晶粒經由再分配結構電耦合至控制器晶粒。據此，再分配結構及電連接器可在控制器晶粒與該(等)晶粒堆疊之間路由信號。與其中控制器晶粒經安裝於一封裝基板上且與該(等)晶粒堆疊隔開之裝置相比，本文中所描述之裝置可減少及/或簡化透過封裝基板之信號路由，因為控制器晶粒可經由再分配結構及引線接合(或其他電連接器)而非封裝基板與該(等)晶粒堆疊通信。因此，可使用更薄且更簡單的封裝基板，此會降低封裝高度及製造成本。本技術亦可改良信號完整性及阻抗，諸如減少或消除來自基板路由可能出現之重疊信號之串擾，因為信號係透過再分配結構進行路由。另外，本文中所描述之技術允許經由一覆晶程序將控制器晶粒直接安裝至路由基板上，而無需任何介入間隔件或支撐件，此可簡化製程且進一步減小封裝大小。此外，路由基板可用於在單一封裝基板上實體及電橋接多個晶粒堆疊，此可改良總體封裝之機械強度且減輕翹曲。
相關技術者將認知，可以晶圓級或以晶粒級執行本文中所描述之方法之合適階段。因此，取決於其使用脈絡，術語「基板」可指代一晶圓級基板或一單粒化、晶粒級基板。此外，除非脈絡另有指示，否則可使用習知半導體製造技術來形成本文中所揭示之結構。例如，可使用化學氣相沈積、物理氣相沈積、原子層沈積、鍍敷、無電鍍敷、旋塗及/或其他合適技術來沈積材料。類似地，可例如使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他合適技術來移除材料。
本文中揭示眾多特定細節以提供對本技術之實施例之一全面且可行的描述。然而，熟習此項技術者將理解，本技術可具有額外實施例且可在沒有下文參考圖1A至圖4所描述之實施例之若干細節之情況下實踐本技術。例如，已省略此項技術中熟知之半導體裝置及/或封裝之一些細節以免混淆本技術。一般而言，應理解，除本文中所揭示之彼等特定實施例之外的各種其他裝置及系統亦可在本技術之範疇內。
如本文中所使用，術語「垂直」、「橫向」、「上」、「下」、「上方」及「下方」可指代半導體裝置中之特徵鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可指代比另一特徵更靠近一頁面頂部之一特徵。然而，此等術語應廣義地解釋為包含具有其他定向之半導體裝置，諸如倒置或傾斜定向，其中頂部/底部、之上/之下、上方/下方、上/下及左/右可取決於定向而互換。
圖1A及圖1B繪示根據本技術之實施例組態之一半導體封裝100。更具體而言，圖1A係封裝100之一側視橫截面圖且圖1B係封裝100之一俯視圖。封裝100包含安裝於一封裝基板104上之一晶粒堆疊102及安裝於晶粒堆疊102上之一路由基板106 (例如，半導體晶粒或中介層)。晶粒堆疊102包含複數個垂直堆疊的半導體晶粒108a-c (統稱為「第一晶粒108」；僅出於清楚之目的而自圖1B省略第一晶粒108)。第一晶粒108可經配置成一疊瓦式或階梯式組態，其中各晶粒與下方的晶粒水平地偏移以允許電互連，如下文更詳細地論述。儘管圖1A將晶粒堆疊102描繪為包含三個第一晶粒108a-c，但在其他實施例中，晶粒堆疊102可包含更少或更多第一晶粒108 (例如，一個、兩個、四個、五個、六個、七個、八個、九個、十個或更多個晶粒)。封裝100進一步包含安裝於路由基板106上之一第二半導體晶粒110 (「第二晶粒110」)。第二晶粒110可為經組態以控制路由基板106及/或第一晶粒108之操作之一控制器晶粒(例如，一微控制器)，如下文更詳細地論述。
第一及第二晶粒108、110可各包含一半導體基板(例如，一矽基板、砷化鎵基板、一有機層壓基板等)。在一些實施例中，第一及第二晶粒108、110各包含具有各種類型之半導體組件之一前及/或主動表面。例如，第一晶粒108及/或第二晶粒100可各具有記憶體電路(例如，動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體(例如，NAND、NOR)或其他類型之記憶體電路)、控制器電路(例如，DRAM控制器電路)、邏輯電路、處理電路、電路元件(例如，電線、跡線、互連件、電晶體等)、成像組件及/或其他半導體特徵。在一些實施例中，第一晶粒108可各配置成一「面朝上」組態，其中其等前表面向上且遠離封裝基板104定向。然而，在其他實施例中，第一晶粒108之一或多者可呈一「面朝下」組態，其中其等前表面向下且朝向封裝基板104定向。視情況，第一晶粒108之一或多者可為不包含半導體組件且由例如以下材料形成之一「空白」基板：結晶、半結晶及/或陶瓷基板材料，諸如矽、多晶矽、氧化鋁(Al2 O3 )、藍寶石及/或其他合適材料。
路由基板106包含經組態以在晶粒堆疊102之第二晶粒110與第一晶粒108之間路由信號(例如，控制信號、ONFI信號、電流信號、測試信號等)之一再分配結構112。例如，在其中路由基板106係一半導體晶粒或以其他方式包含功能組件之實施例中，再分配結構112亦可在第二晶粒110與路由基板106之間路由信號。如圖1A中最佳可見，路由基板106可包含一上(例如，前)表面114a及一下(例如，後)表面114b，且再分配結構112可具有暴露於上表面114a處之墊或其他端子。在一些實施例中，再分配結構112係或包含一再分配層(RDL)(例如，在一晶圓探針測試之後形成)或一直插式再分配層(iRDL)(例如，在一晶圓探針測試之前形成)。
再分配結構112可包含一或多種導電元件，諸如接觸件、跡線、墊、接腳、佈線、電路系統及類似者，及一或多種介電材料。再分配結構112之導電組件可由任何合適導電材料製成，諸如一或多種金屬(例如，銅、金、鈦、鎢、鈷、鎳、鉑等)、含金屬組合物(例如，金屬矽化物、金屬氮化物、金屬碳化物等)及/或導電摻雜半導體材料(例如，導電摻雜矽、導電摻雜鍺等)。儘管圖1A將再分配結構112繪示為具有單一路由或金屬化層，但在其他實施例中，再分配結構112可包含多個路由或金屬化層(例如，兩個、三個、四個、五個或更多個層)。
路由基板106可為作為用於製造再分配結構112之一合適基板之任何組件。在一些實施例中，路由基板106係一半導體晶粒，例如，具有類似於第一及/或第二晶粒108、110之特徵之一半導體晶粒。例如，路由基板106可為一記憶體晶粒(例如，一NAND晶粒、一SRAM晶粒等)，且第一晶粒108亦可為記憶體晶粒(例如，NAND晶粒)。替代地，路由基板106可為一中介層，諸如一無機中介層(例如，矽、玻璃、陶瓷等)或一有機中介層(例如，FR-4、聚醯亞胺、一無芯層壓板等)。可使用熟習此項技術者已知之任何合適技術，諸如半導體製造程序(例如，若路由基板106係一半導體晶粒、無機中介層或其他無機基板)或電路板製程(例如，若路由基板106係一有機中介層或其他有機基板)，在路由基板106上形成再分配結構112。
視情況，除再分配結構112之外，路由基板106亦可包含其他功能組件。例如，路由基板106可包含主動電路元件(例如，電晶體、記憶體電路、控制器電路、邏輯電路或其他半導體組件)且再分配結構112經形成於主動電路元件上或之上。在一些實施例中，路由基板106係一記憶體晶粒(例如，一NAND晶粒、SRAM晶粒等)且再分配結構112經形成於記憶體晶粒之記憶體電路上或之上。作為另一實例，路由基板106可包含被動電路元件，諸如電容器、電感器及/或電阻器。被動電路元件可使用半導體製造技術形成於路由基板106中，或可為附接至路由基板106之表面安裝組件，如下文更詳細地論述。然而，在其他實施例中，路由基板106可僅用於在第二晶粒110與晶粒堆疊102之第一晶粒108之間路由信號，且可不包含任何額外主動及/或被動電路元件。
第二晶粒110藉由互連結構118電及機械耦合至路由基板106上之再分配結構112。如圖1A中最佳可見，第二晶粒110可包含一上(例如，後)表面116a及一下(例如，主動及/或前)表面116b。第二晶粒110可呈一面對面(F2F)組態安裝至路由基板106，其中第二晶粒110之下表面116b面向路由基板106之上表面114a及再分配結構112。在一些實施例中，第二晶粒110直接連接至路由基板106而在第二晶粒110與路由基板106之間沒有任何介入間隔件、支撐件、其他晶粒等。
一起參考圖1A及圖1C (圖1C係圖1A之一互連結構118之一特寫圖)，互連結構118可為在第二晶粒110之下表面116b與再分配結構112之間的凸塊、微凸塊、支柱、柱、螺柱等。如圖1C中所展示，各互連結構118可將第二晶粒110上之一接腳或墊120 (例如，一資料接腳、一位址接腳、一控制接腳)連接至再分配結構112之一對應接觸件122。儘管圖1C繪示單一接腳120及單一接觸件122，但熟習此項技術者應明白，第二晶粒110可包含複數個接腳120且再分配結構112可包含對應的複數個接觸件122。互連結構118可包含任何合適的導電材料，諸如銅、鎳、金、矽、鎢、焊料(例如，SnAg基焊料)、導電環氧樹脂、其等組合等，且可藉由電鍍、無電鍍覆或其他合適程序來形成。在一些實施例中，互連結構118亦包含形成於互連結構118之末端部分之上的阻障材料(例如，鎳、鎳基金屬間化合物及/或金；未展示)。阻障材料可促進接合及/或防止或至少抑制用於形成互連結構118之銅或其他金屬之電遷移。視情況，互連結構118可被路由基板106與第二晶粒110之間的一底部填充材料(未展示)環繞。
一起參考圖1B及圖1C，再分配結構112可包含在路由基板106之上表面114a之上延伸以將信號自第二晶粒110路由至路由基板106之周邊之複數個跡線124。第二晶粒110可位於路由基板106 (圖1B)之內部部分處，且跡線124可自第二晶粒110下面之互連結構118及接觸件122 (圖1C)之位置延伸至路由基板106之周邊部分處之複數個接合墊126。各跡線124可將一各自接觸件122 (圖1C)電連接至路由基板106之周邊部分處之一對應接合墊126 (圖1B)。跡線124可藉由一絕緣材料(例如，一介電材料；未展示)而彼此分開以減少或消除個別跡線124之間的干擾及/或串擾。
跡線124之數目、幾何形狀及配置可被設計為提供不同信號路由組態且可針對特定裝置或封裝進行客製化。圖1B中所展示之跡線124可延伸至路由基板106之四個邊緣之各者。然而，在其他實施例中，跡線124可延伸至路由基板106之較少邊緣，諸如一個邊緣、兩個邊緣或三個邊緣。另外，一些或所有跡線124可具有不同幾何形狀(例如，不同長度、寬度、形狀等)。例如，跡線124a比跡線124b寬，該等跡線124b比跡線124c寬。在一些實施例中，不同幾何形狀用於適應不同類型之信號，例如，較寬跡線可用於電流輸送，而較窄跡線可用於高速資料信號。
再次一起參考圖1A及圖1B，封裝100進一步包含將再分配結構112、封裝基板104及第一晶粒108彼此耦合以在此等組件之間路由信號(例如，控制信號、ONFI信號、電流信號、測試信號等)之複數個電連接器128a-d (例如，引線接合)。在一些實施例中，各電連接器之末端經附接至對應封裝組件上之各自接合墊(僅出於清楚之目的而在圖1A中省略再分配結構112及第一晶粒108上之接合墊)。例如，再分配結構112可經由在再分配結構112之接合墊126 (圖1B)與封裝基板104上之對應接合墊130之間延伸之一或多個電連接器128a電耦合至封裝基板104。據此，再分配結構112及電連接器128a可直接在第二晶粒110與封裝基板104之間路由信號(例如，電流信號、至及/或來自一主機裝置之信號)。
再分配結構112及電連接器128b-c可在第二晶粒110與晶粒堆疊102之第一晶粒108之各者之間路由信號。例如，在所繪示實施例中，封裝100包含將再分配結構112電耦合至最上第一晶粒108a以直接在第二晶粒110與最上第一晶粒108a之間路由信號之至少一個電連接器128b。封裝100亦可包含將第一晶粒108a-c彼此連接之一系列級聯電連接器128c。例如，最上第一晶粒108a藉由一個電連接器128c電耦合至第一晶粒108b，且第一晶粒108b藉由另一電連接器128c電耦合至最下第一晶粒108c。據此，再分配結構112、電連接器128b-c及最上第一晶粒108a可共同地在第二晶粒110與第一晶粒108b之間路由信號。類似地，再分配結構112、電連接器128b-c及第一晶粒108a-b可共同地在第二晶粒110與最下第一晶粒108c之間路由信號。視情況，封裝100可包含將最下第一晶粒108c直接電耦合至封裝基板104之至少一個電連接器128d。電連接器128d可直接在最下第一晶粒108c與封裝基板104之間路由信號(例如，測試信號)。
儘管在圖1A及圖1B之組態中，電連接器128a-d被描繪為引線接合，但封裝100可包含用於將再分配結構112、封裝基板104、路由基板106及/或第一晶粒108彼此電耦合之其他類型之電連接器。在其他實施例中，例如，圖1A及圖1B中展示之晶粒至晶粒連接(例如，在路由基板106與最上第一晶粒108a之間及/或在任何第一晶粒108之間)及/或晶粒至基板連接(例如，在最下第一晶粒108c與封裝基板104之間)之任一者可代替地使用穿矽通路(TSV)、互連結構(例如，凸塊、微凸塊、支柱、柱、螺柱等)及/或熟習此項技術者已知之任何其他互連技術來實施。此外，在其他實施例中，可省略電連接器128a-d之一或多者。下文關於圖2A至圖2C進一步論述電連接器128a-d之組態之額外實例。
封裝基板104可為或包含一中介層、一印刷電路板、一介電間隔件、另一半導體晶粒(例如，一邏輯晶粒)或另一合適基板。在一些實施例中，封裝基板104包含額外半導體組件(例如，摻雜矽晶圓或砷化鎵晶圓)、非導電組件(例如，各種陶瓷基板，諸如氧化鋁(Al2 O3 )等)、氮化鋁及/或導電部分(例如，互連電路系統、TSV等)。封裝基板104可進一步包含電耦合至封裝基板104且經組態以將封裝100電耦合至一外部裝置(未展示) (諸如如下文進一步論述之一主機裝置)之電連接器134 (例如，焊球、導電凸塊、導電支柱、導電環氧樹脂及/或其他合適導電元件)。視情況，封裝基板104可包含一或多個信號路由結構或層(未展示)，該等信號路由結構或層包含在電連接器134與第二晶粒110及/或晶粒堆疊102之間傳輸信號之導電組件，諸如跡線、通路等。如先前所論述，本文中所描述之晶粒堆疊102、第二晶粒110及再分配結構112之組態可減少經由封裝基板104路由信號，使得與透過封裝基板路由控制器信號之習知系統相較，可使封裝基板104可更薄及/或更簡單。例如，封裝基板104可包含不超過一個、兩個、三個或四個信號路由層。封裝基板104可具有小於或等於250 μm、200 μm、150 μm、125 μm、100 μm或75 μm之一厚度。
封裝100可進一步包含形成於封裝基板104之至少一部分之上及/或至少部分地圍繞路由基板106與第一及第二晶粒108、110之一模制材料或囊封劑140 (僅出於清楚之目的而自圖1B省略模制材料140)。模制材料140可為樹脂、環氧樹脂、矽基材料、聚醯亞胺或適合於囊封路由基板106、第一及第二晶粒108、110及/或封裝基板104之至少一部分以保護此等組件免受污染及/或實體損壞之任何其他材料。
視情況，封裝100可包含表面安裝組件150 (圖1A及圖1B中最佳可見)，諸如電容器、電阻器、電感器及/或其他電路元件。表面安裝組件可在封裝基板104上(例如，在遠離晶粒堆疊102及接合墊130之周邊部分處)、在路由基板106上(例如，在遠離跡線124及第二晶粒110之位置處—圖1B)及/或在任何其他合適位置處。在一些實施例中，半導體封裝100包含其他組件，諸如外部散熱器、一外殼(例如，導熱外殼)、電磁干擾(EMI)遮蔽組件等。
在一些實施例中，封裝100經由電連接器134可操作地連接至一主機裝置(未展示)。主機裝置可為一運算裝置，諸如一桌上型或可擕式電腦、一伺服器、一手持裝置(例如，一行動電話、一平板電腦、一數位閱讀器、一數位媒體播放器)或其等某一組件(例如，一中央處理單元、一共處理器、一專用記憶體控制器等)。主機裝置可為一網路化裝置(例如，一交換機、一路由器等)，一數位影像、音訊及/或視訊記錄器，一車輛，一電器，一玩具或數個其他產品之任一者。在一些實施例中，主機裝置直接連接至封裝100，而在其他實施例中，主機裝置可間接連接至封裝100 (例如，透過一網路化連接或透過中間裝置)。
例如，在一些實施例中，封裝100一係記憶體裝置且經組態以連接至利用記憶體來暫時或永久儲存資訊之一主機裝置或其組件。在此等實施例中，第一晶粒108可為記憶體晶粒(例如，NAND記憶體晶粒)，且第二晶粒110可為一記憶體控制器。路由基板106亦可為一記憶體晶粒(例如，一NAND記憶體晶粒、一SRAM記憶體晶粒)。例如，路由基板106可為一SRAM記憶體晶粒或為記憶體控制器之操作提供資料儲存之其他記憶體晶粒。替代地，路由基板106可不包含任何記憶體電路且可僅起到在記憶體控制器與個別記憶體晶粒之間路由信號之作用。記憶體裝置可包含複數個外部端子，該等外部端子包含耦合至一命令匯流排及一位址匯流排以分別接收命令信號CMD及位址信號ADDR之命令及位址端子。記憶體裝置可進一步包含用於接收一晶片選擇信號CS之一晶片選擇端子，用於接收時脈信號CK及CKF之時脈端子，用於接收資料時脈信號WCK及WCKF之資料時脈端子，用於接收資料信號之資料端子DQ、RDQS、DBI及DMI及/或電源供應端子VDD、VSS及VDDQ。
可使用熟習此項技術者已知之任何合適程序來製造封裝100。在一些實施例中，例如，封裝100之一製程包含使用晶圓級或晶片級程序在路由基板106上形成再分配結構112。隨後，將路由基板106安裝於晶粒堆疊102上(例如，經由晶粒附接膜或其他合適技術)。晶粒堆疊102可在將路由基板106安裝於晶粒堆疊102上之前、期間或之後安裝於封裝基板104上。第二晶粒110可在將路由基板106安裝於晶粒堆疊102上之前、期間或之後安裝於路由基板106上。在一些實施例中，第二晶粒110使用一熱壓接合(TCB)操作經由互連結構118機械及電耦合至路由基板106。接著，可形成電連接器128a-d且將其附接至路由基板106，第一及第二晶粒108、110與封裝基板104以將此等組件彼此電耦合，如上文所論述。
圖2A至圖2C繪示根據本技術之實施例組態之具有各種電連接器配置之半導體封裝。圖2A至圖2C中所展示之封裝可大體上類似於關於圖1A至圖1C所描述之封裝100。據此，類似數字用於識別類似或相同組件，且圖2A至圖2C中所展示之封裝之描述將限於不同於圖1A至圖1C之封裝100之彼等特徵。
圖2A繪示包含用於互連晶粒堆疊102、封裝基板104、路由基板106及第二晶粒110之複數個電連接器248a-c (例如，引線接合)之一半導體封裝200a。電連接器248a將再分配結構112直接耦合至封裝基板104；電連接器248b將再分配結構112直接耦合至最上第一晶粒108a；且級聯電連接器248c將第一晶粒108a-c彼此串聯耦合。與圖1A至圖1C之封裝100不同，封裝200a不包含將最下第一晶粒108c直接耦合至封裝基板104之任何電連接器。代替地，電連接器248a-c、再分配結構112及第一晶粒108a-b共同地在最下第一晶粒108c與封裝基板104之間路由信號。
圖2B繪示包含用於互連晶粒堆疊102、封裝基板104、路由基板106及第二晶粒110之複數個電連接器258a-d (例如，引線接合)之一半導體封裝200b。電連接器258a將再分配結構112直接耦合至封裝基板104。在所繪示實施例中，各第一晶粒108經由一組各自電連接器直接電耦合至再分配結構112。例如，電連接器258b將最上第一晶粒108a直接耦合至再分配結構112；電連接器258c將第一晶粒108b直接耦合至再分配結構112；且電連接器258d將最下第一晶粒108c直接耦合至再分配結構112。據此，再分配結構112及電連接器258b-d可直接在各自之第一晶粒108與第二晶粒1102之間傳輸信號。
圖2C繪示包含用於互連晶粒堆疊102、封裝基板104、路由基板106及第二晶粒110之複數個電連接器268a-d (例如，引線接合)之一半導體封裝200c。電連接器268a將再分配結構112直接耦合至封裝基板104。在所繪示實施例中，一些第一晶粒108直接電耦合至再分配結構112，而一些第一晶粒108經由其他第一晶粒108間接耦合。例如，電連接器268b-c分別將第一晶粒108a-b直接耦合至再分配結構112，以提供第二晶粒110與第一晶粒108a-b之各者之間的直接信號傳輸。然而，最下第一晶粒108c不直接耦合至再分配結構112。代替地，電連接器268d將最下第一晶粒108c耦合至第一晶粒108b，且第一晶粒108b在最下第一晶粒108c與第二晶粒110之間路由信號。然而，在其他實施例中，封裝200c可包含第二晶粒110與第一晶粒108之間的不同路由組態。
圖3係根據本技術之實施例組態之一半導體封裝300之一示意橫截面圖。封裝300可大體上類似於關於圖1A至圖2C所描述之封裝，不同之處在於封裝300包含多個晶粒堆疊(例如，第一晶粒堆疊302a及第二晶粒堆疊302b)而非單一晶粒堆疊。據此，類似數字用於識別類似或相同組件(例如，路由基板306對比路由基板106)，且封裝300之描述將限於不同於圖1A至圖2C之封裝之彼等特徵。
第一及第二晶粒堆疊302a-b經安裝於一封裝基板104上。第一及第二晶粒堆疊302a-b可各相同於或大體上類似於圖1A至圖1C之晶粒堆疊102。例如，第一晶粒堆疊302a包含第一組第一半導體晶粒308a (例如，第一組記憶體晶粒)且第二晶粒堆疊302b包含第二組第一半導體晶粒308b (例如，第二組記憶體晶粒)。在所繪示實施例中，第一及第二晶粒堆疊302a-b兩者經配置成一疊瓦式組態且朝向彼此成角度。在其他實施例中，第一及第二晶粒堆疊302a-b可彼此遠離成角度、在平行方向上成角度或任何其他合適組態。另外，儘管第一及第二晶粒堆疊302a-b被描繪為各包含四個晶粒，但在其他實施例中，第一及/或第二晶粒堆疊302a-b可包含較少或較多晶粒(例如，一個、兩個、三個、五個或更多個晶粒)。第一及第二晶粒堆疊302a-b可包含相同數目個晶粒及/或以其他方式具有相同或實質上類似的高度。
封裝300進一步包含一路由基板306 (例如，另一半導體晶粒或中介層)，其中再分配結構312形成於路由基板306之上表面314a上。路由基板306可相同於或大體上類似於圖1A至圖2C之路由基板106，不同之處在於路由基板306經安裝於多個晶粒堆疊(例如，第一及第二晶粒堆疊302a-b)上。如圖3中所展示，路由基板306之下表面314b經耦合至第一及第二晶粒堆疊302a-b之各者中之最上晶粒。藉由橋接第一及第二晶粒堆疊302a-b，路由基板306可增加封裝300之機械強度(例如，改良三點彎曲效能)且減少翹曲(例如，由於製造及/或操作期間之加熱)。
再分配結構312 (例如，一iRDL或RDL結構)經組態以在第一及第二晶粒堆疊302a-b與安裝於路由基板306上之一第二晶粒310 (例如，一控制器晶粒)之間路由信號。再分配結構312可相同於或大體上類似於圖1A至圖2C之再分配結構112，不同之處在於再分配結構312將信號路由至多個晶粒堆疊(例如，第一及第二晶粒堆疊302a-b)。類似地，第二晶粒310可相同於或大體上類似於圖1A至圖2C之第二晶粒110，不同之處在於第二晶粒310與多個晶粒堆疊(例如，第一及第二晶粒堆疊302a-b)通信。第二晶粒310可包含背離路由基板306之一上(例如，後)表面316a，及面向路由基板306之上表面314a及再分配結構312之一下(例如，主動及/或前)表面316b。第二晶粒310可經由互連結構318電及機械耦合至再分配結構312。
在一些實施例中，再分配結構312經由複數個電連接器328a-c (例如，引線接合)電耦合至封裝基板104、第一晶粒堆疊302a及/或第二晶粒堆疊302b。例如，封裝300可包含將再分配結構312連接至封裝基板104之一組電連接器328a、將再分配結構312連接至第一晶粒堆疊302a之第一組第一晶粒308a之一組電連接器328b及/或將再分配結構312連接至第二晶粒堆疊302b之第二組第一晶粒308b之一組電連接器328c。據此，電連接器328a-c及再分配結構312可在第二晶粒310、第一晶粒堆疊302a、第二晶粒堆疊302b、封裝基板104及/或路由基板306之間路由信號(例如，控制信號、ONFI信號、電流信號、測試信號等)。在所繪示實施例中，電連接器328b經配置為一級聯串聯，而電連接器328c包含級聯連接器及直接連接至個別晶粒之連接器兩者。然而，在其他實施例中，電連接器328a-c之任一者可不同地配置(例如，如先前關於圖2A至圖2C所論述)，或可完全被省略。另外，封裝300可包含圖3中未展示之額外電連接器，諸如一晶粒與封裝基板104之間的電連接器。
視情況，封裝300可包含一或多個表面安裝組件150，諸如電容器、電阻器、電感器及/或其他電路元件。該等表面安裝組件可在封裝基板104上(例如，在遠離第一及第二晶粒堆疊302a-b之周邊部分處，在第一與第二晶粒堆疊302a-b之間)，在路由基板106上或在任何其他合適位置上。
可使用熟習此項技術者已知之任何合適程序來製造封裝300。在一些實施例中，例如，封裝300之一製程包含將第一及第二晶粒堆疊302a-b安裝於封裝基板104上。該程序進一步包含使用晶圓級或晶片級程序在路由基板306上形成再分配結構312。隨後，將路由基板306安裝於第一及第二晶粒堆疊302a-b上(例如，經由晶粒附接膜或其他合適技術)。第二晶粒310可在將路由基板306安裝於第一及第二晶粒堆疊302a-b上之前、期間或之後安裝於路由基板306上。接著，可形成電連接器328a-c且將其附接至路由基板306、第一及第二晶粒堆疊302a-b與封裝基板104以將此等組件彼此電耦合，如上文所論述。
儘管圖3繪示具有經組態以在兩個晶粒堆疊之間傳輸信號之路由基板306之一封裝300，但在其他實施例中，封裝300可包含更多數目個晶粒堆疊，諸如三個、四個、五個或更多個晶粒堆疊。在此等實施例中，路由基板306可機械及電耦合至該等晶粒堆疊之各者以在該等晶粒堆疊、一控制器晶粒(例如，第二晶粒310)及/或封裝基板104之間路由信號。
具有上文參考圖1A至圖3所描述之特徵之半導體裝置及/或封裝之任一者可併入至無數更大及/或更複雜系統之任一者中，該等系統之一代表性實例係圖4中示意性地展示之系統400。系統400可包含一處理器402、一記憶體404 (例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置406及/或其他子系統或組件408。上文參考圖1A至圖3所描述之半導體晶粒及/或封裝可包含於圖4中所展示之元件之任一者中。所得系統400可經組態以執行各種各樣的合適運算、處理、儲存、感測、成像及/或其他功能之任一者。據此，系統400之代表性實例包含但不限於電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路電器、手持裝置(例如，掌上電腦、可穿戴電腦、蜂巢或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器或可程式化消費電子產品、網路電腦及小型電腦。系統400之額外代表性實例包含燈、相機、車輛等。關於此等及其他實例，系統400可例如透過一通信網路容納於單一單元中或分佈於多個互連單元上。系統400之組件據此可包含本端及/或遠端記憶體儲存裝置與各種各樣的合適電腦可讀媒體之任一者。
自前文將明白，本文中已出於繪示之目的而描述本技術之特定實施例，但可在不背離本發明之情況下進行各種修改。據此，本發明除受隨附發明申請專利範圍限制之外不受限制。此外，特定實施例之脈絡中所描述之新技術之特定態樣亦可在其他實施例中進行組合或消除。此外，儘管與新技術之特定實施例相關聯之優點已在彼等實施例之脈絡中進行描述，但其他實施例亦可展現此等優點且並非所有實施例必定展現此等優點落入本技術之範疇內。據此，本發明及相關聯技術可涵蓋本文中未明確地展示或描述之其他實施例。
100:半導體封裝 102:晶粒堆疊 104:封裝基板 106:路由基板 108a:半導體晶粒/最上第一晶粒 108b:半導體晶粒/第一晶粒 108c:半導體晶粒/最下第一晶粒 110:第二半導體晶粒/第二晶粒 112:再分配結構 114a:上(例如，前)表面 114b:下(例如，後)表面 116a:上(例如，後)表面 116b:下(例如，主動及/或前)表面 118:互連結構 120:接腳或墊 122:接觸件 124:跡線 124a-c:跡線 126:接合墊 128a-d:電連接器 130:接合墊 134:電連接器 140:模制材料或囊封劑 150:表面安裝組件 200a:半導體封裝 200b:半導體封裝 200c:半導體封裝 248a-c:電連接器 258a-d:電連接器 268a-d:電連接器 300:半導體封裝 302a:第一晶粒堆疊 302b:第二晶粒堆疊 306:路由基板 308a:第一組第一半導體晶粒 308b:第二組第一半導體晶粒 312:再分配結構 314a:上表面 314b:下表面 316a:上(例如，後)表面 316b:下(例如，主動及/或前)表面 318:互連結構 328a-c:電連接器 400:系統 402:處理器 404:記憶體 406:輸入/輸出裝置 408:其他子系統或組件
參考以下圖式可更佳地理解本技術之諸多態樣。該等圖式中之組件不一定按比例繪製。代替地，重點放在清楚地繪示本技術之原理上。
圖1A係根據本技術之實施例組態之一半導體封裝之一側視橫截面圖。
圖1B係圖1A之半導體封裝之一俯視圖。
圖1C係圖1A之半導體封裝之一互連結構之一特寫圖。
圖2A係根據本技術之實施例組態之包含複數個電連接器之一半導體封裝之一側視橫截面圖。
圖2B係根據本技術之實施例組態之包含複數個電連接器之另一半導體封裝之一側視橫截面圖。
圖2C係根據本技術之實施例組態之包含複數個電連接器之另一半導體封裝之一側視橫截面圖。
圖3係根據本技術之實施例組態之一半導體封裝之一側視橫截面圖。
圖4係包含根據本技術之實施例組態之一半導體裝置或封裝之一系統之一示意圖。
100:半導體封裝
102:晶粒堆疊
104:封裝基板
106:路由基板
108a:半導體晶粒/最上第一晶粒
108b:半導體晶粒/第一晶粒
108c:半導體晶粒/最下第一晶粒
110:第二半導體晶粒/第二晶粒
112:再分配結構
114a:上(例如，前)表面
114b:下(例如，後)表面
116a:上(例如，後)表面
116b:下(例如，主動及/或前)表面
118:互連結構
128a-d:電連接器
130:接合墊
134:電連接器
140:模制材料或囊封劑
150:表面安裝組件

Claims (24)

  1. 一種半導體總成，其包括：一封裝基板，一晶粒堆疊，其由該封裝基板所支撐且包含複數個半導體晶粒；一路由基板，其經安裝於該晶粒堆疊上，其中該路由基板包含背離該晶粒堆疊之一上表面；一再分配結構，其經形成於該路由基板之該上表面之上，其中該再分配結構包含在該再分配結構之一內部部分處之複數個接觸件及在該再分配結構之一周邊部分處之複數個接合墊；複數個電連接器，其等將該再分配結構之該複數個接合墊耦合至該晶粒堆疊之該複數個半導體晶粒；及一控制器晶粒，其經安裝於該路由基板上，其中該控制器晶粒包含面向該再分配結構且電耦合至該再分配結構之該複數個接觸件之一主動表面，其中該複數個半導體晶粒經由該再分配結構電耦合至該控制器晶粒而不包含透過該封裝基板進行路由之任何介入電連接(intervening electrical connection)。
  2. 如請求項1之半導體總成，其中該路由基板係一半導體晶粒。
  3. 如請求項2之半導體總成，其中該路由基板係一記憶體晶粒。
  4. 如請求項1之半導體總成，其中該路由基板係一有機或無機中介層 (interposer)。
  5. 如請求項1之半導體總成，其中該再分配結構包含複數個路由層。
  6. 如請求項1之半導體總成，其進一步包括將該控制器晶粒之該主動表面耦合至該路由基板之該再分配結構之複數個互連結構。
  7. 如請求項6之半導體總成，其中該再分配結構包含複數個跡線，其中各跡線將在該內部部分處之該複數個接觸件一各自接觸件連接至在該周邊部分處之該複數個接合墊一各自接合墊。
  8. 如請求項7之半導體總成，其中直接自該再分配結構上方觀看，該複數個跡線之至少一些具有不同寬度。
  9. 如請求項1之半導體總成，其中該複數個半導體晶粒包括一或多個記憶體晶粒。
  10. 如請求項1之半導體總成，其中：該晶粒堆疊係一第一晶粒堆疊且該等半導體晶粒係第一半導體晶粒；該半導體總成進一步包括包含複數個第二半導體晶粒之一第二晶粒堆疊；及該路由基板經安裝於該等第一及第二晶粒堆疊上，使得該等第二半 導體晶粒經由該再分配結構電耦合至該控制器晶粒。
  11. 如請求項10之半導體總成，其中該等電連接器係第一電連接器，且該半導體總成進一步包括將該再分配結構耦合至該第二晶粒堆疊之該等第二半導體晶粒之至少一些之複數個第二電連接器。
  12. 如請求項1之半導體總成，其中該封裝基板經由該再分配結構及該複數個電連接器耦合至該晶粒堆疊及該控制器晶粒。
  13. 如請求項12之半導體總成，其中該封裝基板包含不超過兩個路由層。
  14. 如請求項1之半導體總成，其中該路由基板進一步包含一或多個被動電路元件。
  15. 一種製造一半導體總成之方法，該方法包括：在一路由基板之一上表面之上形成一再分配結構；將一控制器晶粒安裝於該路由基板之該上表面上，使得該控制器晶粒之一主動表面面向該上表面且電耦合至該再分配結構；及將該路由基板之一下表面耦合至包含複數個半導體晶粒之一晶粒堆疊。
  16. 如請求項15之方法，其中該控制器晶粒之該主動表面經由一熱壓接 合程序電耦合至該再分配結構。
  17. 如請求項16之方法，其中該熱壓接合程序包括使用複數個互連結構將該主動表面連接至該再分配結構。
  18. 如請求項15之方法，其進一步包括使用複數個引線接合將該再分配結構電耦合至該等半導體晶粒之至少一些。
  19. 如請求項15之方法，其進一步包括將該晶粒堆疊安裝於一封裝基板上。
  20. 如請求項18之方法，其進一步包括使用一或多個引線接合將該再分配結構電耦合至該封裝基板。
  21. 如請求項15之方法，其中該晶粒堆疊係一第一晶粒堆疊且該等半導體晶粒係第一半導體晶粒，且該方法進一步包括將該路由基板之該下表面耦合至包含複數個第二半導體晶粒之一第二晶粒堆疊。
  22. 如請求項15之方法，其中使用一晶圓級程序來形成該再分配結構。
  23. 如請求項15之方法，其中形成該再分配結構包括形成複數個跡線，該等跡線之至少一些具有不同寬度。
  24. 如請求項15之方法，其中該再分配結構經組態以在該控制器晶粒與該晶粒堆疊之間路由信號。
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