TW201822284A - 半導體裝置及形成３ｄ中介體系統級封裝模組的方法 - Google Patents

半導體裝置及形成３ｄ中介體系統級封裝模組的方法 Download PDF

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TW201822284A
TW201822284A TW106142754A TW106142754A TW201822284A TW 201822284 A TW201822284 A TW 201822284A TW 106142754 A TW106142754 A TW 106142754A TW 106142754 A TW106142754 A TW 106142754A TW 201822284 A TW201822284 A TW 201822284A
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substrate
semiconductor
conductive
semiconductor component
disposed
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TW106142754A
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TWI725262B (zh
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金五漢
梁悳景
李勳擇
尹仁相
一權 沈
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新加坡商星科金朋有限公司
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Abstract

一種半導體裝置係具有一第一基板。一第一半導體構件以及第二半導體構件係被設置在該第一基板上。在某些實施例中，一凹處係被形成在該第一基板中，並且該第一半導體構件係被設置在該第一基板的該凹處上。一第二基板係具有穿過該第二基板所形成的一開口。一第三半導體構件係被設置在該第二基板上。該第二基板係被設置在該第一基板以及第二半導體構件之上。該第一半導體構件係延伸穿過該開口。一密封劑係沉積在該第一基板以及第二基板之上。

Description

半導體裝置及形成3D中介體系統級封裝模組的方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種半導體裝置以及形成3D中介體系統級封裝(SiP)模組的方法。
國內優先權的主張
本申請案係主張2016年12月7日申請的美國臨時申請案號62/431,219的益處，該美國臨時申請案係被納入在此作為參考。
半導體裝置係常見於現代的電子產品中。半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、光電的發電、以及產生用於電視顯示器的視覺影像。半導體裝置係見於通訊、電力轉換、網路、電腦、娛樂、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體封裝可以是由數個主動半導體構件、離散的被動構件、以及整合的被動裝置(IPD)所做成的，其係一起被封裝成為單一封裝的系統，有時是以一系統級封裝(SiP)模組著稱的。相較於傳統的半導體封裝， SiP模組係提供較高的密度以及強化的電性功能。
SiP模組的主動及被動構件係被安裝到用於結構的支撐及電互連的一基板。該基板以及構件係為了環境的保護而被密封。在該封裝的頂表面之密封劑一般係被平坦化以做成一方塊形的封裝。因為該頂表面是橫跨該些裝置而為平坦的，因此該密封劑表面必須是至少和該SiP模組內之最高的構件一樣高的。當較高的構件被使用時，則橫跨該整個裝置，甚至是在較矮的構件之上係需要更多的密封劑。密封劑係被浪費在較矮的構件之上，因而半導體裝置係被做成實際上大於所必須者。因此，對於利用在較矮的構件之上未使用的封裝空間之SiP模組、以及形成的方法係存在著需求。
根據本發明之一特點，其係提出有一種製造一半導體裝置之方法，該方法係包括：提供一第一基板；在該第一基板上設置一第一半導體構件以及第二半導體構件；提供一第二基板；形成穿過該第二基板的一開口；在該第二基板上設置一第三半導體構件；在該第一基板以及第二半導體構件之上設置該第二基板，其中該第一半導體構件係延伸穿過該開口；以及在該第一基板以及第二基板之上沉積一密封劑。
根據本發明的另一特點，其係提出一種製造一半導體裝置之方法，該方法係包括：提供一第一半導體構件；提供一垂直的互連結構；提供一第二基板，其係包含穿過該第二基板所形成的一開口；以及在該垂直的互連結構之上設置該第二基板，其中該第一半導體構件係延伸穿過該開口。
根據本發明的另一特點，其係提出一種半導體裝置，該半導體裝置係包括：一第一基板；被設置在該第一基板之上的一第一半導體構件；被設置在該第一基板之上的一第二基板，其中該第一半導體構件係延伸到該第二基板的一開口中；以及沉積在該第一基板以及第二基板之上的一密封劑。
100‧‧‧半導體晶圓
102‧‧‧基底基板材料
104‧‧‧半導體晶粒
106‧‧‧切割道
108‧‧‧非主動表面
110‧‧‧主動表面
112‧‧‧導電層
114‧‧‧凸塊
118‧‧‧鋸刀(雷射切割工具)
150‧‧‧基板
152‧‧‧切割道
153‧‧‧絕緣材料(絕緣層)
154‧‧‧導電層
154a‧‧‧接觸墊
154b‧‧‧導電線路
156‧‧‧導電層
158‧‧‧導電貫孔
160‧‧‧開口
162‧‧‧離散的裝置
166‧‧‧焊料膏
192‧‧‧鋸刀(雷射切割工具、水切割工具)
196‧‧‧中介體單元
200‧‧‧基板
202‧‧‧切割道
203‧‧‧絕緣層
204‧‧‧導電層
206‧‧‧導電層
206a‧‧‧部分
208‧‧‧導電貫孔
210‧‧‧離散的裝置
212‧‧‧互連結構
214‧‧‧銅核心焊料球(CCSB)
214a‧‧‧非可熔的核心(銅球)
214b‧‧‧可熔的外殼(焊料塗層)
220‧‧‧導電的凸塊
252‧‧‧切割道
256‧‧‧密封劑(模製化合物)
258‧‧‧鋸刀(雷射切割工具、水切割工具)
260‧‧‧SiP模組
266‧‧‧中介體單元
270‧‧‧SiP模組
272‧‧‧導電柱
274‧‧‧焊料蓋
275‧‧‧焊料球
276‧‧‧SiP模組
278‧‧‧SiP模組
280‧‧‧SiP模組
282‧‧‧凹處
284‧‧‧中間的導電層
290‧‧‧底部基板
292‧‧‧開口
294‧‧‧載體
296‧‧‧介面層
298‧‧‧SiP模組
299‧‧‧SiP模組
300‧‧‧SiP模組
302‧‧‧屏蔽層
310‧‧‧SiP模組
402‧‧‧PCB(基板)
404‧‧‧導電層(信號線路)
405‧‧‧電子裝置
406‧‧‧接合線封裝
408‧‧‧覆晶
410‧‧‧球格陣列(BGA)
412‧‧‧凸塊晶片載體(BCC)
416‧‧‧平台柵格陣列(LGA)
418‧‧‧多晶片的模組(MCM)
420‧‧‧四邊扁平無引腳封裝(QFN)
424‧‧‧內嵌的晶圓層級球格陣列(eWLB)
426‧‧‧晶圓級晶片尺寸封裝(WLCSP)
504‧‧‧導電層
圖1a-1c係描繪一半導體晶圓，其中複數個半導體晶粒係藉由切割道來加以分開；圖2a-2d係描繪形成用於系統級封裝(SiP)模組的中介體單元的製程；圖3a-3b係描繪形成用於SiP模組的底部基板；圖4a-4c係描繪利用在該底部基板之上的該中介體單元來形成SiP模組；圖5係描繪完成的SiP模組；圖6a-6b係描繪用於製造SiP模組之替代的製程選項；圖7係描繪SiP模組，其係在該中介體以及底部基板之間具有作為該垂直的互連結構之導電柱；圖8係描繪SiP模組，其係具有作為該垂直的互連結構之焊料球；圖9a-9d係描繪形成SiP模組，其係具有作為該垂直的互連結構之銅球；圖10係描繪SiP模組，其係具有被安裝在內嵌於該底部基板中的接觸墊之上的一電感器；圖11a-11c係描繪形成SiP模組，其係具有在該底部基板的開口中的電 感器；圖12a-12c係描繪在無該底部基板之下形成SiP模組；圖13係描繪SiP模組，其係具有一電磁干擾(EMI)屏蔽層；圖14係描繪SiP模組，其係具有一替代的構件組織；以及圖15a-15b係描繪印刷電路板(PCB)，其中SiP模組係被安裝到該PCB的一表面。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
如同在此所用的術語"半導體晶粒"係指該些字詞的單數及複數形，並且於是可以指稱單一半導體裝置以及多個半導體裝置兩者。如同在此所用的術語"半導體構件"或單純是"構件"係指被形成在半導體晶粒中的主動裝置、利用半導體晶粒所形成的封裝、離散的主動或被動裝置、整合的主動或被動電路、或是任何其它主動或被動電性部件。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動 的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。為了單粒化該些半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來加以劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用導電層、凸塊、柱形凸塊、導電膏、或是引線接合來做成。一密封劑或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電性隔離。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示具有一種例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體材料的基底基板材料102的一半導體晶圓100。複數個半導體晶粒或構件104係被形成在晶圓100上，半導體晶粒104係藉由一非主動的晶粒間的晶圓區域或切割道106來加以分開。切割道106係提供切割區域以將半導體晶圓100單粒化成為個別的半導體晶粒104。在一實施例中，半導體晶圓100係具有一100-450毫米(mm)的寬度或直徑。
圖1b係展示半導體晶圓100的一部分的橫截面圖。每一個半導體晶粒104係具有一背表面或非主動表面108以及一包含類比或數位 電路的主動表面110，該類比或數位電路係被實施為形成在該晶粒內或是之上並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。該些電路係包含一或多個電晶體、二極體、以及其它電路元件，其係被形成在主動表面110內以實施類比電路或數位電路，其例如是一數位信號處理器(DSP)、特殊應用積體電路(ASIC)、記憶體、或是其它的信號處理電路。半導體晶粒104亦可包含例如是電感器、電容器及電阻器之IPD，其係被形成在該半導體晶粒的表面之上的互連層之中或是上之，以用於RF信號處理或是其它目的。在某些實施例中，半導體晶粒104係包含多個主動表面，其中電路係被形成在每一個主動表面中或是上面。
一導電層112係利用PVD、CVD、電解的電鍍、無電的電鍍、或是其它適當的金屬沉積製程而被形成在主動表面110之上。導電層112可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層112係運作為電連接至主動表面110的電路的接觸墊。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程來沉積在導電層112之上。該凸塊材料可以是具有一選配的助熔溶劑的Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料、或是其之一組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或是接合製程而被接合到導電層112。在某些實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊114。在一實施例中，凸塊114係被形成在具有一潤濕層、一阻障層、以及一黏著層的凸塊下金屬化(UBM)之上。 凸塊114亦可被壓縮接合或是熱壓接合到導電層112。凸塊114係代表可被形成在導電層112之上的一種類型的互連結構。該些互連結構亦可包含接合線、導電膏、柱形凸塊、微凸塊、導電柱、或是其它的電互連。
在圖1c中，半導體晶圓100係利用一鋸刀或雷射切割工具118，透過切割道106而被單粒化成為個別的半導體晶粒104。該些個別的半導體晶粒104可以在單粒化之前或是之後加以檢查及電性測試，以用於已知良好的晶粒(KGD)的識別。
圖2a-2d係描繪一種形成中介體單元的製程，該些中介體單元係包含半導體晶粒104以及其它安裝在中介體單元之上的構件，以用於整合在一SiP模組中。圖2a係展示基板150的橫截面圖，其係包含藉由切割道152分開的複數個用於中介體單元的形成的區域。儘管只有兩個用於形成中介體單元的區域被展示，但是基板150在其它實施例中是大許多的，其係具有空間以並行地形成數百個或是數千個單元。基板150係由一種基底絕緣材料153所形成的，其中導電層154及156係被形成在該絕緣層的兩個主要的表面上。在一實施例中，絕緣材料153是一模製基板。在某些實施例中，基板150係利用和複數個導電層交錯的複數個絕緣層153來加以形成，此係容許有更複雜的信號繞線。導電層154及156的部分是電性共通或是電性隔離的，其係根據被形成的SiP模組的設計及功能而定。
導電層154及156可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。導電層154及156係包含複數個接觸墊(例如，接觸墊154a)，其可以藉由被形成為該導電層的部分之導電線路(例如導電線路154b)而被耦接在一起。導電貫孔158係延伸穿過絕緣層153，以將 導電層154的部分電連接至導電層156的部分。導電層154及156係提供橫跨基板150的水平的電互連，而導電貫孔158係提供穿過基板150的垂直的電互連。在一實施例中，導電貫孔158係藉由蝕刻、鑽孔、雷射剝蝕、或是其它適當的製程來提供穿過絕緣層153的一開口，並且接著沉積或是電鍍導電材料到該開口中來加以形成。在某些實施例中，用於導電貫孔158的導電材料係沉積到絕緣層153的開口中，以作為形成導電層154或156的部分。
基板150亦可以是任何適當的積層中介體、PCB、晶圓形式、帶式中介體、引線架、內嵌式線路基板(ETS)、或是其它類型的基板。基板150可包含具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合之一或多個疊層的聚四氟乙烯(PTFE)預浸物(預浸料)、FR-4、FR-1、CEM-1、或是CEM-3。絕緣層153係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、阻焊劑、聚醯亞胺、苯環丁烯(BCB)、聚苯並噁唑(PBO)、或是其它具有類似絕緣及結構的性質之材料。基板150亦可以是一種多層的撓性的積層、陶瓷、銅箔基板、玻璃、或是一包含一主動表面的半導體晶圓，該主動表面係包含一或多個電晶體、二極體、以及其它的電路元件以實施類比或數位電路。
基板150在多個位置處包含孔洞或開口160，其中電感器、或是其它較高的構件將被設置在該SiP模組的覆蓋區之內的一底層基板上。開口160係利用一鋸刀、雷射切割工具、水切割工具、一蝕刻製程、或是其它用於形成一穿過一基板的開口的適當的機構，而穿過基板150來 加以形成。在其它實施例中，基板150係以一種留下穿過該基板的開口160的方式來加以形成，而不須在該基板被製造之後分開地形成一開口，例如是模製絕緣材料153以包含開口160。
圖2b係從圖2a的頂端來描繪基板150的平面圖。導電層154係包含複數個接觸墊154a，其係用於根據需要來表面安裝半導體晶粒以及離散的裝置以實施一給定的電性功能、以及複數個導電線路154b，其係用於根據該SiP模組的設計及功能來互連接該些接觸墊。導電層154可包含用任何適當的方式來藉由導電線路互連的接觸墊的任何所要的數量、形狀、以及佈局。在某些實施例中，導電層156亦包含導電線路以將複數個接觸墊彼此電連接。基板150可以在將半導體晶粒以及其它構件安裝在該基板上之前，在圖2a及2b中可見的目前階段加以測試。
在圖2c中，半導體晶粒104以及離散的裝置162係被表面安裝到導電層154之上。在某些實施例中，基板150係被設置在用於半導體晶粒104以及離散的裝置162的安裝的一載體上。在其它實施例中，基板150係被設置在一夾具中。半導體晶粒104可以在安裝到基板150上之前先被測試是否為KGD，以避免在良好的基板裝置區域上利用到不良的晶粒。此外，基板150的區域可以在安裝構件之前先加以測試，因而該基板的具有製造缺陷的區域可被拋棄，而不會在一不良的基板上浪費KGD。在某些實施例中，不良或空白的半導體晶粒104係被設置在基板150的不良的區域上，以保持橫跨該基板的重量分布均勻，並且有助於控制翹曲。
圖2c係展示基板150的每一個裝置區域係具有兩個離散的裝置162，其可以是電感器、電容器、電阻器、或是其它被動電路構件。離 散的裝置162亦可以是具有主動功能的裝置，例如是功率電晶體、暫態電壓抑制的二極體、等等。在其它實施例中，主動及被動裝置的任意組合可以根據需要而被設置在基板150上，以實施一最終的SiP模組所要的功能。在一實施例中，離散的裝置162係實施一帶通濾波器、或是其它射頻(RF)信號處理網路。在另一實施例中，離散的裝置162係濾波至半導體晶粒104的一電源信號。離散的裝置162可以實施任何所要的電性功能。在某些實施例中，離散的裝置162係結合一最終的SiP模組的其它構件來運作。
離散的裝置162係透過焊料或焊料膏166來機械式地接合及電連接至接觸墊154a。在一實施例中，焊料膏166係被印刷到基板150之上，光學地加以檢查，和實體接觸的離散的裝置162一起加以回焊，並且接著加以去焊。在某些實施例中，離散的裝置162係利用一晶片電容器貼片機(CCM)而從一卷帶來加以分配。離散的裝置162至基板150的連接可以在回焊之後，再次光學地加以檢查。半導體晶粒104係透過導電的凸塊114來機械式地接合及電連接至導電層154。在某些實施例中，凸塊114及焊料膏166係同時被回焊，以在單一步驟中表面安裝所有的構件。
在圖2d中，基板150係利用鋸刀、雷射切割工具、或是水切割工具192，透過切割道152而被單粒化成為複數個中介體單元196。在某些實施例中，經單粒化的中介體單元196係在視覺上加以檢查，並且可被封裝到一卷帶中，以用於儲存以及在之後的製造步驟中的處理。
圖3a-3b係描繪形成一用於SiP模組的底部基板。該製程係在圖3a中開始於一基板200係具有用以形成複數個藉由切割道202分開的底部基板子模組的位置。基板200係類似於基板150，並且可以是以上論述 的各種基板類型的任一種。如同所繪的，基板200係包含一或多個絕緣層203、以及在該基板的相反側上的導電層204及206。導電層204及206的部分係藉由在該些導電層之內的導電線路以及穿過基板200的導電貫孔208來電連接至彼此。如同基板150，底部基板200可以在安裝構件之前先被測試，並且該些構件同樣可以在安裝之前先被測試，以減低浪費。基板200可被設置在一載體上、或是在一夾具中，以用於後續的處理。
在圖3b中，離散的裝置162及210係被表面安裝到基板200之上，並且分別藉由焊料膏166以及互連結構212來電連接至導電層204。類似於以上針對於基板150，焊料膏166係被印刷到導電層204的接觸墊之上，並且接著在離散的裝置162的安裝之前先被檢查。在互連結構212是接觸墊、或是其它具有一高於該焊料膏的回焊溫度的電性端子的實施例中，焊料膏166可被利用於離散的裝置210。在另一實施例中，互連結構212是在離散的裝置210的接觸墊以及導電層204之間被回焊的焊料凸塊。在底部基板200上的離散的裝置162可以是和在中介體單元196上的離散的裝置相同或是不同的，並且可包含任何適當的主動或被動構件。離散的裝置210是具有較離散的裝置162大的高度之構件。離散的裝置210係被描繪為電感器，因為電感器在許多SiP模組中通常是最高的構件。然而，離散的裝置210可以是任何相對於在基板200上的其它構件較高的構件。
銅核心焊料球(CCSB)214係被設置在基板200的導電層204上，以作為垂直的互連結構。CCSB 214係包含一非可熔的核心214a，其係由Cu或是其它可以在遭受到被施加以回焊該可熔的外殼214b的熱時保持固體的材料所形成的。在一實施例中，可熔的外殼214b是一種類似於凸塊 114的焊料材料，並且可以被電鍍或者是塗覆到非可熔的核心214a之上。可熔的外殼214b可以同時和焊料膏166及互連結構212來加以回焊，以在一共同的回焊步驟中將CCSB 214、離散的裝置162、以及離散的裝置210實體及電耦接至基板200。在某些實施例中，在回焊之前，CCSB 214、離散的裝置162、以及離散的裝置210係在基板200上加以光學地檢查。在回焊之後，CCSB 214、離散的裝置162、以及離散的裝置210可以被去焊，並且再次被光學地檢查。在另一實施例中，CCSB 214係被壓縮接合到導電層204。
導電的凸塊220係與離散的裝置162、離散的裝置210、以及CCSB 214相對地被形成在基板200之上的導電層206的接觸墊上。凸塊220係類似於在半導體晶粒104上的凸塊114，並且可以是焊料凸塊、柱形凸塊、導電柱、或是其它適當的互連結構。導電的凸塊220可以在將構件設置於導電層204上之前或是之後加以形成。在某些實施例中，形成導電的凸塊220係在一稍後的製造步驟加以執行。導電的凸塊220係藉由回焊、壓縮接合、或是其它適當的手段而被黏附到導電層206。X射線檢查可被利用以確認用於所有在基板200上的構件之適當的電連接。
圖4a-4c係描繪將基板200以及中介體單元196組合成為SiP模組的一製程。在圖4a中，中介體單元196係被設置在基板200的頂表面之上，亦即在離散的裝置162及210被安裝到其上的基板200的表面之上。若中介體單元196先前是被儲存在一卷帶中，則該些中介體單元可以利用一CCM而被設置在基板200之上。在其它實施例中，中介體單元196係在圖2d中的單粒化之後，從一載體來加以拾取與置放。在另一實施例中，在 基板150並未先被單粒化為個別的中介體單元196之下，基板150係被設置在基板200之上。
開口160係與該些較高的離散的裝置210對準。開口160係容許中介體單元196能夠直接位於CCSB 214上，即使在該些中介體單元以及基板200之間的空間係不足以容納離散的裝置210的整個高度也是如此。離散的裝置210係在中介體單元196的高度之內延伸到開口160中。在某些實施例中，離散的裝置210係延伸超出中介體單元196的頂表面。
CCSB 214的可熔的外殼214b係被回焊，以透過該CCSB來機械式地並且電耦接中介體單元196至基板200。非可熔的核心214a係在可熔的外殼214b的回焊期間維持固體的，以在基板200以及中介體單元196之間維持一偏移。在某些實施例中，導電層156的接觸墊係包含印刷於其上的焊料膏，以改善至CCSB 214的連接。
在圖4b中，一密封劑或是模製化合物256係利用一膏印刷、壓縮模製、轉移模製、液體密封劑模製、真空疊層、旋轉塗覆、或是其它適當的施用器，而沉積在基板200、中介體單元196、半導體晶粒104、離散的裝置162、以及離散的裝置210之上。密封劑256可以是聚合物複合材料，例如是環氧樹脂、環氧丙烯酸酯、或是具有或不具有填充物的聚合物。密封劑256是非導電的，提供結構的支撐，並且在環境上保護該半導體裝置免於外部的元素及污染物。密封劑256係流動在導電的凸塊114之間的半導體晶粒104之下、在焊料膏166之間的離散的裝置162之下、以及在互連結構212之間的離散的裝置210之下，以完全地填入在基板200或中介體單元196與該些半導體晶粒及離散的裝置之間的空間。在其它實施例 中，一個別的底膠填充係被使用於某些構件或是所有的構件。
在某些實施例中，密封劑256係進行一模製後的固化，接著是一選配的雷射標記。被覆蓋密封劑256的基板200以及中介體單元196的組合係形成一面板的SiP模組。在某些實施例中，密封劑256係沉積成超過所必要的厚，並且被背面研磨以降低該密封劑的一厚度。背面研磨係利用化學機械平坦化(CMP)、一蝕刻製程、雷射直接剝蝕(LDA)、或是其它適當的薄化程序來加以執行。
在圖4c中，該面板係利用鋸刀、雷射切割工具、或是水切割工具258，在切割道252之處穿過基板200及密封劑256，而被單粒化成為複數個SiP模組260。在某些實施例中，該面板係穿過中介體單元196的一部分來加以切割。在其它實施例中，該面板係被單粒化成使得密封劑256的一部分係保持在中介體單元196的側表面以及SiP模組260的側表面之間。
在一實施例中，凸塊220並未在沉積密封劑256之前被形成。該被封入的面板可加以翻轉並且設置在一載體上，其中基板200係被定向成遠離該載體，以用於在封入之後並且在單粒化之前的凸塊接合。
圖5係描繪一經單粒化的SiP模組260。SiP模組260可以在烘烤及運送之前先被檢查引線，並且進行其它外部的視覺檢查及測試。導電的凸塊220係被配置以容許SiP模組260能夠安裝到一PCB或是其它具有一較大電子裝置的基板之上，以用於系統整合。在基板200上的離散的裝置162及210係透過導電層204、導電貫孔208、以及導電層206來電耦接至導電的凸塊220。中介體單元196的離散的裝置162以及半導體晶粒 104係藉由導電層154、導電貫孔158、導電層156、CCSB 214、導電層204、導電貫孔208、以及導電層206來耦接至導電的凸塊220。在某些實施例中，導電層154、156、204或206的導電線路係用任何所要的配置，來在SiP模組260的內部將離散的裝置162、離散的裝置210、以及半導體晶粒104彼此電耦接。在一實施例中，在基板200上的離散的裝置162的一或多個端子可以藉由印刷在導電層156上的焊料膏、或是其它互連結構來直接耦接至中介體單元196。
SiP模組260係在單一容易整合的封裝中提供複數個構件，每一個構件都可供該較大的電子裝置使用的。離散的裝置210是一相對高的構件。離散的裝置210係被設置在開口160的一覆蓋區之內，此係容許離散的裝置210以及中介體單元196能夠佔用相同的垂直的尺寸，而不干擾到彼此。離散的裝置210的高度係延伸在中介體單元196的一高度之內。在某些實施例中，離散的裝置210係完全地延伸超過中介體單元196的高度，並且可以延伸至一超過在中介體單元196上的離散的裝置162或半導體晶粒104的頂端之高度。開口160係容許一中介體能夠被使用在較矮的離散的裝置162之上，而不干擾到離散的裝置210的較高的高度。
中介體單元196的使用係容許在SiP模組260之內有額外的構件，而不須增加基板200的覆蓋區。在某些實施例中，離散的裝置210是高到使得中介體單元196可以被添加在較矮的離散的裝置162之上，而不增加SiP模組260的厚度。相對於使得每一個構件在單一基板上散開，電性效能係藉由縮短信號路徑來加以改善。
圖6a及6b係描繪兩種製造變化。在圖6a中，CCSB 214 係最初在中介體單元196的製程期間被設置或是形成在基板150的導電層156上。具有CCSB 214的中介體單元196係被設置在基板200之上，並且接著可熔的外殼214b係透過回焊、壓縮接合、或是其它適當的手段而被接合到導電層204。在某些實施例中，焊料膏係被印刷到在CCSB 214之下的導電層204之上，以改善該連接。用於CCSB 214的焊料膏可以在和用於離散的裝置162的焊料膏166相同的印刷製程期間加以印刷。該結構係如同在圖4b-4c中所繪地被封入及單粒化，以形成一與在圖5中實質相同的SiP模組，但是其係CCSB最初被形成在中介體單元196上，而不是在基板200上。
圖6b係描繪利用取代中介體單元196的中介體單元266來形成SiP模組。中介體單元266係以一種類似於中介體單元196的方式來加以形成。然而，中介體單元266並不是包含穿過該中介體單元所形成的開口160，中介體單元266係被做成具有一相較於基板200的一單元的尺寸較小的覆蓋區。中介體單元266的較小的覆蓋區係容許有空間以供該較高的離散的裝置210被設置在該中介體單元的一覆蓋區之外的基板200上。同樣地，具有中介體單元266的該結構係如同在圖4b-4c中所繪地被封入及單粒化，以形成一類似於在圖5中的SiP模組260的SiP模組，但是其中離散的裝置210係相鄰或是完全地在該中介體單元的一覆蓋區之外，而不是在該中介體單元的一開口中。
圖7是描繪一SiP模組270，其係具有被使用作為該垂直的互連結構的導電柱272，而不是CCSB 214。導電柱272係由Cu、Al、Au、Ag、其它適當的導電材料、或是其之組合所形成的。在一實施例中，導電 柱272係被電鍍到導電層204之上而到一遮罩開口中。焊料蓋274可以藉由沉積焊料或是其它可熔的材料到被用來形成導電柱272的相同的遮罩開口內來加以形成。焊料蓋274係藉由回焊、壓縮接合、或是其它適當的手段而被接合到導電層156。在另一實施例中，導電柱272係被電鍍到導電層156之上，並且接著利用焊料蓋274而被接合到導電層204。
圖8是描繪一SiP模組276，其係利用焊料球275來加以製造，而不是CCSB 214。焊料球275例如是Sn-Pb、Sn-Ag、Sn-Ag-Cu、或是其它適當的焊料組成物之焊料的一均勻的主體。焊料球275係在將中介體單元196附接至基板200時完全地回焊，其係不同於CCSB 214其中只有該外部的外殼214b被回焊。焊料球275並不提供和具有一非可熔的核心的CCSB 214相同程度的間隔功能，但是其對於許多實施例而言是滿足需求的。
圖9a-9d係描繪形成一SiP模組，其係在無該焊料塗層214b之下具有作為該垂直的互連的銅球214a。在圖9a中，焊料或焊料膏166係被印刷或者是設置在導電層204的接觸墊上。焊料膏166係被設置在如上所述用於離散的裝置162的位置處，但是其亦被設置在垂直的互連至中介體單元196是所要的位置處。在某些實施例中，焊料膏166亦被印刷在離散的裝置210將被連接至基板200的位置處。
在圖9b中，離散的裝置162及210係如同在圖3b中地被設置在基板200上。此外，銅球214a係被設置在導電層204的接觸墊上，而在焊料膏166之上。如上所述，銅球214a可以是由銅或是其它並不和焊料膏166被回焊的適當的金屬所形成的。焊料膏166係被回焊以機械式地接 合銅球214a至基板200。
在圖9c中，中介體單元196係被設置在基板200以及銅球214a之上。焊料膏166先前已經在將與銅球214a對準的位置處被設置在導電層156上。焊料膏166係被回焊以接合銅球214a至中介體單元196。該些SiP模組係如上所述地被密封及單粒化，此係產生在圖9d中的SiP模組278。銅球214a係以一種類似於在SiP模組260中的方式被使用，亦即用以提供物理間隔及電互連，但是其係利用一個別的焊料膏166來連接，而不是一焊料塗層214b。
圖10係描繪一SiP模組280，其中離散的裝置210係被設置在基板200的一凹處282中，而在一中間的導電層284上。在圖10中的基板200係在絕緣材料203的層之間、以及在該基板的頂表面及底表面上的導電層204及206之間包含至少一中間的導電層284。中間的導電層284可被利用以藉由包含導電線路作為導電層284的部分，來在導電層204及206之間橫向地佈線電性信號。在某些實施例中，導電層284的部分係位在或是延伸在凹處282的一覆蓋區之外。SiP模組280係用和在以上的SiP模組260實質相同的方式來加以形成，但是其中離散的裝置210係被設置在凹處282中的導電層284上，而不是在導電層204上。
在某些實施例中，凹處282係藉由蝕去上方的絕緣層203以露出該中間的導電層284來加以形成。在其它實施例中，凹處282係完全地延伸穿過絕緣材料203以露出導電層206，因而離散的裝置210係被設置在與導電的凸塊220直接相對的導電層206上。將離散的裝置210設置在一凹處中係降低離散的裝置210的高度，此係在不顯著地增加該SiP模組 的尺寸下容許有較高的離散的裝置210。
圖11a-11c係描繪形成一SiP模組，其中離散的裝置210係被形成在一完全地穿過該底部基板的開口中。圖11a係描繪一底部基板290，其中開口292係在用於較高的離散的裝置210的位置處，穿過該基板來加以形成。基板290係與在以上的基板150及200實質相同的，並且開口292係類似於開口160而穿過該基板來加以形成。基板290係被設置在一具有選配的熱釋放層、雙面膠帶、或是其它介面層296的載體294上。介面層296可包含一黏著的性質，以在處理期間協助保持基板290以及離散的裝置210在適當的地方。在某些實施例中，一帶係被疊層到基板290的底部之上，以在基板290被設置於一夾具中時，將構件保持在開口292中。
離散的裝置210係被設置在開口292中，其中互連結構212係接觸介面層296。當載體294及介面層296之後被移除時，互連結構212以及導電層206的接觸墊係被露出，以用於電互連。在一實施例中，互連結構212是類似於導電層206的那些接觸墊之接觸墊。在另一實施例中，互連結構212是類似於凸塊114的焊料凸塊、或是類似於焊料膏166的焊料膏。如同在以上的基板200，離散的裝置162及CCSB 214係在設置於載體294上之前或是之後被安裝在基板290之上。
同樣如上所述的，中介體單元196係被設置在基板290的單元的每一個之上，並且在圖11b中被密封。載體294以及介面層296係藉由機械式剝離、熱釋放、UV釋放、或是其它適當的機構來加以移除，以露出導電層206以及互連結構212。導電的凸塊220係如同以上地被施加。在 其中互連結構212包含焊料凸塊的實施例中，互連結構212可以和對應的凸塊220一起被回焊，以形成焊料的單一連續的主體。
該面板係穿過密封劑256及基板290而被單粒化以形成在圖11c中的個別的SiP模組298。穿過基板290的開口292係容許一幾乎是和SiP模組298的整個厚度相同的高度之離散的裝置210的使用，而不干擾到基板290或是中介體單元196。同時，其它較矮的構件係彼此被堆疊到兩個個別的基板，亦即基板290及中介體單元196之上，以增加構件密度。
圖12a-12c係描繪在無底部基板之下形成SiP模組。在圖12a中，CCSB 214、離散的裝置162、以及離散的裝置210係全部都被直接設置在載體294及介面層296上。在一實施例中，介面層296的一黏著的性質係被用來將該構件保持在適當的地方。中介體單元196係如上所述地被設置在CCSB 214上。該結構係被封入以形成一面板。該面板係選配地被翻轉到其它載體之上以用於凸塊220的施加，並且接著在圖12b中被單粒化。
圖12c係描繪從在圖12b中的面板被單粒化的SiP模組299。SiP模組299係類似於以上的實施例，但是並不具有一底部基板。導電的凸塊220係直接被設置在CCSB 214、互連結構212、以及焊料膏166上。在某些實施例中，焊料膏166並不存在；離散的裝置162係在無焊料膏166之下直接被設置在介面層296上，並且凸塊220係在載體294的移除之後被直接設置在離散的裝置162的端子上。在某些實施例中，導電的凸塊220係和可熔的外殼214b一起被回焊，以在核心214a的周圍形成一均勻的主體的焊料。
圖13係描繪SiP模組300，其係具有被形成在該封裝之上 的屏蔽層302。SiP模組300係類似於SiP模組260，但是利用一容許屏蔽層302能夠被電鍍在該些封裝之上的製程來加以形成的。在一實施例中，屏蔽層302係在圖4c中的單粒化之後，但是在從一載體移除該SiP模組以用於封裝在一卷帶中之前，被濺鍍在該SiP模組之上。屏蔽層302係選配地透過導電層154的一導電的線路154b來電耦接至一下面的基板的一接地節點，該導電的線路154b係被指定路由至基板150的邊緣以接觸該屏蔽層或是導電層206的一部分206a。屏蔽層302亦可以透過導電層204或156來耦接至一接地節點。屏蔽層302係有助於保護在SiP模組300之內的構件免於由電磁輻射的外部來源所引起的干擾。屏蔽層302亦可被用來降低由來自於該SiP模組外部附近的裝置上的SiP模組300的輻射的干擾。屏蔽層302係與以上或是以下所述的SiP模組的任一者相容的。
離散的裝置162、半導體晶粒104、以及離散的裝置210的實際的佈局並不限於所揭露的實施例。主動及被動構件的任意組合都可被置放在中介體單元196或是基板200的任一者上。圖14係描繪一SiP模組310，其中半導體晶粒104係被設置在底部基板200上，而不是如上所述的在中介體單元196上。在其它實施例中，只有被動裝置係被使用。該些較高的離散的裝置210亦可以是在一SiP模組的覆蓋區之內的任意位置，並且開口160係在對應的位置，穿過中介體單元196而被形成。
圖15a-15b係描繪將上述的SiP模組納入到一電子裝置中。圖15a係描繪來自圖5的SiP模組260被安裝到一PCB或是其它基板402之上以作為一電子裝置的部分的部分橫截面。凸塊220係被回焊到導電層504之上，以實體附接及電連接SiP模組260至PCB 402。上述的SiP模組 的任一者都可以類似地被安裝到PCB 402之上。在其它實施例中，熱壓或是其它適當的附接及連接的方法係被使用。在某些實施例中，一黏著或底膠填充層係在SiP模組260以及PCB 402之間被使用。
半導體晶粒104係透過凸塊114、基板150、CCSB 214、基板200、以及凸塊220來電耦接至導電層404。離散的裝置162及210係透過焊料膏166、互連結構212、基板150、CCSB 214、基板200、以及凸塊220來耦接至導電層404。在某些實施例中，基板150及200係將半導體晶粒104以及離散的裝置162彼此耦接。在其它實施例中，導電層404係將半導體晶粒104、離散的裝置162、以及離散的裝置210彼此耦接。
圖15b係描繪包含PCB 402的電子裝置405，其中包含SiP模組260的複數個半導體封裝係被安裝在該PCB的一表面之上。電子裝置405可以根據應用而具有一種類型的半導體封裝、或是多種類型的半導體封裝。
電子裝置405可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置405可以是一較大的系統的一子構件。例如，電子裝置405可以是一平板電腦、行動電話、數位相機、通訊系統、或是其它電子裝置的部分。電子裝置405亦可以是被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散的主動或被動裝置、或是其它半導體晶粒或電性構件。
在圖15b中，PCB 402係提供一個一般的基板，以用於被安裝在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路 404係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 402的一表面之上、或是在PCB 402的層之內。信號線路404係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統或構件的每一個之間的電性通訊。線路404亦視需要地提供電源及接地連接至該些半導體封裝的每一個。
在某些實施例中，一種半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於機械式及電性地附接該半導體晶粒至一中間的基板的技術。第二層級的封裝係牽涉到機械式及電性地附接該中間的基板至該PCB 402。在其它實施例中，一種半導體裝置可以只有該第一層級的封裝，其中該晶粒係直接機械式及電性地被安裝至該PCB 402。
為了說明之目的，包含接合線封裝406及覆晶408的數種類型的第一層級的封裝係被展示在PCB 402上。此外，數種類型的第二層級的封裝，其包含球格陣列(BGA)410、凸塊晶片載體(BCC)412、平台柵格陣列(LGA)416、多晶片的模組(MCM)418、四邊扁平無引腳封裝(QFN)420、內嵌的晶圓層級球格陣列(eWLB)424、以及晶圓級晶片尺寸封裝(WLCSP)426係和SiP模組260一起被展示安裝在PCB 402。在一實施例中，eWLB 424是一扇出晶圓層級的封裝(Fo-WLP)，並且WLCSP 426是一扇入晶圓層級的封裝(Fi-WLP)。導電線路404係電耦接被設置在基板402上的各種封裝至SiP模組260，以用於接達在該SiP模組之內的構件。
根據系統需求，利用第一及第二層級的封裝類型的任意組合來加以配置的半導體封裝以及其它的電子構件的任意組合可以連接至PCB 402。在某些實施例中，電子裝置405係包含單一附接的半導體封裝，而其 它實施例係需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可以將預製的構件納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，所以電子裝置可以利用較不昂貴的構件以及一精簡的製程來加以製造。所產生的裝置是較不可能失效，而且製造起來是較不昂貴的，此係產生較低的成本給消費者。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於那些實施例可以做成修改及調適，而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一第一基板；在該第一基板上設置一第一半導體構件以及第二半導體構件；提供一第二基板；形成一穿過該第二基板的開口；在該第二基板上設置一第三半導體構件；在該第一基板以及第二半導體構件之上設置該第二基板，其中該第一半導體構件係延伸穿過該開口；以及在該第一基板以及第二基板之上沉積一密封劑。
  2. 如申請專利範圍第1項之方法，其進一步包含：在該第一基板中形成一凹處；以及在該第一基板的該凹處中設置該第一半導體構件。
  3. 如申請專利範圍第1項之方法，其中該第一半導體構件是一電感器。
  4. 如申請專利範圍第1項之方法，其進一步包含在該第一基板以及第二基板之間設置一銅核心的焊料球體(CCSB)。
  5. 如申請專利範圍第1項之方法，其進一步包含在該密封劑之上形成一屏蔽層。
  6. 如申請專利範圍第5項之方法，其進一步包含耦接該屏蔽層至該第一基板或是第二基板的一導電線路。
  7. 一種製造一半導體裝置之方法，其係包括：提供一第一半導體構件； 提供一垂直的互連結構；提供一第二基板，其係包含穿過該第二基板所形成的一開口；以及在該垂直的互連結構之上設置該第二基板，其中該第一半導體構件係延伸穿過該開口。
  8. 如申請專利範圍第7項之方法，其進一步包含：提供一第一基板；在該第一基板上設置該垂直的互連結構；以及在該第一基板上設置該第一半導體構件。
  9. 如申請專利範圍第7項之方法，其進一步包含：提供一第一基板；在該第一基板中形成一開口；在該第一基板上設置該垂直的互連結構；以及在該開口中設置該第一半導體構件。
  10. 如申請專利範圍第7項之方法，其中該第一半導體構件係高於該垂直的互連結構。
  11. 一種半導體裝置，其係包括：一第一基板；一第一半導體構件，其係被設置在該第一基板之上；一第二基板，其係被設置在該第一基板之上，其中該第一半導體構件係延伸到該第二基板的一開口中；以及一密封劑，其係沉積在該第一基板以及第二基板之上。
  12. 如申請專利範圍第11項之半導體裝置，其進一步包含被形成在該密 封劑之上的一屏蔽層。
  13. 如申請專利範圍第11項之半導體裝置，其進一步包含被形成在該第一基板中的一凹處，其中該第一半導體構件係被設置在該凹處中。
  14. 如申請專利範圍第11項之半導體裝置，其進一步包含被設置在該第一基板以及第二基板之間的一垂直的互連結構。
  15. 如申請專利範圍第11項之半導體裝置，其進一步包含被設置在該第一基板以及第二基板之間的一第二半導體構件。
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