TWI722268B - 用於電磁干擾屏蔽的虛設傳導結構 - Google Patents

用於電磁干擾屏蔽的虛設傳導結構 Download PDF

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TWI722268B
TWI722268B TW107102624A TW107102624A TWI722268B TW I722268 B TWI722268 B TW I722268B TW 107102624 A TW107102624 A TW 107102624A TW 107102624 A TW107102624 A TW 107102624A TW I722268 B TWI722268 B TW I722268B
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conductive layer
conductive
layer
pillar
forming
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TW107102624A
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TW201838139A (zh
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尹仁相
蔡昇龍
朴素演
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新加坡商星科金朋有限公司
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Abstract

一種半導體裝置係具有一第一導電層以及一第二導電層。該第一導電層的一第一部分係與該第二導電層的一第一部分對準。一絕緣層係沉積在該第一導電層以及第二導電層之上。一第三導電層係包含與該第一導電層的該第一部分以及該第二導電層的該第一部分垂直地對準的該第三導電層的一第一部分。一電性構件係被設置在該第一導電層以及第二導電層之上。一密封劑係沉積在該第一導電層、第二導電層、以及電性構件之上。一切割係穿過該密封劑、第一導電層、以及第二導電層來加以完成。一第四導電層係沉積在該第一導電層、第二導電層、以及密封劑的側表面之上。

Description

用於電磁干擾屏蔽的虛設傳導結構
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種半導體裝置，其係包含一種形成用於電磁干擾(EMI)的屏蔽的虛設傳導結構之方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、發送及接收電磁信號、控制電子裝置、光電、以及產生用於電視顯示器的視覺影像。半導體裝置係見於通訊、電力轉換、網路、電腦、娛樂、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體裝置通常是易受電磁干擾(EMI)、射頻干擾(RFI)、諧波失真、或是其它裝置間的干擾，例如是電容性、電感性或導電性的耦合(亦以串音著稱)的影響，此可能會干擾到其操作。數位電路的高速的切換亦產生干擾。
導電層通常是被形成在半導體封裝之上，以屏蔽在該封裝之內的電子部件免於EMI及其它干擾。屏蔽層係在信號可能影響在該封裝之內的半導體晶粒及離散的構件之前吸收EMI。某些屏蔽層係透過一封裝基板來電耦接至接地以改善效能。許多的挑戰係存在於利用一簡單的製程來形成一亦具有良好的電連接至接地的屏蔽層上。
根據本發明之一個態樣，其提供一種製造半導體裝置之方法，其係包括：形成一第一導電層；形成一第二導電層，其中該第一導電層的一第一部分係與該第二導電層的一第一部分垂直地對準；在該第一導電層以及第二導電層之上沉積一密封劑；切割穿過該密封劑、該第一導電層的該第一部分、以及該第二導電層的該第一部分；以及在該第一導電層、第二導電層、以及密封劑的側表面之上沉積一第三導電層。
根據本發明之另一個態樣，其提供一種製造半導體晶粒之方法，其係包括：形成一第一導電層；形成一與該第一導電層對準的第二導電層；切割穿過該第一導電層以及第二導電層；以及在該第一導電層以及第二導電層的側表面之上沉積一第三導電層。
根據本發明之另一個態樣，其提供一種半導體裝置，其係包括：一第一導電層；一第二導電層，其係與該第一導電層對準；以及一第三導電層，其係被形成在該第一導電層以及第二導電層的側表面之上。
120‧‧‧半導體晶圓
122‧‧‧基底基板材料
124‧‧‧半導體晶粒(構件)
126‧‧‧切割道
128‧‧‧背表面(非主動表面)
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧導電凸塊
142‧‧‧鋸刀(雷射切割工具)
200‧‧‧載體
202‧‧‧核心基板
204‧‧‧晶種層
206‧‧‧晶種層
210‧‧‧切割道
212‧‧‧導電層
212a‧‧‧導電層
212b‧‧‧導電層
216‧‧‧導電柱
216a‧‧‧導電柱
216b‧‧‧導電柱
220‧‧‧絕緣(鈍化)層
222‧‧‧導電層
222a‧‧‧導電層
222b‧‧‧導電層
222c‧‧‧導電層
226‧‧‧導電柱
226a‧‧‧導電柱
226b‧‧‧導電柱
230‧‧‧絕緣層
232‧‧‧導電層
232a‧‧‧導電層(部分)
232b‧‧‧導電層(部分)
240‧‧‧絕緣(鈍化)層
250‧‧‧封裝基板
252‧‧‧虛設傳導結構
258‧‧‧離散的構件
259‧‧‧焊料膏
270‧‧‧密封劑(成型化合物)
274‧‧‧導電凸塊
274a‧‧‧導電凸塊
274b‧‧‧導電凸塊
280‧‧‧載體
282‧‧‧介面層(雙面帶)
284‧‧‧鋸刀(雷射切割工具)
300‧‧‧半導體封裝
310‧‧‧屏蔽層
312‧‧‧PCB
314‧‧‧接觸墊(信號線路)
316‧‧‧半導體封裝
350‧‧‧電子裝置
356‧‧‧接合導線封裝
358‧‧‧覆晶
360‧‧‧球格陣列(BGA)
362‧‧‧凸塊晶片載體(BCC)
366‧‧‧平台柵格陣列(LGA)
368‧‧‧多晶片的模組(MCM)
370‧‧‧四邊扁平無引腳封裝(QFN)
372‧‧‧四邊扁平封裝
374‧‧‧嵌入式晶圓層級球格陣列(eWLB)
圖1a-1d係描繪一半導體晶圓，其中複數個半導體晶粒係藉由切割道來加以分開的；圖2a-2f係描繪一種形成一具有虛設傳導結構的封裝基板的製程；圖3a-3e係描繪一種利用該封裝基板來形成半導體封裝的製程，其中一屏蔽層係耦接至該虛設傳導結構；圖4係描繪被安裝在一印刷電路板之上的該些半導體封裝中之一； 圖5係描繪具有一透過該封裝基板的導電層至接地的連接的虛設傳導結構；圖6係描繪透過導電凸塊來直接連接至印刷電路板的虛設傳導結構；圖7a-7c係以平面圖來描繪三個範例的虛設傳導結構的佈局；以及圖8係描繪被安裝有不同類型的封裝以及具有虛設傳導結構的半導體封裝的印刷電路板。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。如同在此所用的術語"半導體晶粒"係指單數形及複數形兩者，並且於是可以指稱單一半導體裝置以及多個半導體裝置兩者。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。為了單粒化該些半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來加以劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒 化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用導電層、凸塊、柱形凸塊、導電膏、引線接合、或是其它適當的互連結構來做成。一密封劑或是其它成型材料係沉積在該封裝之上，以提供實體支撐及電性隔離。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示一具有一種例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體材料的基底基板材料122的半導體晶圓120。複數個半導體晶粒或構件124係被形成在晶圓120上，半導體晶粒124係藉由一非主動的晶粒間的晶圓區域或切割道126來加以分開。切割道126係提供切割區域以將半導體晶圓120單粒化成為個別的半導體晶粒124。在一實施例中，半導體晶圓120係具有一100-450毫米(mm)的寬度或直徑。
圖1b係展示半導體晶圓120的一部分的橫截面圖。每一個半導體晶粒124係具有一背表面或非主動表面128以及一包含類比或數位電路的主動表面130，該類比或數位電路係被實施為形成在該半導體晶粒內以及之上並且根據一所要的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。例如，該電路可包含一或多個電晶體、二極體、以及其它的電路元件，其係被形成在主動表面130內以實施類比電路或數位電路，其例如是一數位信號處理器(DSP)、特殊應用積體電路(ASIC)、記憶體、或是其它的信號處理電路。半導體晶粒124亦可包含例如是電感器、電容器及電阻器之整合的被動裝置(IPD)，以用於RF信號處理。IPD在某些實施例中係被形成在主動表面130之上的金屬層中。
一導電層132係利用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解的電鍍、無電的電鍍製程、或是其它適當的金屬沉積製程而被形成在主動 表面130之上。導電層132可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層132係運作為電連接至主動表面130上的電路的接觸墊。
在圖1c中，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程來沉積在導電層132之上。該凸塊材料可以是具有一選配的助熔溶劑的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、或是其之一組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或是接合製程而被接合到導電層132。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成導電球或凸塊134。在一實施例中，導電凸塊134係被形成在具有一潤濕層、一阻障層、以及一黏著層的凸塊下金屬化(UBM)之上。導電凸塊134亦可被壓縮接合或是熱壓接合到導電層132。導電凸塊134係代表可被形成在導電層132之上以用於電連接至一基板的一種類型的互連結構。該些互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊、或是其它的電互連。
在圖1d中，半導體晶圓120係利用一鋸刀或雷射切割工具142，透過切割道126而被單粒化成為個別的半導體晶粒124。該些個別的半導體晶粒124可以在單粒化之前或是之後加以檢查及電性測試，以用於已知良好的晶粒(KGD)的識別。
圖2a係描繪一載體200。載體200係包含一核心基板202以及被形成在該核心基板的相對的表面上的晶種層204及206。載體200的一區域係被保留在裝置形成區域之間，以用於切割道210。核心基板202係包含一或多個具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合之聚四氟乙烯預浸物(預浸料)、FR-4、FR-1、CEM-1、或是CEM-3的疊層的層。在一實施例中，核心基板202是一具有機織物及填充物的複合物。 或者是，核心基板202係包含一或多個絕緣或鈍化層。晶種層204及206係由Cu或是其它適當的導電材料所形成的。在一實施例中，載體200是一銅箔的積層(CCL)。
在圖2b中，一導電層232係利用一圖案化及金屬沉積製程，例如是印刷、PVD、CVD、濺鍍、電解的電鍍、或是無電的電鍍而被形成在晶種層204之上。導電層232係包含一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。在一實施例中，一光阻遮罩層係沉積在晶種層204之上，並且根據用於導電層232的形成所需要地加以圖案化。導電材料係被沉積在該遮罩層的開口中，以在晶種層204上直接形成導電層232。該遮罩通常是在導電層232的形成之後被移除。其它加成、半加成、或是減成的圖案化導電層的方法係在其它實施例中被使用來形成導電層232。
導電層232係包含個別的部分232a及232b。導電層232a係根據所做的封裝的電性功能所需要地被圖案化，使得被形成在載體200之上的基板係適當地互連在該封裝之內的裝置與該封裝將會被安裝到的一PCB或其它基板之間。載體200最終將會被移除，並且導電層232a的接觸墊將會形成用於將被安裝到該基板之上的半導體以及其它電性裝置的接觸墊。因此，導電層232a的接觸墊通常應該被設置在其中互連結構是在該基板與被形成的封裝的子構件之間所要的位置處。導電層232a亦可包含導電線路以運作為一重分佈層(RDL)，因此根據在被形成的封裝基板之內的下一層級的互連所需要的橫向地繞線電連接。
導電層232b是一橫跨切割道210所形成的虛設圖案。導電層232b係被稱為一虛設圖案，因為該導電層並未直接被使用、也不是所形成的裝置的電性功能所必要的。在某些實施例中，導電層232b係與導電層232a電性隔離的。在其它實施例中，導電層232a的某些部分係電耦接至導電層232b，以提供或接收一接地電壓電位。導電層232b係橫跨切割道210而被形成，使得透過該些切割 道的單粒化係導致該虛設圖案的側表面從所形成的基板的側邊露出。導電層232b在單粒化之後的露出的側表面係被用來電連接一屏蔽層。
在圖2c中，導電柱226係被形成在導電層232之上。導電柱226係以一種類似導電層232的方式來加以形成，例如是藉由沉積導電材料到一經圖案化的光阻遮罩中。導電柱226係包含在導電層232a之上的導電柱226a、以及在導電層232b之上的導電柱226b。導電柱226a係運作為在該封裝基板中的導電貫孔，並且從導電層232a垂直地繞線功能電性信號至接著所形成的導電層。
導電柱226b係形成一類似於導電層232b的虛設圖案。在一實施例中，導電柱226b係用實質相同的圖案而被直接形成在導電層232b上並且與導電層232b垂直地對準，以形成具有一致的覆蓋區的虛設結構。導電柱226b係類似於導電層232b來重疊切割道210，以在單粒化該封裝基板時露出該整體虛設結構的一側表面。
在圖2d中，一絕緣或鈍化層240係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、狹縫塗覆、滾筒塗覆、疊層、燒結、或是熱氧化，而被形成在載體200、導電層232、以及導電柱226之上。絕緣層240係包含具有或不具有填充物或纖維的一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、鉿氧化物(HfO2)、苯環丁烯(BCB)、聚醯亞胺(PI)、聚苯並噁唑(PBO)、聚合物介電質光阻、或是其它具有類似結構及介電性質之材料。在其它實施例中，絕緣層240是在一成型製程中所施加的一密封劑。若必要的話，絕緣層240係利用機械式研磨、化學機械平坦化(CMP)、或是其它適當的製程而被平坦化以露出導電柱226，並且產生與絕緣層240的一頂表面共平面的該導電柱的頂表面。在其它實施例中，絕緣層240係利用一膜輔助的成型製程而被施加的，使得導電柱226並未被該成型製程所覆蓋。
一導電層222係被形成在絕緣層240以及導電柱226上。導電層222 係類似於導電層232來加以形成並且操作。導電層222a是導電層222的一部分，其係在操作上連接至之後被設置在該基板上的電路。導電層222a係包含在導電柱226之上的接觸墊，以用於透過該些導電柱來電連接至導電層232a。導電層222a亦包含接觸墊以用於電互連至接著所形成的導電層。在某些實例中，一導電層222a的部分可以作為一用於連接至一導電柱226a的接觸墊，並且亦用於一接著在相同的接觸墊之上所形成的與導電柱226a正好相對的導電柱。
導電層222a係包含導電線路或RDL，以根據所形成的封裝的電性功能所需要地來將該些接觸墊彼此電耦接。導電層222b是導電層222的一虛設圖案部分。導電層222b係被圖案化在導電層232b以及導電柱226b之上，並且與其對準。在某些實施例中，導電層222b係耦接至導電層222a的一部分以提供或接收一接地連接，即如同在以下圖5中所繪者。
在圖2e中，導電柱216係以一種類似先前的導電柱226的形成的方式而被形成在導電層222之上。導電柱216a係被使用於下一層級的互連，而導電柱216b是一被形成在先前所形成的導電層232、導電柱226、以及導電層222的虛設圖案部分之上並且與其對準的虛設圖案。
絕緣層230係以一種類似絕緣層240的方式而被形成在導電層222及導電柱216之上。絕緣層230係覆蓋並且填入在導電層222與導電柱216之間的空間中。若必要的話，導電柱216係藉由機械式平坦化、CMP、化學蝕刻、或是其它適當的製程而被露出。該平坦化製程係留下絕緣層230的一頂表面是與導電柱216的頂表面共平面的。在其它實施例中，膜輔助的成型係被用來在不覆蓋導電柱216的頂表面下施加絕緣層240。
導電層212係被圖案化在絕緣層230及導電柱216的頂表面之上。導電層212a係包含用於容許互連結構能夠被設置在該基板上的接觸墊。導電層212a亦包含用於根據需要的電性信號的橫向的分布的導電線路。導電層212b是 導電層212的一虛設圖案部分，其被形成在導電層232b、導電柱226b、導電層222b、以及導電柱216b之上，並且與其對準。
在圖2f中，絕緣或鈍化層220係沉積在導電層212之上，並且載體200係被移除，以完成封裝基板250。封裝基板250係選配地被翻轉，使得在該封裝之內的電子裝置係被設置在導電層232上，並且導電層212係從最終的封裝露出以用於電互連。絕緣層220係以一種類似絕緣層230及240的方式來加以形成。絕緣層220可以和導電層212一起被平坦化、或是可以被留著完全地覆蓋導電層212。開口係接著藉由雷射直接剝蝕、化學蝕刻、或是其它適當的製程，穿過在導電層212a的接觸墊之上的絕緣層220以露出該接觸墊來加以形成，以用於凸塊接合或是提供另一種類型的電互連。
包含晶種層204的載體200係藉由化學蝕刻、化學機械平坦化(CMP)、機械式研磨、或是其它適當的製程來加以移除，以露出導電層232以及絕緣層240。晶種層204的移除係電性隔離導電層232的各種部分。
封裝基板250係包含具有一陣列形式的複數個封裝形成區域。在圖2f中，兩個封裝形成區域係被展示在三個切割道210之間。但一般而言，遠超過兩個裝置係一次以一個二維陣列而被形成在封裝基板250上。該些封裝形成區域係包含用於電性信號的橫向的分布的導電層212a、222a及232a、以及導電柱216a及226a，以在後續的導電層之間垂直地連接。封裝基板250係用一種扇入、扇出、或是其它配置來從該封裝基板的頂端至底部地繞線電性信號，以運作為用於一半導體封裝的一中介體或是互連基板。
封裝基板250係包含橫跨該封裝基板的切割道210，以任意所要的圖案加以形成的虛設傳導結構252。虛設傳導結構252係由導電層212b、222b及232b以及導電柱216b及226b的對準的部分的一堆疊所構成的。虛設傳導結構252的每一個導電層及導電柱都包含一大致相同的覆蓋區，使得該些虛設傳導結構 整體係大略一致地延伸穿過該整個基板厚度。圖7a-7c係描繪用於虛設傳導結構252的許多可行的圖案中的三個。儘管封裝基板250係被展示具有藉由兩個層級的導電柱連接的三個導電層，但在其它實施例中，任意數量的層係被用來形成一封裝基板。
圖3a-3e係描繪利用封裝基板250來形成一半導體封裝。在圖3a中，半導體晶粒124以及離散的構件258係被安裝到導電層232a的接觸墊之上。離散的構件258可以是離散的被動裝置，例如是電感器、電容器及電阻器、或者可以是離散的半導體構件，例如是二極體或電晶體。焊料膏259係被印刷到其中離散的構件258將被連接的接觸墊之上，並且該些離散的構件以及半導體晶粒124係被設置在封裝基板250之上。熱係被施加以回焊焊料膏259及導電凸塊134。在回焊之後，半導體晶粒124係透過導電凸塊134來機械式地接合且電連接至導電層232a，並且離散的構件258係透過焊料膏259來機械式地接合且電連接至導電層232a。具有相同或不同的功能的額外的半導體晶粒124以及離散的構件258可被設置以實施任意所要的電性功能。在其它實施例中，只有被動構件係被形成且設置在封裝基板250上，而無半導體晶粒124或其它的主動裝置，以例如是形成一射頻(RF)濾波器網路。
在圖3b中，一密封劑或成型化合物270係利用一膏印刷、壓縮成型、轉移成型、液體密封劑成型、真空疊層、旋轉塗覆、或是其它適當的施用器，而被沉積在封裝基板250、半導體晶粒124、以及離散的構件258之上以作為一種絕緣材料。密封劑270可以是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。密封劑270是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。密封劑270亦保護半導體晶粒124免於由於曝露到光的劣化。在圖3c中，導電凸塊274係以一種類似在導電層132上的導電凸塊134的方式而被形成在導電層212的接 觸墊上。
具有半導體晶粒124、離散的構件258、以及密封劑270的封裝基板250係被設置在圖3d中的載體280上。載體280係包含犧牲基底材料，例如是矽、聚合物、鈹氧化物、玻璃、或是其它適當的低成本的剛性材料，以用於結構的支撐。一介面層或是雙面帶282係被形成在載體280之上，以作為一臨時的黏著接合膜、蝕刻停止層、或是熱釋放層。
一旦在載體280上之後，鋸刀或雷射切割工具284係被用來穿過封裝基板250的密封劑270及虛設傳導結構252，以單粒化該面板成為個別的半導體封裝300。穿過虛設傳導結構252的單粒化係留下導電層212b、導電柱216b、導電層222b、導電柱226b、以及導電層232b的側表面全部與密封劑270的一側表面共平面的。虛設傳導結構252係在半導體封裝300的側邊露出。
在圖3e中，一屏蔽層310係利用例如是CVD、PVD、或無電的電鍍的適當的金屬沉積技術，而被施加在半導體封裝300之上。屏蔽層310係覆蓋密封劑270的頂表面及側表面、以及虛設傳導結構252的露出的側表面。該濺鍍或電鍍製程係導致屏蔽層310附著到密封劑270及虛設傳導結構252的表面之上。屏蔽層310係完全地覆蓋半導體封裝300的頂表面以及所有的側表面，以提供用於阻擋EMI的良好的覆蓋。屏蔽層310係電連接至虛設傳導結構252，此係改善該屏蔽層的導電度，因此改進屏蔽的效能。
半導體封裝300係利用例如是一拾放操作而從載體280加以移除。熱或是紫外光可被用來降低介面層282的黏著，此係使得半導體封裝300的移除更容易。半導體封裝300可被封裝以用於例如是用一捲帶來銷售。圖4係描繪半導體封裝300的使用在一PCB或其它基板312上，以作為一電子裝置的部分。PCB 312係包含在該PCB的一表面上的接觸墊314。半導體封裝300係被設置在PCB 312之上，並且導電凸塊274係被回焊以機械式地接合且電連接該半導體封 裝至該PCB。
半導體晶粒124及離散的裝置258係藉由導電層232a、導電柱226a、導電層222a、導電柱216a、導電層212a、以及導電凸塊274，來電連接至彼此、PCB 312、以及在PCB 312上的其它電性構件。該電連接係容許半導體晶粒124以及離散的裝置258的功能能夠和其它半導體封裝的功能一起被整合到一電子裝置中。
虛設傳導結構252係被形成在基板250的切割道之處，並且在單粒化之後座落在半導體封裝300的邊緣以電連接至屏蔽層310。基板250可被形成具有任意數量的堆疊的導電層及絕緣層，其中該些導電層的每一個都單純有一部分留在該切割道之內以用於虛設傳導結構252。屏蔽層310係有助於使得入射在半導體封裝300上的EMI、RFI、以及其它的干擾減少到達半導體晶粒124及離散的裝置258。到達半導體晶粒124的干擾可能會劣化在該半導體晶粒上的主動及被動電路的效能。屏蔽層310係阻擋干擾的一相當大的部分。虛設傳導結構252係藉由提供額外的橫截面區域給電流流動，來增大屏蔽層310的電流處理功能。該被增大的電流處理功能係增加屏蔽層310所阻擋的干擾量。
圖5係描繪一半導體封裝316，其係具有一透過導電層222c而至虛設傳導結構252的選配的接地連接。導電層222c是導電層222的一部分，其係結合虛設部分222b與導電的線路部分222a。屏蔽層310係透過導電凸塊274、導電層212a、導電柱216a、以及導電層222c來電連接至PCB 312上的一接地電壓節點。透過導電層222c的接地連接係改善屏蔽功能。封裝基板250的導電層中的任一個都可被利用以連接虛設傳導結構252至接地，但是只需要單一層來連接即可，因為該虛設傳導結構的全部的層係垂直地連接至彼此。在某些實施例中，多個導電層係將虛設傳導結構252連接至接地。在其它實施例中，虛設傳導結構252的不同的部分係藉由不同的導電層來連接至接地。
圖6係描繪半導體封裝300，其中虛設傳導結構252係利用導電凸塊274b來直接連接至PCB 312上的一接地電壓節點。導電凸塊274b係和導電凸塊274a被形成的同時被形成在導電層212b上，並且被接合到接觸墊314。導電凸塊274係提供虛設傳導結構252一直接的電連接至PCB 312。該透過導電凸塊274b的接地連接係改善屏蔽層310在降低針對於封裝320的干擾上的效能。
圖7a-7c係描繪虛設傳導結構252可被形成所用的圖案之非限制性的選項。圖7a係展示虛設傳導結構252，其係具有被形成在半導體封裝300的每一個角落的部分、以及沿著該封裝的每一側的分開的部分。除了在該封裝內部用於電連接半導體晶粒124、離散的裝置258、以及PCB 312所需的任何部分以外(其並未被描繪在圖7a-7c中)，每一個導電層(包含被用來形成導電柱216及226的導電層)都被圖案化以包含在用於虛設傳導結構252的該些舉例說明的區域的部分。圖7b係描繪在半導體封裝300的整個周圍所形成的虛設傳導結構252。圖7c係描繪只被形成在半導體封裝300的角落處之虛設傳導結構252。虛設傳導結構252亦可以只被形成在半導體封裝300的側邊上、或是具有任意其它所要的圖案。
圖8係描繪具有屏蔽層310的半導體封裝300被整合到一電子裝置350中，該電子裝置350係具有一晶片載體基板或PCB 312，其係具有複數個被安裝在PCB 312的一表面之上的半導體封裝以及半導體封裝300。電子裝置350可以根據應用而具有一種類型的半導體封裝、或是多種類型的半導體封裝。
電子裝置350可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置350可以是一較大的系統的一子構件。例如，電子裝置350可以是一平板電腦、行動電話、數位相機、通訊系統、或是其它電子裝置的部分。或者是，電子裝置350可以是可被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處 理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散的裝置、或是其它半導體晶粒或電性構件。小型化及重量縮減對於欲被市場接受的產品而言是重要的。在半導體裝置之間的距離可被縮短以達成較高的密度。
在圖8中，PCB 312係提供一個一般的基板，以用於被安裝在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路314係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 312的一表面之上、或是在PCB 312的層之內。信號線路314係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統構件的每一個之間的電性通訊。線路314亦視需要地提供電源以及接地的連接至該些半導體封裝的每一個。
在某些實施例中，一種半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於機械式及電性地附接該半導體晶粒至一中間的基板的技術。第二層級的封裝係牽涉到機械式及電性地附接該中間的基板至該PCB。在其它實施例中，一種半導體裝置可以只有該第一層級的封裝，其中該晶粒係直接機械式及電性地被安裝至該PCB。
為了說明之目的，包含接合導線封裝356及覆晶358的數種類型的第一層級的封裝係被展示在PCB 312上。此外，數種類型的第二層級的封裝，其包含球格陣列(BGA)360、凸塊晶片載體(BCC)362、平台柵格陣列(LGA)366、多晶片的模組(MCM)368、四邊扁平無引腳封裝(QFN)370、四邊扁平封裝372、以及嵌入式晶圓層級球格陣列(eWLB)374。在一實施例中，eWLB 374是一扇出晶圓層級的封裝(Fo-WLP)、或是扇入晶圓層級的封裝(Fi-WLP)。依據系統的需求，被配置有第一及第二層級的封裝類型的任意組合的半導體封裝以及其它電子構件的任意組合都可以連接至PCB 312。在某些實施例中，電子裝置350係包含單一附接的半導體封裝，而其它實施例則需要多個互連的封裝。藉由在單一基板 之上組合一或多個半導體封裝，製造商可以將預製的構件納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，所以電子裝置可以利用較不昂貴的構件以及一精簡的製程來加以製造。所產生的裝置是較不可能失效，而且製造起來是較不昂貴的，此係產生較低的成本給消費者。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於那些實施例可以做成修改及調適，而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。
124‧‧‧半導體晶粒(構件)
134‧‧‧導電凸塊
212a‧‧‧導電層
212b‧‧‧導電層
216a‧‧‧導電柱
216b‧‧‧導電柱
220‧‧‧絕緣(鈍化)層
222a‧‧‧導電層
222b‧‧‧導電層
226a‧‧‧導電柱
226b‧‧‧導電柱
230‧‧‧絕緣層
232a‧‧‧導電層(部分)
232b‧‧‧導電層(部分)
240‧‧‧絕緣(鈍化)層
258‧‧‧離散的構件
270‧‧‧密封劑(成型化合物)
274a‧‧‧導電凸塊
274b‧‧‧導電凸塊
300‧‧‧半導體封裝
310‧‧‧屏蔽層
312‧‧‧PCB
314‧‧‧接觸墊(信號線路)

Claims (14)

  1. 一種製造半導體裝置之方法，其包括：形成第一導電層；在該第一導電層之上形成第一導電柱；在該第一導電層和該第一導電柱之上形成第一絕緣層；在該第一絕緣層上形成第二導電層，其中該第一導電層的第一部分係與該第二導電層的第一部分和該導電柱垂直地對準；形成第二導電柱在該第二導電層之上並且垂直地對準該第一導電柱；在該第二導電層和該第二導電柱之上形成第二絕緣層；在該第二絕緣層上形成第三導電層，其中該第三導電層的第一部分是垂直對準該第一導電柱；在該第二絕緣層和該第三導電層之上沉積密封劑；切割穿過該密封劑、該第一導電層的該第一部分、該第一導電柱、該第二導電層的該第一部分、該第二導電柱以及該第三導電層的該第一部份；以及沉積接觸該第一導電層的側表面、該第一導電柱的側表面、該第二導電層的側表面、該第二導電柱的側表面、該第三導電層的側表面以及該密封劑的側表面之第四導電層。
  2. 如申請專利範圍第1項之方法，其進一步包含：形成該第一導電層以包含與該第一部分分開的第二部分；以及形成該第二導電層以包含第二部分，該第二導電層的該第二部分連接該第二導電層的該第一部分至該第一導電層的該第二部分。
  3. 如申請專利範圍第2項之方法，其進一步包含在該第一導電層的該第二部分上設置導電凸塊，其中該導電凸塊係透過該第二導電層來電連接至該第一導電層的該第一部分。
  4. 如申請專利範圍第1項之方法，其進一步包含：在該第一導電層的該第一部分上設置導電凸塊；以及利用該導電凸塊來將該半導體裝置安裝至基板。
  5. 如申請專利範圍第1項之方法，其進一步包含：在該第一導電層以及該第二導電層之上設置電性構件；以及在該電性構件之上沉積該密封劑。
  6. 一種製造半導體裝置之方法，其係包括：形成第一導電層；在該第一導電層上形成導電柱；在該第一導電層和該導電柱上方形成絕緣層；在該導電柱和該絕緣層上形成第二導電層；切割穿過該第一導電層、該導電柱以及該第二導電層；以及在該第一導電層的側表面以及該第二導電層的側表面之上沉積第三導電層。
  7. 如申請專利範圍第6項之方法，其進一步包含形成該第二導電層以包含導電的線路，該導電的線路連接該第一導電層的第一部分及第二部分。
  8. 如申請專利範圍第7項之方法，其進一步包含在該第一導電層的該第二部分上設置導電凸塊。
  9. 如申請專利範圍第6項之方法，其進一步包含在該第一導電層上設置導電凸塊。
  10. 一種製造半導體裝置之方法，其包括：形成第一導電層；在該第一導電層上形成導電柱；在該第一導電層和該導電柱上方形成絕緣層； 在該導電柱和該絕緣層之上形成第二導電層；以及形成接觸該第一導電層的側表面、該導電柱的側表面以及該第二導電層的側表面之第三導電層。
  11. 如申請專利範圍第10項之方法，其進一步包含：在該第一導電層以及該第二導電層之上沉積密封劑；以及在該密封劑的側表面之上形成該第三導電層。
  12. 如申請專利範圍第11項之方法，其進一步包含在該密封劑中的該第二導電層之上設置電性構件。
  13. 如申請專利範圍第10項之方法，其進一步包含形成該第二導電層以包含導電的線路，該導電的線路連接該第一導電層的兩個部分。
  14. 如申請專利範圍第10項之方法，其進一步包含在該第一導電層上形成凸塊。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573590B2 (en) * 2016-10-20 2020-02-25 UTAC Headquarters Pte. Ltd. Multi-layer leadless semiconductor package and method of manufacturing the same
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
KR101982056B1 (ko) * 2017-10-31 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지 모듈
US10600743B2 (en) * 2017-11-08 2020-03-24 Inari Semiconductor Labs Sdn Bhd Ultra-thin thermally enhanced electro-magnetic interference shield package
US10847470B2 (en) * 2018-02-05 2020-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10796976B2 (en) * 2018-10-31 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US11094634B2 (en) * 2018-12-24 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure comprising rigid-flexible substrate and manufacturing method thereof
US10825782B2 (en) * 2018-12-27 2020-11-03 Micron Technology, Inc. Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact
CN111669926B (zh) * 2020-05-22 2021-09-17 台达电子企业管理（上海）有限公司 电磁场收发装置及无线充电装置
US11177223B1 (en) * 2020-09-02 2021-11-16 Qualcomm Incorporated Electromagnetic interference shielding for packages and modules
TWI755861B (zh) * 2020-09-18 2022-02-21 財團法人工業技術研究院 重布線結構及其形成方法
TWI773360B (zh) * 2021-06-03 2022-08-01 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法
CN117525039A (zh) * 2022-07-30 2024-02-06 华为技术有限公司 芯片封装结构及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090256244A1 (en) * 2008-02-05 2009-10-15 Kuo-Hsien Liao Semiconductor device packages with electromagnetic interference shielding

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
SG146460A1 (en) * 2007-03-12 2008-10-30 Micron Technology Inc Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US8350367B2 (en) 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20110156090A1 (en) * 2008-03-25 2011-06-30 Lin Charles W C Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts
US8288792B2 (en) * 2008-03-25 2012-10-16 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/post heat spreader
US7648911B2 (en) * 2008-05-27 2010-01-19 Stats Chippac, Ltd. Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias
KR20100048610A (ko) * 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
JP5324890B2 (ja) * 2008-11-11 2013-10-23 ラピスセミコンダクタ株式会社 カメラモジュールおよびその製造方法
KR101153536B1 (ko) * 2010-06-07 2012-06-11 삼성전기주식회사 고주파 패키지
KR101171512B1 (ko) * 2010-06-08 2012-08-06 삼성전기주식회사 반도체 패키지의 제조 방법
US8709874B2 (en) 2010-08-31 2014-04-29 Advanpack Solutions Pte Ltd. Manufacturing method for semiconductor device carrier and semiconductor package using the same
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
US8623702B2 (en) * 2011-02-24 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
US20130337648A1 (en) * 2012-06-14 2013-12-19 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity
US20140048950A1 (en) * 2012-08-14 2014-02-20 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with embedded semiconductor device and built-in stopper and method of making the same
US9064977B2 (en) * 2012-08-22 2015-06-23 Freescale Semiconductor Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US20140246227A1 (en) * 2013-03-01 2014-09-04 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9337073B2 (en) * 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
US9209154B2 (en) * 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9305911B2 (en) * 2013-12-05 2016-04-05 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication
US9263420B2 (en) * 2013-12-05 2016-02-16 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication
US9355985B2 (en) * 2014-05-30 2016-05-31 Freescale Semiconductor, Inc. Microelectronic packages having sidewall-deposited heat spreader structures and methods for the fabrication thereof
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US20160013076A1 (en) * 2014-07-14 2016-01-14 Michael B. Vincent Three dimensional package assemblies and methods for the production thereof
CN105720031A (zh) 2014-12-03 2016-06-29 恒劲科技股份有限公司 中介基板及其制法
US10388607B2 (en) * 2014-12-17 2019-08-20 Nxp Usa, Inc. Microelectronic devices with multi-layer package surface conductors and methods of their fabrication
US10727082B2 (en) * 2015-08-28 2020-07-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9917100B2 (en) * 2015-11-20 2018-03-13 Sandisk Technologies Llc Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
TW201724423A (zh) * 2015-12-23 2017-07-01 力成科技股份有限公司 扇出型封裝堆疊構造與方法
US9691811B1 (en) * 2016-06-02 2017-06-27 Semiconductor Components Industries, Llc Image sensor chip scale packages and related methods
KR102634389B1 (ko) * 2016-09-07 2024-02-06 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090256244A1 (en) * 2008-02-05 2009-10-15 Kuo-Hsien Liao Semiconductor device packages with electromagnetic interference shielding

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