CN103975427B - 互连衬底的功率管理应用 - Google Patents

互连衬底的功率管理应用 Download PDF

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CN103975427B
CN103975427B CN201280060141.1A CN201280060141A CN103975427B CN 103975427 B CN103975427 B CN 103975427B CN 201280060141 A CN201280060141 A CN 201280060141A CN 103975427 B CN103975427 B CN 103975427B
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conductive structure
interconnection substrate
conductive
edge
circuit node
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CN103975427A (zh
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M·迈克尔
K·H·陈
I·耶尔格维奇
C·江
A·斯特拉塔克斯
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Wal Tai La Semiconductor Co
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Wal Tai La Semiconductor Co
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Abstract

描述了互连衬底在功率管理系统中的各种应用。

Description

互连衬底的功率管理应用
相关申请数据
本申请根据35U.S.C.119(e)要求2011年10月7日提交的名为“Power ManagementApplications of Premolded Substrates”的美国临时专利申请No.61/544945(代理文档No.VOLTP013P)的优先权，出于所有目的通过引用将其全部公开内容并入本文。
技术领域
本发明总体涉及互连衬底，并尤其涉及在功率管理应用中使用的互连衬底。
背景技术
被称为倒装芯片QFN(四边扁平无引线)的半导体封装技术涉及将倒装芯片IC安装到包括从实心铜板蚀刻出的导电迹线的引线框架上。之后，将这一组件埋入到模塑料中，以保护该器件不受环境影响。这种建立倒装芯片IC安装在其上的导电迹线的“减除”方案的局限在于当前的蚀刻技术限制了导电迹线的密度。也就是说，铜蚀刻技术的分辨率限定了相邻导电迹线之间的距离的下限(例如，大约125微米)。这转而又限制了要安装在导电迹线上的器件(例如，倒装芯片IC)上的连接(即，球、凸起或柱)的间距。可以通过降低所蚀刻的铜的厚度获得一定的改善，但是其最终将导致不可接受的可靠性问题，例如，导电迹线和引线框架的易碎性。因而，在引线框架上制造导电迹线的常规方案给将这样的技术用于倒装芯片以及其它具有越来越多的I/O的封装带来了显著的障碍。
采用有机衬底的技术能够实现较高的密度，但是对于很多应用而言其过分的昂贵，而且对于很多极端条件的应用而言或者从产品寿命的角度来看往往是较差的。
发明内容
描述了在功率管理应用中使用的互连衬底。
根据特定类别的实施方式，提供了用于将器件连接至组件的互连衬底，该器件的特征为器件间距，并且该组件的特征为小于约800微米的组件间距。该互连衬底包括多个导电结构，将该导电结构中的每个配置为连接至器件的多个电路节点中的对应的一个。将对应于器件的电路节点中的至少一个电路节点的导电结构与对应于其它电路节点中的至少一个电路节点的导电结构按照交替图案布置在互连衬底中。器件间距是组件间距的大约一半，并且导电结构中的至少一些导电结构的宽度至少约为导电结构中的至少一些导电结构之间的间隔的两倍。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
所述器件的电路节点中的至少一些电路节点对应于一个或多个功率器件的端子；一个或多个功率器件是开关调节器的部分；一个或多个功率器件包括两个功率器件，并且端子包括两个功率节点端子、以及开关端子；将对应于功率节点端子和开关端子的导电结构配置为连接至组件的对应的导电结构。
互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，导电结构中的特定一个导电结构未到达互连衬底的边缘；将未到达互连衬底的边缘的特定导电结构配置为将器件的对应电路节点连接至组件的对应导电结构，该对应导电结构的至少部分位于器件正下方；互连衬底的大部分导电结构都位于器件正下方。
互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，导电结构中的特定一个导电结构至少延伸到互连衬底的边缘。
导电结构中的至少一些具有长度和宽度，并且长度至少是宽度的四倍。
导电结构中的至少一些导电结构中的每个均具有一个或多个位于其上的栓体，其被配置为连接至组件的导电结构；将栓体配置为接纳焊料；栓体包括电镀焊料和预先形成的焊料；栓体中的至少一些是圆形的，并且在导电结构中的至少一些导电结构上具有多个圆形栓体；圆形栓体中的至少一些包括焊球；栓体中的至少一些包括细长栓体。
与器件的电路节点中的第一个电路节点相对应的导电结构沿互连衬底的主平面取向中的第一方向延伸，并使与器件的第一电路节点相对应的导电结构在互连衬底内通过沿第二方向延伸的公共导电结构相互连接，第二方向与互连衬底的主平面取向中的第一方向不平行；互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，并且对应于第一电路节点的导电结构以及公共导电结构未到达互连衬底的边缘；互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，并且将公共导电结构设置在互连衬底的边缘的一部分附近，由此允许将对应于器件的第一电路节点的导电结构连接至组件的单个导电结构；互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，并且将公共导电结构设置在互连衬底的边缘的第一部分附近，互连衬底还包括第二公共导电结构，该第二公共导电结构在互连衬底中连接与器件的电路节点中的第二个电路节点相对应的导电结构，并且该第二公共导电结构设置在互连衬底的边缘的第二部分附近。
将对应于电路节点中的两个或更多电路节点的导电结构设置在互连衬底中的以导电材料的第一宽度间隔比为特征的第一区域中，并将对应于电路节点中的两个或更多电路节点的导电结构设置在互连衬底中的以导电材料的第二宽度间隔比为特征的第二区域中，第二宽度间隔比不同于第一宽度间隔比；器件至少包括开关调节器的一部分，并且设置在互连衬底的第一区域中的导电结构对应于开关调节器的功率级的功率级节点，并且设置在互连衬底的第二区域中的导电结构对应于开关调节器的控制电路的控制电路节点。
器件包括一个或多个功率器件以及相关联的控制电路，并且导电结构中的第一导电结构对应于一个或多个功率器件的端子，并且导电结构中的第二导电结构对应于控制电路的控制电路节点；一个或多个功率器件以及相关联的控制电路是开关调节器的部分。
互连衬底具有用于连接至器件的第一表面，导电结构中的至少一些导电结构的部分暴露于互连衬底的第一表面上，互连衬底还包括多个导电凸起，该多个导电凸起形成在导电结构的暴露部分上，并被配置为与器件相连接；导电凸起包括球、凸起、柱或栓体中的任一个；导电凸起包括直接形成于导电结构上的铜柱；导电凸起包括铜柱，并且铜柱形成于凸起下金属化(UBM)层上，该金属化(UBM)层形成于导电结构上；导电凸起包括铜柱，并且铜柱降低了导电结构的侧向导电性。
互连衬底具有用于连接至器件的第一表面，导电结构中的至少一些导电结构的部分暴露于互连衬底的第一表面上，并且被配置为连接至形成于器件上的导电凸起；导电凸起包括球、凸起、柱或栓体中的任一个。
将导热结构配置为传导来自器件的热量；导热结构中的至少一部分通过互连衬底延伸，从而使来自器件的热量能够传导至组件。
将导电结构中的至少一些配置为将分立的无源电路元件安装到互连衬底上。
导电结构中的至少一些包括促进与互连衬底的插入介质的粘附的结构特征，并且结构特征包括波浪形边缘、锯齿形边缘、之字形边缘、无规则边缘、边缘穿孔或边缘突出中的一个或多个。
按照交替图案布置的导电结构包括分别对应于第一和第二电路节点的细长结构，细长结构具有沿互连衬底中的第一方向的取向，对应于第一电路节点的细长结构与对应于第二电路节点的细长结构相交替；按照交替图案布置的导电结构中的每个导电结构都具有至少是其宽度四倍的长度，对应于第一电路节点的导电结构中的每个都具有位于其上的一个或多个栓体，其处于该导电结构的接近互连衬底的第一边缘的末端，并且对应于第二电路节点的导电结构中的每个都具有位于其上的一个或多个栓体，其处于该导电结构的接近互连衬底的与第一边缘相对的第二边缘的末端，并且在对应于第一电路节点的导电结构上的栓体被配置为连接至组件上的第一导电平面，并且在对应于第二电路节点的导电结构上的栓体被配置为连接至组件上的第二导电平面，第一和第二导电平面相邻并且非重叠。
根据另一类实施方式，将互连衬底提供为将器件连接至组件。互连衬底包括多个导电结构，将导电结构中的每个均配置为连接至器件的多个电路节点中的对应的一个。导电结构中的对应于器件的第一电路节点的一个或多个导电结构在互连衬底中被导电结构中的对应于器件的第二电路节点的一个或多个导电结构包围。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
器件的电路节点中的至少一些电路节点对应于一个或多个功率器件的端子；一个或多个功率器件是开关调节器的部分；一个或多个功率器件包括两个功率器件，并且端子包括两个功率节点端子、以及开关端子；功率节点端子之一包括器件的第一电路节点，并且开关端子包括器件的第二电路节点；将对应于第一电路节点的一个或多个导电结构以及对应于第二电路节点的导电结构中的一个或多个配置为连接至组件的对应的导电结构。
对应于第一电路节点的一个或多个导电结构包括多个导电结构，并且对应于器件的第二电路节点的一个或多个导电结构包括具有多个位于其中的孔的第一导电平面结构，对应于器件的第一电路节点的导电结构被包围在该孔中；包围对应于第一电路节点的导电结构的孔在第一导电平面结构中形成了棋盘式图案；将对应于第一电路节点的导电结构和第一导电平面结构配置为在互连衬底的一侧经由多个导电凸起分别与器件的第一和第二电路节点连接，并还将对应于第一电路节点的导电结构和第一导电平面结构配置为在互连衬底的相对侧分别与组件的第一和第二组件导电平面结构连接；第一和第二组件导电平面结构是相邻并且非重叠的；将第一导电平面结构配置为在第一导电平面结构的边缘与第二组件导电平面结构连接，并将对应于第一电路节点的导电结构配置为连接至所处位置处于基本垂直于互连衬底的主平面取向的方向中的第一组件导电平面结构；对应于第三电路节点的多个导电结构中的每个均在互连衬底中也被包围在第一导电平面结构的孔中的对应的一个孔内。
器件包括开关调节器的至少一部分，并且设置在互连衬底的第一区域中的导电结构中的第一导电结构对应于开关调节器的功率级的功率级节点，并且设置在互连衬底的第二区域中的导电结构中的第二导电结构对应于开关调节器的控制电路的控制电路节点。
互连衬底具有用于连接器件的第一表面，导电结构中的至少一些导电结构的部分暴露于互连衬底的第一表面上，互连衬底还包括形成于导电结构的暴露部分上的并且被配置为与器件连接的多个导电凸起；导电凸起包括球、凸起、柱或栓体中的任一个；导电凸起包括直接形成在导电结构上的铜柱；导电凸起包括铜柱，并且铜柱形成于凸起下金属化(UBM)层上，该金属化(UBM)层形成于导电结构上。
互连衬底具有用于连接至器件的第一表面，导电结构中的至少一些导电结构的部分暴露于互连衬底的第一表面上，并且被配置为连接至形成于器件上的导电凸起；导电凸起包括球、凸起、柱或栓体中的任一个。
将导热结构配置为传导来自器件的热量；导热结构的至少一部分通过互连衬底延伸，从而使来自器件的热量能够传导至组件。
将导电结构中的至少一些配置为将分立的无源电路元件安装到互连衬底上。
导电结构中的至少一些包括促进与互连衬底的插入介质的粘附的结构特征，并且结构特征包括波浪形边缘、锯齿形边缘、之字形边缘、无规则边缘、边缘穿孔或边缘突出中的一个或多个。
根据另一类实现方式，提供了一种封装，其包括器件和互连衬底，该器件包括一个或多个功率器件，该互连衬底用于将器件连接至组件。互连衬底包括多个导电结构，导电结构中的第一导电结构对应于一个或多个功率器件的端子。将器件经由导电凸起安装在互连衬底的导电结构的暴露部分上。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
一个或多个功率器件是开关调节器的部分。
一个或多个功率器件包括两个功率器件，并且端子包括两个功率节点端子、以及开关端子。
第一导电结构中的对应于端子之一的至少一个导电结构在互连衬底中被第一导电结构中的对应于另一个端子的至少另一个导电结构包围。
器件包括与一个或多个功率器件相关联的控制电路，导电结构中的第二导电结构对应于控制电路的控制电路节点。
互连衬底的导电结构中的至少一些具有与之连接的分立无源电路元件；分立无源电路元件包括连接至一个或多个功率器件的端子中的至少一些端子的多个电容器；一个或多个功率器件的第一端子具有与之连接的多个电容器中的两个或更多，两个或更多电容器沿器件的不只一个边缘安装在互连衬底上；将对应于一个或多个功率器件的第一端子的第一导电结构配置为沿互连衬底的第一边缘连接至组件，并且沿互连衬底的不同于第一边缘的第二边缘安装对应于第一端子的一个或多个电容器；连接分立无源元件中的第一个的导电结构未被配置为连接至组件；只有采用器件的测试接口才可访问第一分立无源电路元件，以进行测试；将分立无源电路元件中的一个或多个安装在互连衬底上的导电凸起中的相邻凸起之间；分立无源电路元件包括电容器、电阻器或电感器中的一个或多个。
底部填充材料占据将互连衬底的导电结构连接至器件的导电凸起之间的空间；底部填充材料包括分配的底部填充或模制的底部填充；底部填充材料是至少局部包封器件的包封材料的部分。
将器件安装在器件的第一侧上的互连衬底的导电结构上，器件的与第一面相反的第二侧被露出以供散热；互连衬底还包括导热结构，封装还包括散热器结构，该散热器结构安装在器件的露出的第二侧上，并与互连衬底的导热结构热连接，以促进热量从器件传导至导热结构；导热结构的至少一部分通过互连衬底延伸，并且被配置为连接至组件，由此能够使热量从器件传导至组件；沿互连衬底的与器件相邻的一个或多个边缘设置载体框架的一个或多个部分，散热器结构经由载体框架的部分热连接至互连衬底的导热结构；载体框架在互连衬底上绕器件呈矩形并且连续；载体框架包括处于互连衬底上的围绕器件的一个或多个不连续段；散热器结构包括多个断开的或者局部连接的部分和/或一个或多个孔。
封装还包括第二器件以及第二互连衬底，该第二互连衬底用于经由互连衬底将第二器件连接至组件，第二互连衬底包括多个第二导电结构，并将第二器件经由第二导电凸起安装在多个第二导电结构的暴露部分上，并且将第二互连衬底安装在器件上，其中，多个第二导电结构中的至少一些经由与器件的边缘相邻的第三导电凸起连接至互连衬底的多个导电结构中的一个或多个上；第二器件也包括一个或多个功率器件。
使对应于一个或多个功率器件的端子中的至少一个端子的第一导电结构在互连衬底中与对应于一个或多个功率器件的端子中的至少一个其它端子的第一导电结构按照交替图案布置。
该器件的特征为器件间距，并且组件的特征为小于约800微米的组件间距，并且器件间距是组件间距的大约一半，并且导电结构中的至少一些导电结构的宽度至少约为导电结构中的至少一些导电结构之间的间隔的2倍。
互连衬底具有连接至器件的第一表面和连接至组件的第二表面、以及边缘，导电结构中的至少一些导电结构未到达互连衬底的边缘。
互连衬底具有连接至器件的第一表面和连接至组件的第二表面、以及边缘，导电结构中的至少一些导电结构至少延伸至互连衬底的边缘。
导电结构中的至少一些导电结构具有长度和宽度，并且长度至少是宽度的四倍。
导电结构中的至少一些导电结构中的每个均具有位于其上的一个或多个栓体，其被配置为连接至组件的导电结构；将栓体配置为接纳焊料；栓体包括电镀焊料和预先形成的焊料；栓体中的至少一些是圆形的，并且在导电结构的至少一些上具有多个圆形栓体；圆形栓体中的至少一些包括焊球；栓体中的至少一些包括细长栓体。
对应于端子中的第一个的第一导电结构沿互连衬底的主平面取向中的第一方向延伸，并且使对应于第一端子的第一导电结构在互连衬底中通过沿第二方向延伸的公共导电结构相互连接，第二方向与互连衬底的主平面取向中的第一方向不平行；互连衬底具有用于连接至器件的第一表面和用于连接至组件的第二表面、以及边缘，并且对应于第一端子的第一导电结构以及公共导电结构未到达互连衬底的边缘；互连衬底具有连接至器件的第一表面和连接至组件的第二表面、以及边缘，并且公共导电结构被设置在互连衬底的边缘的一部分的附近，并且被配置为将对应于第一端子的第一导电结构连接至组件的单个导电结构；互连衬底具有连接至器件的第一表面和连接至组件的第二表面、以及边缘，并且将公共导电结构设置在互连衬底的边缘的第一部分附近，互连衬底还包括第二公共导电结构，该第二公共导电结构在互连衬底中连接对应于端子中的第二个端子的第一导电结构，并且第二公共导电结构被设置在互连衬底的边缘的第二部分附近。
将对应于一个或多个功率器件的端子的第一导电结构设置在互连衬底中的以导电材料的第一宽度间隔比为特征的第一区域中，并将对应于与一个或多个功率器件相关联的控制电路的控制电路节点的导电结构中的第二导电结构设置在互连衬底中的以导电材料的第二宽度间隔比为特征的第二区域中，第二宽度间隔比不同于第一宽度间隔比。
将导热结构配置为传导来自器件的热量；导热结构的至少一部分通过互连衬底延伸，并且被配置为连接至组件，由此能够使热量从器件传导至组件。
导电结构中的至少一些包括促进与互连衬底的插入介质的粘附的结构特征，并且该结构特征包括波浪形边缘、锯齿形边缘、之字形边缘、无规则边缘、边缘穿孔或边缘突出中的一个或多个。
使第一导电结构中的对应于一个或多个功率器件的第一端子的至少一个导电结构在互连衬底中被第一导电结构中的对应于一个或多个功率器件的第二端子的一个或多个导电结构包围；第一导电结构中的对应于第二端子的一个或多个导电结构包括第一导电平面结构，该第一导电平面结构具有多个位于其中的孔，对应于第一端子的第一导电结构被包围在孔中；包围对应于第一端子的第一导电结构的孔在第一导电平面结构中形成棋盘式图案；对应于第一端子的第一导电结构和第一导电平面结构被配置为在互连衬底的一侧经由导电凸起的子集分别与第一和第二端子连接，并且还将对应于第一端子的第一导电结构和第一导电平面结构配置为在互连衬底的相反侧分别与第一和第二组件导电平面结构连接；第一导电结构中的至少一些导电结构包括过孔，该过孔能够沿垂直于互连衬底的主平面取向的方向将电流或热量传导至位于器件正下方的组件结构；第一和第二组件导电平面结构是相邻的并且非重叠；将第一导电平面结构被配置为在第一导电平面结构的边缘与第二组件导电平面结构连接，并且将对应于第一端子的第一导电结构配置为连接至第一组件导电平面结构，第一组件导电平面结构处于基本上垂直于互连衬底的主平面取向的方向中；多个第一导电结构中的对应于一个或多个功率器件的第三端子的每个导电结构在互连衬底中也被包围在第一导电平面结构的孔中的对应的一个孔中。
导电凸起包括球、凸起、柱或栓体中的任一个；导电凸起包括铜柱；铜柱直接形成于互连衬底的导电结构上；铜柱形成于凸起下金属化(UBM)层上，该金属化(UBM)层形成于互连衬底的导电结构上；器件包括铜重新分布层(RDL)，并且铜柱直接形成于RDL上；器件包括铜重新分布层(RDL)，并且铜柱形成于凸起下金属化(UBM)层上，该金属化(UBM)层形成于RDL上。
根据另一类实现方式，提供用于将器件连接至组件的互连衬底，其包括多个导电结构。将导电结构中的每个均配置为连接至器件的多个电路节点中的对应一个电路节点。互连衬底的导电结构中的至少一些具有分立无源电路元件，该分立无源电路元件安装在与之连接的互连衬底上。导电结构中的与分立无源元件中的第一个分立无源元件的端子连接的至少一个导电结构仅被配置为连接至器件而非组件。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
将分立无源电路元件中的两个或更多配置为连接至器件的第一电路节点，沿互连衬底的不只一个边缘安装两个或更多分立无源电路元件。
将对应于器件的第一电路节点的导电结构配置为沿互连衬底的第一边缘连接至组件，并将分立无源电路元件中的对应于第一电路节点的一个或多个分立无源电路元件安装到互连衬底的不同于第一边缘的第二边缘上。
将分立无源电路元件中的一个或多个安装在互连衬底上的处于互连衬底的导电结构的露出部分之间的位置上，该露出部分被配置为连接至器件。
分立无源电路元件包括电容器、电阻器或电感器中的一个或多个。
器件包括一个或多个功率器件，导电结构中的至少一些对应于一个或多个功率器件的端子，并且分立无源电路元件包括被配置为连接至一个或多个功率器件的端子中的至少一些端子的多个电容器。
将第一分立无源电路元件和对应的导电结构配置为，在器件、互连衬底和组件连接时，第一分立无源电路元件只有在采用器件的测试接口的情况下才可访问，以进行测试。
根据另一类实现方式，提供了一种用于将器件连接至组件的互连衬底，其包括多个导电结构。将导电结构中的每个导电结构均配置为连接至器件的多个电路节点中的对应的一个。互连衬底的导电结构中的至少一些导电结构具有分立无源电路元件，该分立无源电路元件安装在与之连接的互连衬底上。将分立无源电路元件中的两个或更多配置为连接至器件的第一电路节点。沿互连衬底的不只一个边缘安装两个或更多分立无源电路元件。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
将对应于器件的第一电路节点的导电结构配置为沿互连衬底的第一边缘连接至组件，第一边缘不同于两个或更多分立无源电路元件安装所沿的边缘中的至少一个。
将分立无源电路元件中的一个或多个安装在互连衬底上的处于互连衬底的导电结构的露出部分之间的位置，露出部分被配置为连接至器件。
分立无源电路元件包括电容器、电阻器或电感器中的一个或多个。
器件包括一个或多个功率器件，导电结构中的至少一些导电结构对应于一个或多个功率器件的端子，并且分立无源电路元件包括被配置为连接至一个或多个功率器件的端子中的至少一些端子的多个电容器。
根据另一类实现方式，提供了一种用于将器件连接至组件的互连衬底，其包括多个导电结构。将导电结构中的每个均配置为连接至器件的多个电路节点中的对应的一个。互连衬底的导电结构中的至少一些具有分立无源电路元件，该分立无源电路元件被安装在与之连接的互连衬底上。将对应于器件的第一电路节点的导电结构配置为沿互连衬底的第一边缘连接至组件，并将对应于第一电路节点的分立无源电路元件中的一个或多个安装在互连衬底的不同于第一边缘的第二边缘上。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
将分立无源电路元件中的两个或更多配置为连接至器件的第一电路节点，两个或更多分立无源电路元件沿互连衬底的不只一个边缘安装。
将分立无源电路元件中的一个或多个安装在互连衬底上的处于互连衬底的导电结构的露出部分之间的位置上，该露出部分被配置为连接至器件。
分立无源电路元件包括电容器、电阻器或电感器中的一个或多个。
器件包括一个或多个功率器件，导电结构中的至少一些对应于一个或多个功率器件的端子，并且分立无源电路元件包括被配置为连接至一个或多个功率器件的端子中的至少一些端子的多个电容器。
根据另一类实现方式，提供了一种带凸起器件，其包括含有重新分布层(RDL)的多个导电结构、以及多个铜柱，该多个铜柱直接形成于RDL上而不使铜柱和RDL之间的材料钝化。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
钝化层覆盖RDL，铜柱通过RDL延伸。
铜柱降低了导电结构的侧向导电性。
器件包括集成电路。
带凸起器件包括具有多个端子的一个或多个功率器件；一个或多个功率器件是开关调节器的部分；一个或多个功率器件包括两个功率器件，并且端子包括两个功率节点端子、以及开关端子；铜柱被配置为将一个或多个功率器件的端子连接至衬底的导电结构。
根据另一类实现方式，提供了一种制造器件的方法。在下层衬底的可触及金属化上溅射种晶层。将具有第一图案的第一光致抗蚀剂层设置在种晶层之上。根据第一图案采用种晶层电镀第一导电金属层。将具有第二图案的第二光致抗蚀剂设置在第一导电金属层之上。根据第二图案采用种晶层电镀第二导电金属层。第二导电金属层是在不使第二导电金属层和第一导电金属层之间的材料钝化的情况下形成的。对种晶层进行蚀刻。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
第一和第二导电金属层包括铜。
第一导电金属层包括铜重新分布层(RDL)，并且第二导电金属层包括多个铜柱；在RDL和铜柱之上沉积钝化材料；将焊料电镀在铜柱上。
采用种晶层电镀一个或多个额外的导电金属层。
在施加第二光致抗蚀剂层之前剥离第一光致抗蚀剂层。
第一和第二光致抗蚀剂层是基本同时剥离的。
根据另一类实施方式，提供了一种用于将器件连接至组件的互连衬底。器件包括开关调节器的功率级。功率级具有第一和第二功率节点端子、以及开关端子。互连衬底包括多个导电结构，导电结构中的第一导电结构被配置为连接至第一功率节点端子，导电结构中的第二导电结构被配置为连接至开关端子，并且导电结构中的第三导电结构被配置为连接至第二功率节点端子。在互连衬底中将第一、第二和第三导电结构布置为，当使传导在第一导电结构和第三导电结构之间环流时，由开关调节器的功率级的操作产生的第二导电结构中的电流基本保持恒定。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
第二导电结构中的每个均与第一导电结构中的一个和第三导电结构中的一个相邻；第二导电结构中的每个均具有在该第二导电结构的第一侧的第一导电结构中的一个以及在该第二导电结构的与第一侧相对的相对侧的第三导电结构中的一个。
根据另一类实现方式，提供了一种封装，其包括包含开关电压调节器的功率级的器件，功率级具有第一和第二功率节点端子以及开关端子。封装还包括用于将器件连接至组件的互连衬底。互连衬底包括多个导电结构，导电结构中的第一导电结构连接至第一功率节点端子，导电结构中的第二导电结构连接至开关端子，并且导电结构中的第三导电结构连接至第二功率节点端子。在互连衬底中将第一、第二和第三导电结构布置为，当使传导在第一导电结构和第三导电结构之间环流时，由开关调节器的功率级的操作产生的第二导电结构中的电流基本保持恒定。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
第二导电结构中的每个均与第一导电结构中的一个和第三导电结构中的一个相邻；第二导电结构中的每个均具有在该第二导电结构的第一侧的第一导电结构中的一个以及在该第二导电结构的与第一侧相对的相对侧的第三导电结构中的一个。
根据另一类实现方式，提供了一种带凸起器件，其包括开关电压调节器的功率级，功率级具有第一和第二功率节点端子以及开关端子。带凸起器件还包括布置于其表面上的多个导电凸起，其被配置为便于对开关电压调节器的功率级的第一和第二功率节点端子以及开关端子的外部连接。将导电凸起中的第一导电凸起电连接至第一功率节点端子，将导电凸起中的第二导电凸起电连接至开关端子，并且将导电凸起中的第三导电凸起电连接至第二功率节点端子。对开关稳压器的功率级进行配置，并且对第一、第二和第三导电凸起进行布置，从而在使传导在第一导电凸起和第三导电凸起之间进行环流时，使得由开关调节器的功率级的操作产生的第二导电凸起中的电流基本保持恒定。
这些实现方式可以包括下述特征的任一个，包括它们的任何适当组合、排列或子集：
第二导电凸起的多个子集中的每个与第一导电凸起的多个子集之一以及第三导电凸起的多个子集之一相邻；使第一、第二和第三导电凸起的多个子集中的每个按行布置，第二导电凸起的每一行具有在该第二导电凸起的行的第一侧的一行第一导电凸起以及在该第二导电凸起的行的与第一侧相对的相对侧的一行第三导电凸起。
导电凸起包括球、凸起、柱或栓体中的任一个。
导电凸起包括铜柱；带凸起器件包括铜重新分布层(RDL)以及直接形成于RDL上的铜柱；带凸起器件包括铜重新分布层(RDL)，并且铜柱形成于凸起下金属化(UBM)层上，该金属化(UBM)层形成于RDL上。
导电凸起是细长的。
可以通过参考说明书的其余部分以及附图来实现对本发明的实质和优点的进一步理解。
附图说明
图1示出了互连衬底的具体实现方式。
图2示出了互连衬底的另一实现方式。
图3示出了互连衬底的另一实现方式。
图4示出了可以与互连衬底的具体实现方式一起使用的导电凸起的图案。
图5(a)-5(e)示出了互连衬底的具体实现方式的各种部件以及导电凸起的对应图案。
图6(a)和6(b)示出了互连衬底和安装于其上的对应器件的其它实现方式。
图7和图8示出了具有安装于其上的器件和散热器的互连衬底的实现方式。
图9示出了叠置的互连衬底和器件。
图10(a)-10(c)示出了具有安装于其上的无源部件的互连衬底的具体实现方式的各个方面。
图11示出了在互连衬底的具体实现方式中导电元件的各种实现方式。
图12和13(a)-13(c)示出了可以与各种实现方式一起使用的导电结构。
图14和15示出了互连衬底的具体实现方式的导电元件的具体布置。
具体实施方式
现在将更加详细地参考本发明的具体实施例，其包括发明人所设想的用于实施本发明的最佳方式。在附图中示出了这些具体实施例的示例。尽管本发明是结合这些具体实施例描述的，但是应当理解其并非意在使本发明局限于所描述的实施例。相反，其旨在涵盖可以包含在本发明的由所附权利要求限定的精神和范围内的替代方案、修改和等价方案。在下述说明中，阐述了具体的细节，以提供对本发明的透彻理解。可在没有一些或所有的这些具体细节的情况下实践本发明。此外，为了避免对本发明造成不必要的混淆，可能没有对公知的特征予以详细描述。
采用“添加”技术(例如，将导电迹线电镀到衬底上)制造导电迹线的预模制衬底可以在一些应用中实现适当高的密度(例如，在导电迹线之间大约为40-50微米，并在有些情况下可能低到30微米)。
文中描述的各种预模制衬底的特征在于相对于蚀刻技术的源自于电镀技术的优点的第一组好处和/或相对于常规引线框架的源自于预模制结构的优点的第二组好处。
就电镀对比蚀刻而言，蚀刻迹线相对于电镀迹线在可获得的迹线长宽比方面存在限制。例如，在从铜板的两侧蚀刻时，常规工艺通常只能获得略大于迹线厚度的一半的迹线间间隔。相比之下，一般将电镀视为能够产生高得多的长宽比结构。有很多采用蚀刻获得类似的间隔的方式，但是它们要求仅对薄层进行蚀刻。因而，电镀相对于蚀刻的一个优点是较高的长宽比结构(例如，110um的迹线厚度以及40um的迹线间间隔)。
此外，预模制衬底(其既可以采用蚀刻技术建立，也可以采用电镀技术建立)相对于常规引线框架的优点在于对于预模制衬底而言不需要用于导电迹线的实际框架。也就是说，就常规引线框架而言，必须将中间级的蚀刻迹线连接至框架，该框架使结构保持在一起直到模制为止。这带来了这样的要求，即所有的迹线都要到达器件的边缘，即，不能建立处于器件内部的浮置结构。这使得区域阵列和多行封装的建立非常困难，因为没有办法获得未到达器件边缘的内部浮置导电结构。由于预模制衬底不需要这样的框架，因而它们不受这种方式的限制。
可以采用按照文中的描述实现的预模制衬底实现各种各样的优点，参考下文对具体实施例的描述，这些优点将变得明显。例如，采用蚀刻制造的具有200um厚度的常规引线框架通常将得到具有250um的宽度以及400um的间距的导电迹线。通过比较并且根据文中描述的一个或多个实施例，为获得相同的导电迹线宽度，可以采用电镀在预模制衬底中获得290um的间距；即降低了110um。如果想要使常规引线框架的导电迹线的宽度降至250um以下，蚀刻工艺将导致不具有机械稳定性的结构。例如，如果通过半蚀刻建立这样的结构，则它们将形成在能够延伸多远方面存在限制的悬臂桥。尽管在理论上能够将蚀刻引线框架中的迹线宽度降至125um(由此能够实现275um的间距以及150um的间隔)，但是这样的结构在长度方面严重受限。通过比较，预模制衬底的导电迹线受到模塑料的支撑，导电迹线悬置于该模塑料中并且能够行进大的距离，例如，超过其宽度的四倍。
此外，尽管某些器件(例如，倒装芯片器件)上的间距可以非常低(例如，150um)，但是印刷电路板(PCB)上的间距一般为500um(限制了具有400um的间距的应用)。一般而言，PCB和过孔技术的当前工艺水平不允许使间距降至500um以下而成本又不增大到不可接受的水平(对于大部分应用而言)。这是由于PCB通常是采用蚀刻技术制造的(过孔和外层采用一些添加性电镀)。因而，由于PCB的这种限制，外部器件间距需要保持在500um，同时内部器件间距需要被扇入至任何减小的间距。令人遗憾的是，常规的引线框架技术对内部器件间距存在实际限制，其不能有效地匹配诸如倒装芯片器件的某些器件技术以之为特征的非常低的间距和高I/O量。下文将描述各种实施例，这些实施例将说明预模制衬底相对于这些设计问题的一个或多个优点。
根据一些实施例，预模制衬底的制造可以如下文所述。将载体衬底或载体框架(例如，可以采用钢作为低成本选择)预先电镀上铜薄膜，以促进电镀。将包括在第一层导电迹线顶上的第二层导电迹线(即栓体(stud))电镀到铜上，并且之后在导电迹线和载体上淀积模制材料。之后，将模制材料研磨掉，以露出用于将预模制衬底连接至另一组件(例如，印刷电路板(PCB))的栓体。与用于引线框架形成的常规减除技术形成对照的是，形成这些导电迹线的附加工艺能够在将焊盘放到哪里方面提供灵活性。之后，从组件的另一侧蚀刻掉载体，从而露出嵌入到模制材料中的导电迹线。可选地，将绝缘层淀积在导电迹线之上，之后可以在绝缘层中形成焊盘，在焊盘处要安装到预模制衬底上的带凸起的器件将与预模制衬底导电迹线发生接触。为了获得更多有关可以与本发明的各种实施例一起采用的预模制衬底技术的信息，请参考美国专利公开文本No.2008/0145967，以获取2008年6月19日公开的“Semiconductor Package and Manufacturing Method Thereof”，出于所有目的通过引用将其全部公开内容并入本文。
文中描述的本发明的各种实施例涉及采用诸如预模制衬底的互连衬底与带凸起的半导体封装(例如，倒装芯片，更具体而言是在功率管理应用中采用的带凸起的半导体封装)对接。文中采用的“带凸起的器件”指的是具有跨越器件的表面布置的导电元件(例如，球、凸起、柱等)的阵列的任何半导体器件，导电元件用于与其它器件、板、组件或衬底发生电连接。
图1示出了预模制衬底的导电迹线，所述预模制衬底被配置为与上覆盖的带凸起的器件进行连接，并还与下层PCB上的控制焊盘和导电平面进行连接。根据特定类别的实施例，导电平面表示(例如)开关电压调节器的三个端子，在图1中示出了其中的两个，即，VX平面和地/VSS平面。如图所示，连接至下层导电平面的导电迹线类似于交替或者“交错”的手指。使暴露导电迹线的圆形栓体与下层PCB上的对应导电平面对准。可以采用任何适当的技术(例如球、凸起、柱、糊料等)实现栓体和导电平面之间的连接。
图2示出了另一预模制衬底的导电迹线，该预模制衬底同样被配置为与上覆盖的带凸起的器件进行连接，并还与下层PCB上的控制焊盘和导电平面进行连接。而且，在这一示例中，导电平面表示开关电压调节器的三个端子。然而，与图1相比，栓体是沿导电迹线的长度形成的，并且栓体形成了用于与下层PCB连接的引线指(finger)。此外，与图1所示的相邻导电迹线之间的隔离相比，使图2中的对应于PCB上的同一导电平面的导电迹线(经由水平总线)相互电连接。图3更加清楚地示出了在对模制化合物进行背面研磨之后具有等同的露出栓体的电连接导电迹线。
图3的上部示出了悬置在预模制衬底中的互连的VX导电迹线、互连的VSS导电迹线、以及互连的VDD导电迹线，其中，每一组导电迹线对应于PCB上的将与之连接的导电平面。使每一组导电迹线的垂直指互连的水平总线对于一些实现方式而言可以是有利的，这将允许与互连的导电迹线进行单端子连接。这样的方案也可以是有利的，这是因为如果个别引线或连接发生了故障则能够更好地确保电连接性。
图3的下部示出了形成于导电迹线上的栓体(以引线指的形式)的图案，其将与下层的PCB上的导电平面和焊盘进行直接连接。应当指出，采用球、凸起或柱代替引线可以导致板级可靠性的提高。下文将讨论一些实施例。还应当理解，所有的这些结构(球、凸起、柱、栓体等)也可以形成在隔离的导电迹线上，例如，图1所示的那些导电迹线。图4示出了可以形成于图3的上部所示的结构的导电迹线上的球、凸起或柱的IC焊盘和引脚外布局模式(在这一示例中将VSS标为GND)。可以将球、凸起或柱的这一图案形成在预模制衬底导电迹线、IC器件或两者上。
与这些实施例中的一些相关联的一个优点是在保持与采用更为常规的方案(例如，QFN、BGA、TSOP、J引线、Gull-Wing等)的当前设计类似的覆盖区的同时提高I/O密度的能力。在功率管理集成电路的背景中提高的I/O密度将允许设计者在这样的器件的控制和监测方面具有更高的灵活性，并尤其是使其具有将通往外部空间的I/O与开关电路在同一器件中的能力，这与单独的控制IC形成了对照。此外，可以减小高电流导电迹线(例如，VX、VSS和VDD迹线)之间的间距，电阻和开关损耗也将对应地减小。还可以实现与电迁移相关的改进，因为提高的密度意味着每单位面积具有更多的焊料。由提高的密度带来的更为均匀的功率分布还可以导致更好的热性能。
而且应当认识到，所描述的导电迹线图案和连接结构只是对预模制衬底在功率管理器件和系统的背景下的很多可能的构造和应用进行举例说明的示例。在图5(a)中示出了使迹线上的球、凸起或柱自身发生“交错”的构造的另一示例。如图所示，在VX导电平面中形成岛，用于连接至VDD和VSS/GND的球、凸起或柱。所示出的图案旨在降低内部金属连接电阻，以提高开关半导体元件的总的导通状态电阻(Rdson)。这一方案的目的还在于在采用固态导电平面降低PCB电阻以及提高导热的情况下改进PCB连接。由于焊盘连接较大，其还可以促进PCB安装的组装。为了获得更多有关与本发明的实施例结合使用的用于使导电迹线和/或球、凸起或柱的构造发生交错的技术的信息，请参考2008年12月24日提交的名为“Lead Assembly for a Flip-Chip Power Switch”的美国专利申请No.12/344134，这里出于所有目的通过引用将其全部公开内容并入本文。
图5(b)-5(e)示出了诸如图5(a)所示的交错节点的构造的铜柱凸起和芯片上金属连接的额外细节。在图5(c)中示出了图5(b)的区域A的详细分解透视图，该详细分解透视图示出了区域A中的节点的芯片上金属连接。在图5(d)中示出了图5(b)的区域B的详细分解透视图，该详细分解透视图示出了区域B中的节点的芯片上金属连接。在图5(e)中示出了图5(b)的区域C的详细分解透视图，该详细分解透视图示出了区域C中的节点的芯片上金属连接。如图5(c)-5(e)中的每个所示，金属层3(M3)和凸起下金属(UBM)之间的具有相同电极性并对应于相同的调节器端子的所有层都是通过相互缝合(inter-stitch)连接的。
文中讨论的一些实施例中的导电迹线的交错构造(例如，图1-3)导致了内部迹线的间距的2倍的外部器件间距，即，因为每隔一条迹线才被连接至下层PCB上的同一导电元件。因而，将产生这样的效果，即能够将内部器件间距降至250um，而不会将PCB的外部器件间距推到其典型的500um的极限以下。在根据本发明的实施例所构造的且在导电迹线之间具有40um间隔的预模制衬底中，这将导致210um的迹线宽度。相比之下，常规引线框架技术将需要100um的迹线宽度；这远低于鲁棒结构的建议极限。除了易碎之外，这样的迹线宽度还可能不足以承载电流，并且将导致小到不可接受的器件焊盘宽度(例如，100um)；对于常规引线框架技术而言其远低于当前可接受的可焊宽度。
根据一些实施例，预模制衬底不仅促进了内部器件的I/O部分的扇入，而且还能够实现在I/O部分中建立区域阵列，因而与诸如常规引线框架的外围器件相比允许提高I/O密度。应当指出，还能够利用预模制衬底与印刷电路板的连接性的LGA或BGA变型，来实现这样的实施例。
根据一些实施例，在器件的一侧的公共迹线的共处位置允许放宽PCB间距规则，因为可以使在同一侧上的所有迹线(例如，VX或VSS)与固体导电平面接触，因此消除了对用于这一目的的精细蚀刻以及PCB上的迹线的需求，从而允许未来使间距进一步降至500um以下。此外，这样的设计不需要在PCB焊盘中设置过孔；方案会在回流期间造成问题，因为这样的过孔将陷获焊料气孔，并降低板级可靠性。也就是说，可以设想这样的实施例，其允许使VX、VSS和VDD平面中的过孔位于焊料掩模中的焊料开口之间，该焊料开口被配置为连接至导电迹线、LGA的可焊接区域的迹线、和/或预模制衬底的BGA变型的焊球。过孔允许在器件正下方的PCB中的多个层的连接。这样的方案相对于常规引线框架设计显著提高了过孔密度，由此能够实现较低的电损耗以及从器件封装到板的较好的导热。
可以采用文中描述的适当配置的预模制衬底的功率管理器件和系统的类别的示例包括(例如)2001年8月21日颁发的名为“Flip-Chip Switching Regulator”的美国专利No.6278264的权利要求所描述和涵盖的那些，出于所有目的将其全部公开内容通过引用并入本文。具有很宽的多样性的可以得益于文中描述的具体实施例的其它功率管理器件和系统以及其它带凸起的器件对于本领域技术人员而言也是明显的。
根据特殊的实施例，可以使安装在预模制衬底的导电迹线上的带凸起的器件的背面露出。也就是说，一旦将带凸起的器件安装在预模制衬底上，就可以在除了带凸起的器件的背面之外的所有侧面上对组合结构进行模制，或者可以在所有侧面对其进行包覆模制，接下来将包覆模制的一部分去除(例如，通过蚀刻或研磨)，以露出带凸起的器件的背面。
图6(a)示出了与图1所示的类似的预模制衬底，以及带有安装好的带凸起的器件的预模制衬底的两个替代截面。在所示的示例中，带凸起器件(a)的背面被示为露出。带凸起器件被示为经由铜柱(b)和焊料凸起(c)连接至预模制衬底的导电迹线(d)，但是也可以采用各种其它类型的连接。沿导电迹线的栓体(e)也具有焊料(在这一示例中具有焊球(f)的形式)，从而实现与PCB(未示出)的连接。
如图6(a)(下方器件截面)所示，本发明的实施例可以采用常规底部填充来填充在与带凸起器件的连接之间的空间中。也就是说，一旦附着了带凸起的器件，并且在施加包覆模制之前，施用底部填充材料，该材料在器件下面流动并通过毛细作用填充器件下面的空隙。该底部填充材料可以是任何适当的常规底部填充材料，其非常适合具有高I/O密度以及极精细间距的实现。
可替换地，可以设想这样的实施例，其中，可以采用模制底部填充(图6(a)中上方器件截面)。模制底部填充采用模制材料替代所施用的底部填充材料，该模制材料是采用模制类型工艺引入的。包括在模塑料中的较粗的材料使得所述工艺比施用常规底部填充材料更具有挑战性(尤其是对于极精细间距应用而言)，但是该材料的昂贵程度明显更低。模制底部填充还可有助于可靠性的提高，因为其可以比常规底部填充材料提供更为鲁棒的机械和/或环境保护。图6(b)示出了与图6(a)的上方器件截面类似的另一模制衬底，但是其中迹线上的球、凸起或柱按照与图5(a)中所示的类似的方式交错。
根据图7和图8所示的实施例的种类，将散热器结构连接至所安装的带凸起器件的露出的背面，以提供用于从带凸起器件散除热量的导热通路。图7示出了三种散热器构造，它们提供两维的导热，即，向上通过散热器，以及沿横向通往超出了下面的半导体器件延伸的散热器部分。可以采用集成散热器扩展部作为热和/或电连接。如图7的中间图示所示，可以使散热器向下与PCB进行接触，以促进通过对流经由PCB进行额外的热转移。如图7的底部图示所示，还可以将集成散热器扩展部附着至预模制衬底导电迹线和/或经由栓体和焊接接头附着至PCB。随着单位功率管芯面积和I/O密度的持续增大，这样的实施例可能尤为重要。
根据图8所示的特定的实施例，在蚀刻出来的用于露出悬置于预模制衬底中的导电迹线的窗口的边缘周围保留载体衬底(即，载体框架)的至少一部分。框架在器件周围可以是矩形的并且是连续的，或者可以处于绕边缘的一个或多个不连续的段内，例如，在组件的四个角上，沿一条或多条边等。这一载体框架为PCB提供了额外的热通路，以提高热性能。上面的两个图示示出了这样的实施例，其中，散热器按照与图7所示的实施例类似的方式延伸至载体框架之外。应当指出，也可以将这些散热器扩展部连接至预模制衬底导电迹线和/或PCB，如图7的底部图示所示。底部图示示出了这样的实施例，其中，散热器不延伸到载体框架之外，因此通往PCB的主散热通路要经由载体框架。在所示出的示例中，将载体框架示为连接至PCB地平面。也可以设想具有多个断开的或者局部连接的部分和/或一个或多个孔的散热器结构。这样的结构可用降低应力，否则会由作用于具有连续的散热器的器件上的热膨胀或机械应变而产生这样的应力。
在2010年3月2日提交的名为“Chip-Scale Packaging with Protective HeatSpreader”美国专利申请No.12/716197中描述了可以和本发明的实施例一起使用的散热器结构，出于所有目的将其全部公开内容通过引用并入本文。
可以设想这样的实施例，其中，多个预模制衬底能够实现图9所示的带凸起器件和/或其它有源或无源部件的叠置。顶部图示示出了与两个带凸起器件(具有底部填充)叠置的两个预模制衬底，其中，两个器件之间的电连接是围绕叠置结构中的下方器件的边缘制作的(示出了焊球，但是可以采用任何适当的结构)。中间的图示示出了附加的无源部件(例如，电容器、电阻器、电感器等)。底部图示示出了如上文讨论的模制底部填充的使用。所示出的常规或模制底部填充的使用只是示例。也可以设想这样的实施例，其中，一个预模制衬底/带凸起器件组件可以采用常规底部填充，而另一个则采用模制底部填充。还应当理解，叠置不限于两个组件，即，可以针对具体应用酌情按照文中的描述叠置任意数量的器件和预模制衬底。
图10(a)-10(c)示出了这样一个实施例的不同视图，其中，在管芯的两个边缘上提供在这种情况下为去耦电容器(部件0201)的无源部件，但是仅沿管芯的一个边缘提供用于VDDH和VCC的外部焊盘。图10(a)示出了在上覆盖的管芯1004上的凸起(例如1002)相对于预模制衬底的导电迹线的取向。图10(b)示出了在预模制衬底的导电迹线上的用于连接至下层的PCB的球、凸起或柱(例如，1022)的图案。图10(c)示出了下层的PCB的VX、VDDH和VSS/GND导电区域相对于导电平面要连接的预模制衬底的导电迹线上的球、凸起或柱(例如，1022)以及通往PCB的内层的过孔的取向。
在管芯的两个边缘都具有VDDH到VCC(或模拟VDD)电容器的优点在于通过将电容器连接到讨论中的管芯时产生的杂散电感限制了生效的高频解耦。在高电流要求芯片当中杂散电感开关损耗是重要的，因为其将带来LI^2f的开关损耗，该损耗在1Mhz的开关频率上将使得1nH相当于1mOhm的损耗。与在管芯的一个边缘上具有一个电容器相比，在管芯的两个边缘上具有两个电容器将杂散电感切割成一半。可以通过在封装的两个边缘上放置用于VDDH和VCC的外部焊盘来实现相同的效果，但是这将限制用于将调节器的开关节点从管芯中路由出的位置。以该方式，在采用内部路由在管芯的两个边缘上提供解耦的同时，使外部路由局限于在封装的一个边缘上具有VDDH和VCC并且在封装的另一个边缘上具有开关节点VX。此外，还可以使自举(BST)和驱动器去耦电容器共同处于相同的边缘上，以作为高频去耦电容器。将这些电容器集成到封装内部能够潜在地消除对用于这些封装外的连接的I/O的需求(除了使这些连接可为自动测试所触及的需求之外)。因而，可以在内部I/O上提供VCC驱动器电源和VBST－升压电源的路由，该内部I/O不要求可在PCB上路由，而只要求能够在自动化测试期间可访问。集成任何种类的电容器都是有利的，即使它们只处于管芯的一侧上，这是因为相对于PCB安装的电容器而言降低了相对于该电容器的杂散电感，与图示的结构相比，该PCB安装的电容器将在物理上离得更远(相距常规引线框架的厚度)。文中描述的预模制衬底的实施例由于其内部路由的灵活性而允许在管芯的两侧都集成电容器。这些预模制衬底提供了相对于常规引线框架的优点，因为能够降低较精细的间距管芯与导电迹线/引线的支撑体(standoff)，并且电容器可以更小，因而允许实现绕过器件的用于电容器的较低电感连接。最终，电感在一定程度上是由在使环路闭合时电流行进的距离以及该环路内的返回通路之间的距离来定义的。具有30-40um的间距的预先电镀迹线额外地促进了管芯和电容器之间的杂散电感的降低，因为高频电流将沿最近的可能路径行进(即，导体的表面)，并因而导体的间隔将不可避免地规定连接的杂散电感。而且，尽管在器件的边缘处示出了集成的无源部件，但是应当理解，可以设想这样的实施例，其中，可以将无源部件集成在柱之间(例如，在图6(a)-9所示的结构的任何一个当中所示的柱之间)的此类结构中，从而进一步降低电感。
尽管只示出了集成的电容器，但是可以将诸如电阻器的无源部件集成到同一封装中，并因而与管芯上电阻器相比能够更容易地为芯片建立精确的参考。这样的离开管芯(off-die)的电阻器可以具有可控温度系数，然而其温度可以与管芯温度密切相关，因为它们是接近管芯共同封装的。而且，这些内部电阻器可以仅在ATE测试期间可访问，或者无论怎样都不可由ATE访问，而是要通过管芯－ATE测试接口访问。
由于预模制衬底中的导电迹线之间的距离变小，因而迹线的金属(例如，铜)和迹线悬置于其内的模塑料之间的粘附力可能变成可靠性问题。因此，可以设想这样的实施例，其中，通过控制迹线的厚度、迹线的宽度和/或迹线彼此之间的距离而改善或优化这一粘附力。此外，根据一些实施例，可以在迹线和栓体内引入各种促进粘附的结构特征。图11示出了这样的结构特征的示例。在左手边的图示中，用于将预模制设备连接至PCB的迹线和栓体都是波浪形的，以提高不同材料对接处的表面积量。在右手侧的图示中，使波浪形迹线与直栓体结合。多种多样的其它迹线变化(例如，锯齿形、之字形、无规则、边缘穿孔、边缘突起等等)可以适用于各种实现方式。一些结构特征的另一优点在于，它们可以起到避免模制材料中的裂缝沿材料传播的作用。也就是说，导电迹线和栓体的结构特征可以提供起到“止裂”作用的端接点。
根据特定的实施例，带凸起器件(例如，要安装到预模制衬底中的导电迹线上的倒装芯片)上的外部连接是如图12以及图13(a)-13(c)所示的铜柱结构。应当指出，也可以在预模制衬底的导电迹线上形成这样的结构。传统上，这样的结构的制造涉及一系列处理步骤，通过这些步骤能够在管芯焊盘开口之上或者在预先形成于管芯焊盘开口之上的铜条重新分布层(RDL)上引入“凸起下金属化”或UBM，如图12中所示。之后，形成再钝化(例如，聚酰亚胺(PI))，随后以溅射步骤来形成促进电镀的UBM。之后，在UBM上电镀柱形结构。除了需要一定数量的处理步骤之外，该方案还对柱的宽度设置了限制(例如，由于配准容差的原因等)，对于一些应用而言，这可能是不合适的。因此，根据特定的实施例，提供无需UBM而直接在RDL铜上形成铜柱的处理，或者提供直接在器件焊盘开口上形成铜柱的处理(用或不用UBM)。
图13(a)和13(b)示出了直接形成于RDL铜上的铜柱结构，其去除了包括UBM的形成的工艺步骤(因为可以将铜柱容易地电镀到RDL铜上)。尽管如图13(b)所示，但也可以避免钝化的形成，可以在随柱的形成之后形成钝化(即，PI层)，以抑制氧化以及任何相关问题。
图13(c)示出了直接形成于通往器件的顶部金属层的焊盘开口上的铜柱结构，而没有常规技术中所需的再钝化层(例如，参考图12的PI)，也没有其它实施例中所示的RDL铜。例如，在器件的Rdson充分低的实现方式中，例如，在图5所示的实现方式中，RDL的消除可以是可行的。应当认识到，直接在焊盘开口上形成柱允许利用整个焊盘开口形成所述柱而不存在钝化的侵入。在所示的实施例中，示出了UBM，因为可能有必要促进柱结构与器件的顶部金属层的粘附。但是，也可以设想可不需要UBM的实施例。应当理解，可以任选在形成柱之后施加钝化，如图13(b)中所示。
根据具体的过程，可以根据下述顺序来制造图12的结构：
a.溅射Ti种晶层
b.溅射薄的铜种晶导电层
c.放置光致抗蚀剂
d.电镀图案化铜
e.剥离光致抗蚀剂
f.采用电镀的铜作为掩模剥离种晶层
g.放置聚酰亚胺(PI)
h.光曝光
i.建立开口
j.使PI固化
k.溅射Ti种晶
l.溅射Cu导电种晶
m.放置光致抗蚀剂
n.电镀铜柱图案
o.电镀焊料
p.剥离光致抗蚀剂
q.蚀刻种晶
上面的厚铜的存在降低了底部上的厚铜的要求，因而能够使铜更薄(3um而不是12um)，并当铜正分路出通常不厚于1um的内部金属层时，仍然能够获得大的电气优点。
在用于制造图13(a)的结构的替代工序流程中，省略了几个步骤，因为最终的封装是模制的。这些步骤的省略(上文描述的工序流程的g-l)产生了下述流程：
a.溅射Ti种晶层
b.溅射薄的铜种晶导电层
c.放置第一光致抗蚀剂
d.电镀图案化铜
e.放置干掩模的第二光致抗蚀剂
f.电镀铜柱
g.电镀焊料
h.剥离两个光致抗蚀剂
i.蚀刻单一种晶
应当认识到，这一方案相对于较早描述的流程省略了很多处理步骤，因而降低了成本。可以采用按照上述流程中的描述所实现的铜柱或者采用在2010年7月27日提交的名为“Wafer-Level Chip Scale Package”的美国专利申请No.12/844649中描述的焊料棒结构使得预模制衬底中的导电迹线更加导电，出于所有目的通过引用将所述专利申请的全部公开内容并入本文。铜与迹线串联，因而用于有效地降低迹线的侧向导电性。可以按照2008年12月23日提交的名为“Flip Chip Power Switch With under Bump MetallizationStack”的美国专利申请No.12/343372中的描述来实现铜柱下的RDL路由，出于所有目的通过引用将其全部公开内容并入本文。可以按照2008年12月23日提交的名为“ConductiveRoutings in Integrated Circuits Using Under Bump Metallization”的美国专利申请No.12/343261中的描述来实现由不同的电源轨构成的交错行之间的管芯上连接，出于所有目的通过引用将其全部公开内容并入本文。
应当指出，可以采用各种各样的适于具体应用的构造实现根据各种实施例制造的预模制衬底。例如，就预模制衬底中的专用于开关电压调节器的端子中的相应端子的导电迹线而言，文中描述的一些实施例具有相对非均衡的构造。例如，参见图1-5，其中，对应于VSS/GND的导电迹线在数量上明显超过专用于Vin(VDDH)的导电迹线。这归因于这样的事实，即，这些设计是针对低占空比应用而设计的，在该低占空比应用中，调节器的低压侧开关的导电时间比高压侧开关的导电时间长。但是，可以根据与占空比大得多的、更为均衡的构造一起使用的本发明的实施例来制造预模制衬底。图14示出了一种这样的平面布置图构造，其中，VDDH和VSS/GND迹线的相应数量更加均衡。在名为“Lead Assembly for a Flip-Chip Power Switch”的美国专利申请No.12/344134中描述了可以采用预模制衬底的更为均衡的构造的其它示例，通过上述引用对其进行参考并将其并入本文。例如，参见该申请的图9和图10。在美国专利No.6278264中提供了可以针对其构造预模制衬底的更为均衡的平面布置图的其它示例，通过上述引用对该美国专利No.6278264进行参考并将其并入本文。例如，参见该专利的图3以及图8A-8G。此外，可以设想其它实施例，其中，高压侧开关的导电时间长于低压侧开关的导电时间。因此，本发明的范围不应比照文中公开的具体构造而受到限制。
图15示出了可以采用根据本发明的实施例设计的预模制衬底的又一平面布置图，所述预模制衬底包括按照VDDH/VX/GND/VX模式交替的导电迹线行。VX导电迹线与在下层PCB的一侧的整个VX平面连接。VDDH导电迹线与在PCB的另一侧的具有如图所示的形状的VDDH平面连接。采用过孔到达PCB的内层。图15所示的构造的一个优点在于零“电流换流损耗”。也就是说，不管是高压侧开关还是低压侧开关导电，总是有相同的电流流经VX迹线，在使传导从一个换流到另一个时，该电流不发生变化。这与其它设计形成了对照，在其它设计当中，电流必须通过VX迹线“重新分配”，所述VX迹线在存在杂散电感的情况下将导致开关的一些部分具有延迟的导通时间，从而导致更高的电阻以及对应的损耗。
尽管已经参考本发明的具体实施例对本发明进行了详尽的图示和描述，但是本领域技术人员应当理解，在不背离本发明的精神和范围的情况下可以对所公开的实施例做出形式和细节方面的变化。例如，文中描述的各种结构和技术可以由各种封装技术和衬底结构相兼容，因此保护范围不应比照具体的技术或结构而受到限制。可以实践本发明的各种实施例的其它技术和结构的示例包括但不限于以色列的MCL公司的ALOX衬底技术、加利福尼亚的雷德伍德市的EoPlex技术公司的xLC衬底技术、开曼群岛的ASM Pacific技术公司的DreamPAK衬底技术、新加坡的United Test and Assembly Center公司(UTAC)的高密度引线框架阵列(HLA)技术、以及中国东莞的ASAT公司(现在为香港的UTAC母公司Global A&TElectronics公司所有)的热无引线阵列(TLA)技术。
最后，尽管文中参考各种实施例讨论了本发明的各种优点、方面和目的，但是应当理解本发明的范围不应对照这样的优点、方面和目的而受到限制。相反，本发明的范围应当参照所附权利要求来确定。

Claims (15)

1.一种用于将器件连接至组件的互连衬底，所述器件的特征为器件间距，而所述组件的特征为小于约800微米的组件间距，所述互连衬底包括：
多个导电结构，每个所述导电结构被配置为连接至所述器件的多个电路节点中的对应的一个电路节点；
其中，对应于所述器件的电路节点中的至少一个电路节点的导电结构与对应于电路节点中的至少一个其它电路节点的导电结构按照交替图案布置在所述互连衬底中；并且
其中，所述器件间距是所述组件间距的大约一半，并且其中，所述导电结构中的至少一些导电结构的宽度至少约为所述导电结构中的所述至少一些导电结构之间的间隔的两倍。
2.根据权利要求1所述的互连衬底，其中，所述器件的电路节点中的至少一些电路节点对应于一个或多个功率器件的端子，并且其中，所述一个或多个功率器件是开关调节器的部分。
3.根据权利要求1所述的互连衬底，其中，所述互连衬底具有用于连接至所述器件的第一表面、用于连接至所述组件的第二表面、以及边缘，所述导电结构中的特定导电结构未到达所述互连衬底的边缘。
4.根据权利要求3所述的互连衬底，其中，未到达所述互连衬底的边缘的所述特定导电结构配置为将所述器件的对应的电路节点连接至所述组件的对应的导电结构，所述对应的导电结构的至少一部分处于所述器件的正下方。
5.根据权利要求1所述的互连衬底，其中，所述互连衬底具有用于连接至所述器件的第一表面、用于连接至所述组件的第二表面、以及边缘，所述导电结构中的特定导电结构至少延伸到所述互连衬底的边缘。
6.根据权利要求1所述的互连衬底，其中，所述导电结构中的至少一些导电结构具有长度和宽度，并且其中，所述长度至少是所述宽度的四倍。
7.根据权利要求1所述的互连衬底，其中，所述导电结构中的至少一些导电结构中的每个都具有位于其上的一个或多个栓体，所述栓体被配置为连接至所述组件的导电结构。
8.根据权利要求1所述的互连衬底，其中，与所述器件的电路节点中的第一电路节点相对应的导电结构沿所述互连衬底的主平面取向中的第一方向延伸，并且其中，与所述器件的所述第一电路节点相对应的导电结构在所述互连衬底中通过沿第二方向延伸的公共导电结构相互连接，所述第二方向不与所述互连衬底的主平面取向中的第一方向平行。
9.根据权利要求8所述的互连衬底，其中，所述互连衬底具有用于连接至所述器件的第一表面、用于连接至所述组件的第二表面、以及边缘，并且其中，与所述第一电路节点相对应的导电结构和所述公共导电结构未到达所述互连衬底的边缘。
10.根据权利要求8所述的互连衬底，其中，所述互连衬底具有用于连接至所述器件的第一表面、用于连接至所述组件的第二表面、以及边缘，并且其中，所述公共导电结构设置在所述互连衬底的边缘的一部分附近，由此允许将与所述器件的所述第一电路节点相对应的导电结构连接至所述组件的单个导电结构。
11.根据权利要求8所述的互连衬底，其中，所述互连衬底具有用于连接至所述器件的第一表面、用于连接至所述组件的第二表面、以及边缘，并且其中，所述公共导电结构设置在所述互连衬底的边缘的第一部分附近，所述互连衬底还包括第二公共导电结构，所述第二公共导电结构在所述互连衬底中连接与所述器件的电路节点中的第二电路节点相对应的导电结构，并且其中，所述第二公共导电结构设置在所述互连衬底的边缘的第二部分附近。
12.根据权利要求1所述的互连衬底，其中，与所述电路节点中的两个或更多电路节点相对应的导电结构设置在所述互连衬底的第一区域中，所述第一区域的特征为导电材料的第一宽度间隔比，并且其中，与所述电路节点中的两个或更多电路节点相对应的导电结构设置在所述互连衬底的第二区域中，所述第二区域的特征为所述导电材料的第二宽度间隔比，所述第二宽度间隔比不同于所述第一宽度间隔比。
13.根据权利要求12所述的互连衬底，其中，所述器件至少包括开关调节器的一部分，并且其中，设置在所述互连衬底的第一区域中的导电结构对应于所述开关调节器的功率级的功率级节点，并且其中，设置在所述互连衬底的第二区域中的导电结构对应于所述开关调节器的控制电路的控制电路节点。
14.根据权利要求1所述的互连衬底，其中，所述器件包括一个或多个功率器件以及相关联的控制电路，并且其中，所述导电结构中的第一导电结构对应于所述一个或多个功率器件的端子，并且其中，所述导电结构中的第二导电结构对应于所述控制电路的控制电路节点。
15.根据权利要求1所述的互连衬底，其中，所述互连衬底具有用于连接所述器件的第一表面，所述导电结构中的至少一些导电结构的部分暴露在所述互连衬底的所述第一表面上，所述互连衬底还包括多个导电凸起，所述多个导电凸起形成在导电结构的暴露部分上，并且被配置为与所述器件连接。
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