TW201322840A - 互連基板之功率管理應用 - Google Patents

互連基板之功率管理應用 Download PDF

Info

Publication number
TW201322840A
TW201322840A TW101137026A TW101137026A TW201322840A TW 201322840 A TW201322840 A TW 201322840A TW 101137026 A TW101137026 A TW 101137026A TW 101137026 A TW101137026 A TW 101137026A TW 201322840 A TW201322840 A TW 201322840A
Authority
TW
Taiwan
Prior art keywords
interconnect substrate
conductive
conductive structures
interconnect
substrate
Prior art date
Application number
TW101137026A
Other languages
English (en)
Inventor
Mihalis Michael
Kwang Hong Tan
Ilija Jergovic
Chi-Teh Chiang
Anthony Stratakos
Original Assignee
Volterra Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Volterra Semiconductor Corp filed Critical Volterra Semiconductor Corp
Publication of TW201322840A publication Critical patent/TW201322840A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1427—Voltage regulator [VR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16196—Cap forming a cavity, e.g. being a curved metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

本發明闡述功率管理系統中之互連基板之各種應用。

Description

互連基板之功率管理應用
本申請案依據35 U.S.C.119(e)主張於2011年10月7日提出申請之針對「Power Management Applications of Premolded Substrates」之第61/544,945號美國臨時專利申請案(代理人檔案號為VOLTP013P)之優先權，該美國臨時專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。
本發明闡述用於功率管理應用中之互連基板。
根據一特定種類之實施方案，提供一種用於將一器件連接至一總成之互連基板，該器件由一器件節距來表徵且該總成由小於約800微米之一總成節距來表徵。該互連基板包含複數個導電結構，該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者。對應於該器件之該等電路節點中之至少一者之該等導電結構與對應於該等電路節點中之至少另一者之該等導電結構在該互連基板中配置成一交替圖案。該器件節距係總成節距之約一半，且該等導電結構中之至少某些導電結構之一寬度係該等導電結構中之至少某些導電結構之間的一間距之至少約兩倍。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該器件之該等電路節點中之至少某些電路節點對應於一或多個功率器件之端子；該一或多個功率器件係一切換調節器之部分；該一或多個功率器件包含兩個功率器件，且 該等端子包含兩個功率節點端子及一切換端子；對應於該等功率節點端子之該等導電結構及該切換端子經組態以用於連接至該總成之對應導電結構。
該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，該等導電結構中之特定導電結構未到達該互連基板之該邊緣；未到達該互連基板之該邊緣之該等特定導電結構經組態以將該器件之一對應電路節點連接至該總成之一對應導電結構，該對應導電結構之至少一部分直接位於該器件下方；該互連基板之該等導電結構之一大部分直接位於該器件下方。
該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，該等導電結構中之特定導電結構至少延伸至該互連基板之該邊緣。
該等導電結構中之至少某些導電結構具有一長度及一寬度，且該長度係該寬度之至少四倍。
該等導電結構中之至少某些導電結構各自在其上具有一或多個螺柱，該一或多個螺柱經組態以用於連接至該總成之一導電結構；該等螺柱經組態以接受焊料；該等螺柱包含經電鍍焊料或預形成焊料；該等螺柱中之至少某些螺柱係圓形的，且該等導電結構中之至少某些導電結構上存在多個圓形螺柱；該等圓形螺柱中之至少某些螺柱包含焊料球；該等螺柱中之至少某些螺柱包含細長螺柱。
對應於該器件之該等電路節點中之一第一者之該等導電結構在該互連基板之一主要平面定向中沿一第一方向延 伸，且對應於該器件之該第一電路節點之該等導電結構藉由沿一第二方向延伸之一共同導電結構在該互連基板中彼此連接，在該互連基板之該主要平面定向中該第二方向不平行於該第一方向；該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且對應於該第一電路節點之該等導電結構及該共同導電結構未到達該互連基板之該邊緣；該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且該共同導電結構安置於該互連基板之該邊緣之一部分附近藉此允許將對應於該器件之該第一電路節點之該等導電結構連接至該總成之一單個導電結構；該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且該共同導電結構安置於該互連基板之該邊緣之一第一部分附近，該互連基板進一步包含在該互連基板中連接對應於該器件之該等電路節點中之一第二者之該等導電結構之一第二共同導電結構，且該第二共同導電結構安置於該互連基板之該邊緣之一第二部分附近。
對應於該等電路節點中之兩者或兩者以上之該等導電結構安置於由導電材料之一第一寬度與間距比表徵的該互連基板之一第一區域中，且對應於該等電路節點中之兩個或兩個以上電路節點之該等導電結構安置於由不同於該第一寬度與間距比的該導電材料之一第二寬度與間距比表徵的該互連基板之一第二區域中；該裝置包含一切換調節器之 至少一部分，且安置於該互連基板之該第一區域中之該等導電結構對應於該切換調節器之一功率級之功率級節點，且安置於該互連基板之該第二區域中之該等導電結構對應於該切換調節器之控制電路之控制電路節點。
該裝置包含一或多個功率器件及相關聯之控制電路，且該等導電結構中之若干第一者對應於該一或多個功率器件之端子，且該等導電結構中之若干第二者對應於該控制電路之控制電路節點；該一或多個功率器件及該相關聯之控制電路係一切換調節器之部分。
該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上，該互連基板進一步包含形成於該等導電結構之該等所曝露部分上且經組態以用於與該器件連接之複數個導電凸塊；該等導電凸塊包含球、凸塊、柱或螺柱中之任一者；該等導電凸塊包含直接形成於該等導電結構上之銅柱；該等導電凸塊包含銅柱，且該等銅柱形成於在該等導電結構上形成之一凸塊下金屬化(UBM)層上；該等導電凸塊包含銅柱，且該等銅柱減小該等導電結構之橫向導電性。
該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上且經組態以用於連接至形成於該器件上之導電凸塊；該等導電凸塊包含球、凸塊、柱或螺柱中之任一者。
一導熱結構經組態以用於傳導來自該器件之熱；該導熱結構之至少一部分延伸穿過該互連基板藉此使得能夠將來自該器件之該熱傳導至該總成。
該等導電結構中之至少某些導電結構經組態以用於將離散被動電路元件安裝於該互連基板上。
該等導電結構中之至少某些導電結構包含促進與該互連基板之一介入介質之黏合之結構特徵，且該等結構特徵包含波浪狀邊緣、鋸齒狀邊緣、Z字形邊緣、不規則邊緣、邊緣穿孔或邊緣突出部中之一或多者。
配置成該交替圖案之該等導電結構包含分別對應於第一電路節點及第二電路節點之細長結構，該等細長結構在該互連基板中沿一第一方向定向，其中對應於該第一電路節點之該等細長結構與對應於該第二電路節點之該等細長結構交替；配置成該交替圖案之該等導電結構中之每一者具有係其寬度之至少四倍之一長度，對應於該第一電路節點之該等導電結構中之每一者在其上具有位於該互連基板之一第一邊緣附近的該導電結構之一端處一或多個螺柱，且對應於該第二電路節點之該等導電結構中之每一者在其上具有與位於該第一邊緣相對的該互連基板之一第二邊緣附近的該導電結構之一端處一或多個螺柱，且對應於該第一電路節點之該等導電結構上之該等螺柱經組態以用於連接至該總成上之一第一導電平面，且對應於該第二電路節點之該等導電結構上之該等螺柱經組態以用於連接至該總成上之一第二導電平面，該第一導電平面與該第二導電平面 係毗鄰而不重疊的。
根據另一種類之實施方案，提供一種用於將一器件連接至一總成之互連基板。該互連基板包含複數個導電結構，該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者。對應於該器件之一第一電路節點之該等導電結構中之一或多者由對應於該器件之一第二電路節點之該等導電結構中之一或多者包封於該互連基板中。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該器件之該等電路節點中之至少某些電路節點對應於一或多個功率器件之端子；該一或多個功率器件係一切換調節器之部分；該一或多個功率器件包含兩個功率器件，且該等端子包含兩個功率節點端子及一切換端子；該等功率節點端子中之一者包含該器件之該第一電路節點，且該切換端子包含該器件之該第二電路節點；對應於該第一電路節點之該一或多個導電結構及對應於該第二電路節點之該等導電結構中之該一或多者經組態以用於連接至該總成之對應導電結構。
對應於該第一電路節點之該一或多個導電結構包含複數個該等導電結構，且對應於該裝置之該第二電路節點之該一或多個導電結構包含具有位於其中之複數個孔隙之一第一導電平面結構，該複數個孔隙中包封對應於該器件之該第一電路節點之該等導電結構；包封對應於該第一電路節 點之該等導電結構之該等孔隙在該第一導電平面結構中形成一棋盤圖案；對應於該第一電路節點之該等導電結構與該第一導電平面結構經組態以經由複數個導電凸塊在該互連基板之一側上分別與該器件之該第一電路節點與該第二電路節點連接，且對應於該第一電路節點之該等導電結構與該第一導電平面結構進一步經組態以在該互連基板之一對置側上分別與該總成之第一總成導電平面結構及第二總成導電平面結構連接；該第一總成導電平面結構及該第二總成導電平面結構係毗鄰而不重疊的；該第一導電平面結構經組態以與該第二總成導電平面結構在該第一導電平面結構之一邊緣接觸，且對應於該第一電路節點之該等導電結構經組態以沿實質上垂直於該互連基板之一主要平面定向之一方向在若干位置處連接至該第一總成導電平面結構；對應於一第三電路節點之複數個該等導電結構中之每一者亦包封於該互連基板中在該第一導電平面結構之該等孔隙中之一對應者內。
該裝置包含一切換調節器之至少一部分，且安置於該互連基板之一第一區域中之該等導電結構中之若干第一者對應於該切換調節器之一功率級之功率級節點，且安置於該互連基板之一第二區域中之該等導電結構中之若干第二者對應於該切換調節器之控制電路之控制電路節點。
該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上，該互連基板進一步包含形成於該等導電 結構之該等所曝露部分上且經組態以用於與該器件連接之複數個導電凸塊；該等導電凸塊包含球、凸塊、柱或螺柱中之任一者；該等導電凸塊包含直接形成於該等導電結構上之銅柱；該等導電凸塊包含銅柱，且該等銅柱形成於在該等導電結構上形成之一凸塊下金屬化(UBM)層上。
該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上且經組態以用於連接至形成於該器件上之導電凸塊；該等導電凸塊包含球、凸塊、柱或螺柱中之任一者。
一導熱結構經組態以用於傳導來自該器件之熱；該導熱結構之至少一部分延伸穿過該互連基板藉此使得能夠將來自該器件之該熱傳導至該總成。
該等導電結構中之至少某些導電結構經組態以用於將離散被動電路元件安裝於該互連基板上。
該等導電結構中之至少某些導電結構包含促進與該互連基板之一介入介質之黏合之結構特徵，且該等結構特徵包含波浪狀邊緣、鋸齒狀邊緣、Z字形邊緣、不規則邊緣、邊緣穿孔或邊緣突出部中之一或多者。
根據另一種類之實施方案，提供一種包含一器件之封裝，該器件包含一或多個功率器件及用於將該器件連接至一總成之一互連基板。該互連基板包含複數個導電結構，該等導電結構中之若干第一者對應於該一或多個功率器件之端子。該器件經由導電凸塊安裝於該互連基板之該等導 電結構之所曝露部分上。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該一或多個功率器件係一切換調節器之部分。
該一或多個功率器件包含兩個功率器件，且該等端子包含兩個功率節點端子及一切換端子。
對應於該等端子中之一者的該等第一導電結構中之至少一者藉由對應於該等端子中之另一者的該等第一導電結構中之至少另一者包封於該互連基板中。
該裝置包含與該一或多個功率器件相關聯之控制電路，且該等導電結構中之若干第二者對應於該控制電路之控制電路節點。
該互連基板之該等導電結構中之至少某些導電結構具有連接至其之離散被動電路元件；該等離散被動電路元件包含連接至該一或多個功率器件之該等端子中之至少某些端子之複數個電容器；該一或多個功率器件之一第一端子具有連接至其之該複數個電容器中之兩者或兩者以上，該兩個或兩個以上電容器沿該器件之一個以上邊緣安裝於該互連基板上；對應於該一或多個功率器件之一第一端子之該等第一導電結構經組態以用於沿該互連基板之一第一邊緣連接至該總成，且對應於該第一端子之該等電容器中之一或多者沿不同於該第一邊緣的該互連基板之一第二邊緣而安裝；該等離散被動元件中之一第一者連接至其之該等導電結構經組態以用於連接至該總成；該第一離散被動電路 元件僅可接達用於使用該器件之一測試介面來測試；該等離散被動電路元件中之一或多者安裝於該互連基板上在該等導電凸塊中之若干毗鄰導電凸塊之間；該等離散被動電路元件包含一電容器、一電阻器或一電感器中之一或多者。
佔據將該互連基板之該等導電結構連接至該器件之該等導電凸塊之間的空間之一底填充材料；該底填充材料包含一經施配底填充或一經模製底填充；該底填充材料係至少部分地囊封該器件之一囊封材料之部分。
該器件安裝於該互連基板之該等導電結構上在該器件之一第一側上，且與該第一側對置的該器件之一第二側經曝露以用於熱移除；該互連基板進一步包含一導熱結構，該封裝進一步包含一散熱器結構，該散熱器結構安裝於該器件之所曝露第二側上且熱連接至該互連基板之該導熱結構以促進自該器件至該導熱結構之熱傳導；該導熱結構之至少一部分延伸穿過該互連基板且經組態以用於連接至該總成，藉此使得能夠將來自該器件之熱傳導至該總成；一載體框架之一或多個部分沿毗鄰該器件的該互連基板之一或多個邊緣而安置，該散熱器結構經由該載體框架之該等部分熱連接至該互連基板之該導熱結構；該載體框架係矩形且圍繞該互連基板上之該器件係連續的；該載體框架包含圍繞該互連基板上之該器件之一或多個不連續片段；該散熱器結構包含複數個斷開連接或部分地連接之部分及或一或多個孔隙。
該封裝進一步包含一第二器件及用於經由該互連基板將該第二器件連接至該總成之一第二互連基板，該第二互連基板包含第二複數個導電結構，且該第二器件經由第二導電凸塊安裝於該第二複數個導電結構之所曝露部分上，且該第二互連基板安裝於該器件上，其中該第二複數個導電結構中之至少某些導電結構連經由毗鄰該器件之一邊緣之第三導電凸塊接至該互連基板之該複數個導電結構中之一或多者；該第二器件亦包含一或多個功率器件。
對應於該一或多個功率器件之該等端子中之至少一者之該等第一導電結構與對應於該一或多個功率器件之該等端子中之至少另一者之該等第一導電結構在該互連基板中配置成一交替圖案。
該器件由一器件節距來表徵且該總成由小於約800微米之一總成節距來表徵，且該器件節距係該總成節距之約一半，且該等導電結構中之至少某些導電結構之一寬度係該等導電結構中之至少某些導電結構之間的一間距之至少約2倍。
該互連基板具有連接至該器件之一第一表面及連接至該總成之一第二表面以及一邊緣，該等導電結構中之至少某些導電結構未到達該互連基板之該邊緣。
該互連基板具有連接至該器件之一第一表面及連接至該總成之一第二表面以及一邊緣，該等導電結構中之至少某些導電結構至少延伸至該互連基板之該邊緣。
該等導電結構中之至少某些導電結構具有一長度及一寬 度，且該長度係該寬度之至少四倍。
該等導電結構中之至少某些導電結構各自在其上具有一或多個螺柱，該一或多個螺柱經組態以用於連接至該總成之一導電結構；該等螺柱經組態以接受焊料；該等螺柱包含經電鍍焊料或預形成焊料；該等螺柱中之至少某些螺柱係圓形的，且該等導電結構中之至少某些導電結構上存在多個圓形螺柱；該等圓形螺柱中之至少某些螺柱包含焊料球；該等螺柱中之至少某些螺柱包含細長螺柱。
對應於該等端子中之一第一者之該等第一導電結構在該互連基板之一主要平面定向中沿一第一方向延伸，且對應於該第一端子之該等第一導電結構藉由沿一第二方向延伸之一共同導電結構在該互連基板中彼此連接，在該互連基板之該主要平面定向中該第二方向不平行於該第一方向；該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且對應於該第一端子之該等第一導電結構與該共同導電結構不接觸該互連基板之該邊緣；該互連基板具有連接至該器件之一第一表面及連接至該總成之一第二表面以及一邊緣，且該共同導電結構安置於該互連基板之該邊緣之一部分附近且經組態以用於將對應於該第一端子之該等第一導電結構連接至該總成之一單個導電結構；該互連基板具有連接至該器件之一第一表面及連接至該總成之一第二表面以及一邊緣，且該共同導電結構安置於該互連基板之該邊緣之一第一部分附近，該互連基板進一步包含在該互連基板中連接對應於該 等端子中之一第二者之該等第一導電結構之一第二共同導電結構，且該第二共同導電結構安置於該互連基板之該邊緣之一第二部分附近。
對應於該一或多個功率器件之該等端子之該等第一導電結構安置於由導電材料之一第一寬度與間距比表徵的該互連基板之一第一區域中，且對應於與該一或多個功率器件相關聯之控制電路之控制電路節點之該等導電結構中之若干第二者安置於由不同於該第一寬度與間距比的該導電材料之一第二寬度與間距比表徵的該互連基板之一第二區域中。
一導熱結構經組態以用於傳導來自該器件之熱；該導熱結構之至少一部分延伸穿過該互連基板且經組態以用於連接至該總成，藉此使得能夠將來自該器件之熱傳導至該總成。
該等導電結構中之至少某些導電結構包含促進與該互連基板之一介入介質之黏合之結構特徵，且該等結構特徵包含波浪狀邊緣、鋸齒狀邊緣、Z字形邊緣、不規則邊緣、邊緣穿孔或邊緣突出部中之一或多者。
對應於該一或多個功率器件之一第一端子之該等第一導電結構中之至少一者藉由對應於該一或多個功率器件之一第二端子之該等第一導電結構中之一或多者包封於該互連基板中；對應於該第二端子之該等第一導電結構中之該一或多者包含具有位於其中之複數個孔隙之一第一導電平面結構，在該複數個孔隙中包封對應於該第一端子之該等第 一導電結構；包封對應於該第一端子之該等第一導電結構之該等孔隙在該第一導電平面結構中形成一棋盤圖案；對應於該第一端子之該等第一導電結構及該第一導電平面結構經組態以在該互連基板之一側上經由一子組之該等導電凸塊分別與該第一端子與該第二端子連接，且對應於該第一端子之該等第一導電結構與該第一導電平面結構進一步經組態以在該互連基板之一對置側上分別與第一總成導電平面結構與第二總成導電平面結構連接；該等第一導電結構中之至少某些導電結構包含使得能夠將電流或熱沿垂直於該互連基板之一主要平面定向之一方向傳導至直接在該器件下方之總成結構之通孔；該第一總成導電平面結構及該第二總成導電平面結構係毗鄰而不重疊的；該第一導電平面結構經組態以在該第一導電平面結構之一邊緣處與該第二總成導電平面結構連接，且對應於該第一端子之該等第一導電結構經組態以沿實質上垂直於該互連基板之一主要平面定向之一方向在若干位置處連接至該第一總成導電平面結構；對應於該一或多個功率器件之一第三端子之複數個該等第一導電結構中之每一者亦包封於該互連基板中在該第一導電平面結構之該等孔隙中之一對應者內。
該等導電凸塊包含球、凸塊、柱或螺柱中之任一者；該等導電凸塊包含銅柱；該等銅柱直接形成於該互連基板之該等導電結構上；該等銅柱形成於在該互連基板之該等導電結構上形成之一凸塊下金屬化(UBM)層上；該裝置包含一銅重新分佈層(RDL)且該等銅柱直接形成於該RDL上； 該裝置包含一銅重新分佈層(RDL)，且該等銅柱形成於在該RDL上形成之一凸塊下金屬化(UBM)層上。
根據另一種類之實施方案，提供一種用於將一器件連接至包含複數個導電結構之一總成之互連基板。該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者。該互連基板之該等導電結構中之至少某些導電結構具有安裝於連接至其之該互連基板上之離散被動電路元件。該等離散被動元件中之一第一者之一端子連接至其之該等導電結構中之至少一者經組態僅用於連接至該器件且不連接至該總成。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該等離散被動電路元件中之兩者或兩者以上經組態以用於連接至該器件之一第一電路節點，該兩個或兩個以上離散被動電路元件沿該互連基板之一個以上邊緣而安裝。
對應於該器件之一第一電路節點之該等導電結構經組態以用於沿該互連基板之一第一邊緣連接至該總成，且對應於該第一電路節點之該等離散被動電路元件中之一或多者安裝於不同於該第一邊緣的該互連基板之一第二邊緣上。
該等離散被動電路元件中之一或多者在經組態以用於連接至該器件之該互連基板之該等導電結構之所曝露部分之間的位置處安裝於該互連基板上。
該等離散被動電路元件包含一電容器、一電阻器或一電感器中之一或多者。
該裝置包含一或多個功率器件，該等導電結構中之至少某些導電結構對應於該一或多個功率器件之端子，且該等離散被動電路元件包含經組態以用於連接至該一或多個功率器件之該等端子中之至少某些端子之複數個電容器。
該第一離散被動電路元件及該等對應導電結構經組態以使得當該器件、該互連基板及該總成經連接時該第一離散被動電路元件僅可接達用於使用該器件之一測試介面來測試。
根據另一種類之實施方案，提供一種用於將一器件連接至包含複數個導電結構之一總成之互連基板。該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者。該互連基板之該等導電結構中之至少某些導電結構具有安裝於連接至其之該互連基板上之離散被動電路元件。該等離散被動電路元件中之兩者或兩者以上經組態以用於連接至該器件之一第一電路節點。該兩個或兩個以上離散被動電路元件沿該互連基板之邊緣中之一者以上而安裝。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：對應於該器件之該第一電路節點之該等導電結構經組態以用於沿該互連基板之一第一邊緣連接至該總成，該第一邊緣不同於該兩個或兩個以上離散被動電路元件沿其而安裝之該等邊緣中之至少一者。
該等離散被動電路元件中之一或多者在經組態以用於連 接至該器件之該互連基板之該等導電結構之所曝露部分之間的位置處安裝於該互連基板上。
該等離散被動電路元件包含一電容器、一電阻器或一電感器中之一或多者。
該裝置包含一或多個功率器件，該等導電結構中之至少某些導電結構對應於該一或多個功率器件之端子，且該等離散被動電路元件包含經組態以用於連接至該一或多個功率器件之該等端子中之至少某些端子之複數個電容器。
根據另一種類之實施方案，提供一種用於將一器件連接至包含複數個導電結構之一總成之互連基板。該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者。該互連基板之該等導電結構中之至少某些導電結構具有安裝於連接至其之該互連基板上之離散被動電路元件。對應於該器件之一第一電路節點之該等導電結構經組態以用於沿該互連基板之一第一邊緣連接至該總成，且對應於該第一電路節點之該等離散被動電路元件中之一或多者安裝於不同於該第一邊緣的該互連基板之一第二邊緣上。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該等離散被動電路元件中之兩者或兩者以上經組態以用於連接至該器件之該第一電路節點，該兩個或兩個以上離散被動電路元件沿該互連基板之一個以上邊緣而安裝。
該等離散被動電路元件中之一或多者在經組態以用於連 接至該器件之該互連基板之該等導電結構之所曝露部分之間的位置處安裝於該互連基板上。
該等離散被動電路元件包含一電容器、一電阻器或一電感器中之一或多者。
該裝置包含一或多個功率器件，該等導電結構中之至少某些導電結構對應於該一或多個功率器件之端子，且該等離散被動電路元件包含經組態以用於連接至該一或多個功率器件之該等端子中之至少某些端子之複數個電容器。
根據另一種類之實施方案，提供一種包含複數個導電結構之凸起器件，該複數個導電結構包含一重新分佈層(RDL)及直接形成於該RDL上之複數個銅柱，該等銅柱與該RDL之間不具有鈍化材料。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：一鈍化層覆蓋該等銅柱延伸穿過其之該RDL。
該等銅柱減小該等導電結構之橫向導電性。
該裝置包含一積體電路。
該凸起器件包含具有複數個端子之一或多個功率器件；該一或多個功率器件係一切換調節器之部分；該一或多個功率器件包含兩個功率器件，且該等端子包含兩個功率節點端子及一切換端子；該等銅柱經組態以將該一或多個功率器件之該等端子連接至一基板之導電結構。
根據另一種類之實施方案，提供一種用於製作一器件方法。在一下伏基板之一可接達金屬化上方濺鍍一晶種層。 在該晶種層上方放置具有一第一圖案之一第一光阻劑層。根據該第一圖案使用該晶種層來電鍍一第一導電金屬層。在該第一導電金屬層上方放置具有一第二圖案之一第二光阻劑。根據該第二圖案使用該晶種層來電鍍一第二導電金屬層。在該第二導電金屬層與該第一導電金屬層之間不具有鈍化材料之情形下形成該第二導電金屬層。蝕刻該晶種層。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該第一導電金屬層及該第二導電金屬層包含銅。
該第一導電金屬層包含一銅重新分佈層(RDL)且該第二導電金屬層包含複數個銅柱；在該RDL及該等銅柱上方沈積一鈍化材料；在該等銅柱上電鍍焊料。
使用該晶種層來電鍍一或多個額外導電金屬層。
在施加該第二光阻劑層之前剝離該第一光阻劑層。
實質上同時剝離該第一光阻劑層與該第二光阻劑層。
根據另一種類之實施方案，提供一種用於將一器件連接至一總成之互連基板。該裝置包含一切換調節器之一功率級。該功率級具有第一功率節點端子及第二功率節點端子以及一切換端子。該互連基板包含複數個導電結構，該等導電結構中之若干第一者經組態以用於連接至該第一功率節點端子，該等導電結構中之若干第二者經組態以用於連接至該切換端子，且該等導電結構中之若干第三者經組態以用於連接至該第二功率節點端子。該等第一導電結構、 該等第二導電結構及該等第三導電結構配置於該互連基板中以使得當傳導在該等第一導電結構與該等第三導電結構之間換向時由該切換調節器之該功率級之操作產生的該等第二導電結構中之電流保持實質上恆定。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該等第二導電結構中之每一者毗鄰該等第一導電結構中之一者及該等第三導電結構中之一者；該等第二導電結構中之每一者使該等第一導電結構中之一者在該第二導電結構之一第一側上且該等第三導電結構中之一者在與該第一側相對的該第二導電結構之一對置側上。
根據另一種類之實施方案，提供一種包含一器件之封裝，該器件包含一切換電壓調節器之一功率級，該功率級具有第一功率節點端子及第二功率節點端子以及一切換端子。該封裝亦包含用於將該器件連接至一總成之一互連基板。該互連基板包含複數個導電結構，該等導電結構中之若干第一者連接至該第一功率節點端子，該等導電結構中之若干第二者連接至該切換端子，且該等導電結構中之若干第三者連接至該第二功率節點端子。該等第一導電結構、該等第二導電結構及該等第三導電結構配置於該互連基板中以使得當傳導在該等第一導電結構與該等第三導電結構之間換向時由該切換調節器之該功率級之操作產生的該等第二導電結構中之電流保持實質上恆定。
此等實施方案中之各種實施方案可包含以下特徵中之任 一者，包含其任何適合組合、排列或子組：該等第二導電結構中之每一者毗鄰該等第一導電結構中之一者及該等第三導電結構中之一者；該等第二導電結構中之每一者使該等第一導電結構中之一者在該第二導電結構之一第一側上且該等第三導電結構中之一者在與該第一側相對的該第二導電結構之一對置側上。
根據另一種類之實施方案，提供一種包含一切換電壓調節器之一功率級之凸起器件，該功率級具有第一功率節點端子及第二功率節點端子以及一切換端子。該凸起器件亦包含配置於其一表面上之複數個導電凸塊且經組態以用於促使外部連接至該切換電壓調節器之該功率級之該第一功率節點端子及該第二功率節點端子以及該切換端子。該等導電凸塊中之若干第一者電連接至該第一功率節點端子，該等導電凸塊中之若干第二者電連接至該切換端子，且該等導電凸塊中之若干第三者電連接至該第二功率節點端子。該切換調節器之該功率級經組態且該等第一導電凸塊、該等第二導電凸塊及該等第三導電凸塊經配置以使得當傳導在該等第一導電凸塊與該等第三導電凸塊之間換向時由該切換調節器之該功率級之操作產生的該等第二導電凸塊中之電流保持實質上恆定。
此等實施方案中之各種實施方案可包含以下特徵中之任一者，包含其任何適合組合、排列或子組：該等第二導電凸塊之複數個子組中之每一者毗鄰該等第一導電凸塊之複數個子組中之一者及該等第三導電凸塊之 複數個子組中之一者；該等第一導電凸塊、該等第二導電凸塊及該等第三導電凸塊之該複數個子組中之每一者配置成一列，該等第二導電凸塊之每一列使該等第一導電凸塊之一列在第二導電凸塊之該列之一第一側上且該等第三導電凸塊之一列在與該第一側相對的該等第二導電凸塊之該列之一對置側上。
該等導電凸塊包含球、凸塊、柱或螺柱中之任一者。
該等導電凸塊包含銅柱；該凸起器件包含一銅重新分佈層(RDL)且該等銅柱直接形成於該RDL上；該凸起器件包含一銅重新分佈層(RDL)，且該等銅柱形成於在該RDL上形成之一凸塊下金屬化(UBM)層上。
該等導電凸塊係細長的。
可藉由參考說明書之其餘部分及圖式來實現對本發明之本質及優點之一進一步理解。
現在將詳細參考包含由實施本發明之發明者預計之最佳模式的本發明之特定實施例。隨附圖式中圖解說明此等特定實施例之實例。雖然與此等特定實施例一起闡述本發明，但將理解，其並非意欲將本發明限制於所闡述之實施例。相反，其意欲涵蓋如可包含於如由隨附申請專利範圍定義之本發明之精神及範疇內之替代方案、修改及等效物。在以下說明中，陳述特定細節以便提供對本發明之一透徹理解。可在無此等特定細節中之某些或所有細節之情形下實踐本發明。另外，可尚未詳細地闡述眾所周知之特 徵以避免使本發明不必要地模糊。
稱為覆晶QFN(四方扁平無引線)之半導體封裝技術涉及在包括自一固體銅薄片蝕刻之導電跡線之一引線框架上安裝一覆晶IC。此總成然後圍封於一模製化合物中以保護該器件免受環境影響。用以形成其上安裝有覆晶IC之導電跡線之此「減去性」方法之一限制係當前蝕刻技術限制導電跡線之密度。亦即，銅蝕刻技術之決案對毗鄰導電跡線之間的距離設置一下限(例如，約125微米)。此又限制待安裝於導電跡線上之器件(例如，一覆晶IC)上之連接件(亦即，球、凸塊或柱)之節距。可藉由減小所蝕刻之銅之厚度來達成某一改良，但此最終導致不可接受之可靠性問題，諸如(舉例而言)，導電跡線及引線框架之脆性。因此，在覆晶及其他封裝具有愈來愈多數目個I/O之情形下，在一引線框架上製造導電跡線之習用方法給使用此等技術帶來顯著障礙。
雖然採用有機基板之技術可達成較高密度，但對諸多應用而言過於昂貴，且對較極端應用而言或就一產品壽命而言通常係低劣的。
在某些應用中，其中使用「添加性」技術來製造導電跡線(例如，在一基板上電鍍導電跡線)之預模製基板可達成適合高密度(例如，導電跡線之間約40微米至50微米且在某些情形中可能低至30微米)。
本文中所闡述之各種預模製基板可由自電鍍技術相對於蝕刻技術之優點導出之一第一組益處及/或預模製結構相 對於習用引線框架之優點導出之一第二組益處來表徵。
關於電鍍對蝕刻，就可達成之跡線縱橫比而言，經蝕刻跡線相對於電鍍跡線具有限制。舉例而言，當自銅薄片之兩側蝕刻時，習用製程可通常僅達成稍微大於跡線之厚度之一半的跡線之間的一間距。相比而言，經常看到電鍍產生高得多之縱橫比結構。存在使用蝕刻來達成類似間距之方式，而其需要蝕刻僅一薄層。因此，電鍍相對於蝕刻之一個優點係較高縱橫比結構(例如，110 μm跡線厚度，其中跡線之間40 μm間距)。
另外，預模製基板(其可藉助蝕刻技術及電鍍技術兩者來形成)相對於習用引線框架具有的一優點在於對預模製基板而言不需要用於導電跡線之一實際框架。亦即，在習用引線框架之情形下，中間蝕刻跡線必須連接至將結構保持在一起直至模製為止之一框架。此強加所有跡線到達器件之邊緣(亦即，該器件之內部無浮動結構可形成)之要求。此使得難以形成面積陣列及多列封裝，此乃因無法具有未到達器件之邊緣之內部浮動導電結構。由於預模製基板不需要此一框架，因此其不以此方式受限制。
如參照下文對特定實施例之說明將變得顯而易見，可藉助如本文中所闡述實施之預模製基板來達成多種優點。舉例而言，使用蝕刻製作之具有200 μm厚度之一習用引線框架通常產生具有一400 μm節距的250 μm寬之導電跡線。相比之下且根據本文中所闡述之一或多個實施例，對於相同導電跡線寬度，在使用電鍍之預模製基板中可達成一290 μm節距；110 μm之一減小。若試圖減小低於250 μm之一習用引線框架之導電跡線之寬度，則蝕刻製程將導致機械不穩定之結構。舉例而言，若此等結構以半蝕刻方式形成，則其將形成相對於其可延伸多遠受限制之懸臂橋。雖然經蝕刻引線框架中之跡線寬度理論上了減小至125 μm(藉此達成具有150 μm間距之一275 μm節距)，但此等結構在長度上嚴格受限。相比之下，一預模製基板之導電跡線由模製化合物支撐，其中其被懸置且可行進(例如)大於其寬度4X之極大距離。
另外，雖然某些器件(例如，覆晶器件)上之節距可極低(例如，150 μm)，但印刷電路板(PCB)上之節距通常係500 μm(其中受限制應用具有一400 μm節距)。一般而言，在無成本中之一抑制性增加(對於大多數應用而言)之情形下，用於PCB及通孔技術之目前最佳技術不准許低於500 μm之節距之減小。此係由於以下事實：通常使用蝕刻技術來製造PCB(藉助針對通孔及外層之某一添加性電鍍)。因此，由於對PCB之此限制，外部器件節距需要保持處於500 μm而內部器件節距需要扇形展開成任何經減小之節距。令人遺憾地，習用引線框架技術對不可有效地匹配極低節距與高I/O計數之內部器件節距提出實際限制，某些器件技術(例如，覆晶器件)由高I/O計數來表徵。下文闡述圖解說明預模製基板相對於此等設計問題之優點中之一或多者之各種實施例。
根據某些實施例，可如下製造預模製基板。用一銅薄膜 預電鍍一載體基板或載體框架(例如，可使用鋼作為一低成本選項)以促進電鍍。在銅上電鍍導電跡線(包含在第一導電跡線(即，螺柱)層之頂部上之一第二導電跡線層)，且然後在該等導電跡線及該載體上方沈積一模製材料。然後磨掉模製材料以曝露該等螺柱以用於將預模製基板連接至另一總成(例如，一印刷電路板(PCB))。與用於引線框架形成之習用減去性技術相比，藉助其形成此等導電跡線之添加性製程允許墊可放置之處之靈活性。然後，自總成之另一側蝕除載體以曝露嵌入於模製材料中之導電跡線。視情況在其中可然後形成墊之導電跡線上方沈積一絕緣層，其中待安裝於預模製基板上之凸起器件將與預模製基板導電跡線接觸。對於關於本發明之各種實施例可採用之預模製基板技術之更多資訊，請參考針對於2008年6月19日公開之「Semiconductor Package and Manufacturing Method Thereof」之第2008/0145967號美國專利申請案，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。
本文中所闡述之各種本發明之實施例係關於用於與凸起半導體封裝(例如，覆晶)(且更具體而言，功率管理應用中所使用之凸起半導體封裝)介接之互連基板(例如，預模製基板)之使用。如本文中所使用，「凸起器件」指代具有跨越用於進行至其他器件、板、總成或基板之電連接的器件之一表面配置之一導電元件(例如，球、凸塊、柱等)陣列之任何半導體器件。
圖1展示經組態以用於與一上覆凸起器件連接而且與一下伏PCB上之控制墊及導電平面連接的一預模製基板中之導電跡線。根據一特定種類之實施例，導電平面表示(舉例而言)一切換電壓調節器之三個端子，圖1中展示該三個端子中之兩者，亦即，VX平面及接地/VSS平面。如所展示，連接至下伏導電平面之導電跡線類似交替或「相互交叉」之指狀物。曝露導電跡線之圓形螺柱與下伏PCB上之對應導電平面對準。可使用任何適合技術(例如，球、凸塊、柱、膏等)來製作該等螺柱與導電平面之間的連接件件。
圖2展示另一預模製基板中之導電跡線，亦經組態以用於與一上覆凸起器件連接而且與一下伏PCB上之控制墊及導電平面連接。同樣，在此實例中，導電平面表示一切換電壓調節器之三個端子。然而，與圖1相比，螺柱沿導電跡線之長度而形成且形成用於與下伏PCB連接之引線指。另外，與圖1中所展示之毗鄰導電跡線之間的隔離相比，對應於PCB上之同一導電平面的圖2之導電跡線電彼此連接(經由一水平匯流排)。圖3中更清晰地表示在背面研磨模製化合物之後具有等效曝露之螺柱之經電連接導電跡線。
圖3之上部部分展示預模製基板中懸置之互連VX導電跡線、互連VSS導電跡線及互連VDD導電跡線，每一組導電跡線對應於該組導電跡線將連接至其的PCB上之一導電平面。對於某些實施方案而言使每一組導電跡線之垂直指狀物互連之水平匯流排可係有利的，從而允許至互連導電跡 線之一單個端子連接。此一方法有利之處亦可在於倘若個別引線或連接失敗亦可較佳地確保電連接性。
圖3之下部部分展示形成於將進行直接連接至下伏PCB上之導電平面及墊之導電跡線上之螺柱(呈引線指之形式)之圖案。應注意，使用球、凸塊或柱而非引可導致板級可靠性之改良。下文論述某些實施例。亦應理解，所有此等結構(球、凸塊、柱、螺柱等)亦可形成於經隔離導電跡線(諸如(舉例而言)圖1中所展示之彼等導電跡線)上。圖4展示一IC墊及可形成於圖3之上部部分中所展示之結構之導電跡線上之球、凸塊或柱之接針(pin out)佈局圖案(其中在此實例中VSS標示為GND)。球、凸塊或柱之此圖案可形成於預模製基板導電跡線、IC器件或兩者上。
與此等實施例中之某些實施例相關聯之一個優點係改良I/O密度同時維持類似於採用更多種習用方法(例如，QFN、BGA、TSOP、J引線、鷗翼(Gull-Wing)等)之當前設計之一佔用面積之能力。功率管理積體電路之上下文中之經改良I/O密度允許設計者在對此等器件之控制及監視中更具靈活性及特定而言在與切換電路相同之器件中包含I/O至外部世界之能力(與單獨控制IC相反)。另外，可減小高電流導電跡線(例如，VX、VSS及VDD跡線)之間的節距，而對應地減小電阻以及切換損失。亦可實現與電遷移相關之改良，此乃因經增加之密度意謂著每單位面積存在更多焊料。因經增加之密度所致的電力之更均勻分佈亦可導致較佳熱效能。
且應理解，所闡述之導電跡線圖案及連接性結構僅係圖解說明功率管理器件及系統之上下文中之預模製基板之諸多潛在組態及應用之實例。圖5(a)中展示其中跡線上之球、凸塊或柱自身「相互交叉」之一組態之另一實例。如所展示，島形成於用於連接至VDD及VSS/GND之球、凸塊或柱之VX導電平面中。所圖解說明之圖案意欲減小內部金屬連接電阻以便改良切換半導體元件之全接通狀態電阻(Rdson)。此方法亦意欲藉助使用固體導電平面來改良PCB連接件以減小PCB電阻且改良導熱率。其亦可由於較大焊料墊連接件而促進用於PCB安裝之組裝。對於關於用於使導電跡線及/或球、凸塊或柱之組態相互交叉以供與本發明之實施例一起使用之技術之更多資訊，請參考2008年12月24日提出申請之針對「Lead Assembly for a Flip-Chip Power Switch」之第12/344,134號美國專利申請案，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。
圖5(b)至圖5(e)展示用於相互交叉之節點之一組態(諸如圖5(a)中所展示之彼組態)之銅柱凸塊及晶片上金屬連接件之額外細節。圖5(c)中展示圖5(b)之細節區A之一分解透視圖且該分解透視圖圖解說明用於區A中之節點之晶片上金屬連接件。圖5(d)中展示圖5(b)之細節區B之一分解透視圖且該分解透視圖圖解說明用於區B中之節點之晶片上金屬連接件。圖5(e)中展示圖5(b)之細節區C之一分解透視圖且該分解透視圖圖解說明用於區C中之節點之晶片上金屬連 接件。如圖5(c)至圖5(e)中之每一者中所展示，金屬層3(M3)與具有相同電極性且對應於同一調節器端子之凸塊下金屬(UBM)之間的所有層透過相互拼接而連接。
本文中所論述之實施例中之某些實施例中之導電跡線之相互交叉之組態(例如，圖1至圖3)導致處於內部跡線之節距2X之一外部器件節距，亦即，此乃因僅每隔一個跡線連接至下伏PCB上之同一導電元件。由此斷定，可將內部器件節距減小至250 μm而不將PCB之外部器件節距推動至低於500 μm之其典型限制。在根據本發明之實施例構造且在導電跡線之間具有一40 μm間距之一預模製基板中，此導致210 μm之一跡線寬度。相比而言，習用引線框架技術將需要100 μm之一跡線寬度；遠低於針對一穩健結構之所建議限制。除了係脆性之外，此一跡線寬度亦將可能不適於電流，且導致一不可接受之小器件墊寬度(例如，100 μm)；遠低於習用引線框架技術當前可接受可銲寬度。
根據某些實施例，一預模製基板不僅促進內部器件之I/O區段之扇形展開而且使得能夠形成I/O區段中之一面積陣列，因此與周邊器件(諸如，習用引線框架)相比允許I/O密度之一增加。應注意，亦可使用至印刷電路板之預模製基板連接性之LGA或BGA變型來實現此等實施例。
根據某些實施例，該器件之一側上之共同跡線之共同定位允許PCB節距規則放鬆，此乃因同一側(例如，VX或VSS)上之所有跡線可與一固體導電平面接觸，因此移除對精細蝕刻之需要，且出於此目的，PCB上之跡線允許在將 來節距進一步減小至低於500 μm。此外，此等設計無需在PCB墊中放置通孔；一方法在回流期間造成如此等通孔陷獲焊料空隙且降低板級可靠性之問題。亦即，本發明預計以下實施例：允許使VX、VSS及VDD平面中之通孔位於焊料遮罩中之焊料開口之間，該等焊料開口經組態以連接至導電跡線、LGA之可銲區之跡線及/或預模製基板之BGA變體之焊料球。該等通孔允許直接在該器件下方之PCB中之多層之連接。相對於習用引線框架設計，此一方法可顯著增加通孔密度，藉此實現較低電損失以及自器件封裝至板之較佳導熱性。
可採用如本文中所闡述之以適合方式組態之預模製基板之功率管理器件及系統之種類之實例包含(舉例而言)於2001年8月21日發佈之針對「Flip-Chip Switching Regulator」之第6,278,264號美國專利之申請專利範圍中所闡述及由該申請專利範圍涵蓋之彼等功率管理器件及系統，該美國專利之整個揭示內容出於所有目的以引用方式併入本文中。熟習此項技術者亦將明瞭可受益於本文中所闡述之特定實施例的各種各樣之其他功率管理器件及系統及其他凸起器件。
根據一特定種類之實施例，可曝露安裝於預模製基板之導電跡線上之凸起器件之背部。亦即，一旦在預模製基板上安裝凸起器件，即可在除凸起器件之背部之外的所有側上模製組合結構，或可在所有側上外模製組合結構，其中隨後移除(例如，藉由蝕刻或研磨)外模製件之一部分以曝 露凸起器件之背部。
圖6(a)展示類似於圖1中所展示之預模製基板之一預模製基板以及具有一經安裝凸起器件之預模製基板之兩個替代剖面。在所展示之實例中，展示經曝露之凸起器件(a)之背部。雖然該凸起器件展示為經由銅柱(b)及焊料凸塊(c)連接至預模製基板之導電跡線(d)，但可採用多種其他類型之連接件。沿導電跡線之螺柱(e)亦具有用於進行至PCB(未展示)之連接之焊料(在此實例中呈焊料球(f)之形式)。
且如圖6(a)(下部器件剖面)中所展示，本發明之實施例可採用習用底填充來填充至凸起器件之連接件之間的間隙。亦即，一旦附接凸起器件且在施加一外模製件之前，即施配一底填充材料，該底填充材料藉由一毛細管作用在器件下方流動且填充該器件下方之裂縫。該底填充材料可係任何適合之習用底填充材料且非常適合用於具有帶有一極細節距之高I/O密度之實施方案。
另一選擇係，本發明預計其中可採用一經模製底填充之實施例(圖6(a)中之上部器件剖面)。經模製底填充藉助使用一模製型製程來引入之一模製材料替換經施配底填充。模製化合物中所包含之粗糙材料使製程比施配習用底填充(特別係對於極細節距應用而言)更具挑戰性，但該等材料明顯便宜得多。經模製底填充亦可造成經改良可靠性，此乃因其可提供比習用底填充材料穩健之機械及/或環境保護。圖6(b)展示類似於圖6(a)之上部器件剖面之另一預模製基板，但其中跡線上之球、凸塊或柱以類似於圖5(a)中 所展示之彼方式之一方式相互交叉。
根據圖7及圖8中所圖解說明之一種類之實施例，散熱器結構連接至所安裝凸起器件之所曝露背部以提供用於移除來自凸起器件之熱之導熱路徑。圖7圖解說明在二維中提供熱傳導(亦即，透過散熱器向上，且橫向至延伸超過下伏半導體器件的散熱器之部分)之三個散熱器組態。整合散熱器延伸部可用作熱及/或電連接件。如圖7之中間圖解中所展示，可使散熱器向下變為與PCB接觸以透過對流促進經由PCB之額外熱傳遞。如圖7之底部圖解中所展示，整合散熱器延伸部亦可經由螺柱及焊接接頭附接至預模製基板導電跡線及/或附接至PCB。在每單位晶粒面積之功率及I/O密度繼續增加時，此等實施例可係特別重要的。
根據圖8中所圖解說明之一特定種類之實施例，載體基板(亦即，載體框架)之至少一部分圍繞經蝕除以曝露預模製基板中所懸置之導電跡線之窗之邊緣而維持。該框架可係矩形且圍繞該器件係連續的，或圍繞邊緣(例如，在總成之四個拐角處、沿一或多個邊緣等)呈一或多個不連續片段。此載體框架提供至PCB之額外熱路徑以用於改良熱效能。上部兩個圖式展示其中散熱器以類似於圖7中所展示之實施例之一方式延伸超過載體框架之實施例。應注意，此等散熱器延伸部亦可連接至預模製基板導電跡線及/或連接至PCB，如圖7之底部圖式中所展示。該底部圖式展示其中散熱器不延伸超過載體框架且至PCB之基本熱路徑因此經由載體框架之一實施例。在所繪示之實例中， 展示載體框架連接至PCB接地平面。本發明亦預計具有多個切斷連接或部分連接之部分及/或一或多個孔隙之散熱器結構。此等結構可減小可原本由對具有一連續散熱器之一器件作用之熱膨脹或機械應變引起之應力。
2010年3月2日提出申請之針對「Chip-Scale Packaging with Protective Heat Spreader」之第12/716,197號美國專利申請案中闡述可與本發明之各種實施例一起使用之散熱器結構，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。
本發明預計其中多個預模製基板使得凸起器件及/或其他主動或被動組件能夠堆疊之實施例，如圖9中所展示。頂部圖式展示堆疊有兩個凸起器件(藉助底填充)之兩個預模製基板，其中使得兩個器件之間的電連接件圍繞堆疊中之下部器件之邊緣(雖然展示焊料球，但可使用任何適合結構)。中間圖式展示一被動組件(例如，電容器、電阻器、電感器等)之添加。底部圖式展示如上文所論述之經模製底填充之使用。習用或經模製底填充之所繪示使用僅係實例。本發明亦預計其中一個預模製基板/凸起器件總成可使用習用底填充而另一者使用經模製底填充之實施例。亦應理解，堆疊並不限於兩個總成，亦即，可針對特定應用適當地如本文中所闡述堆疊任意數目個器件及預模製基板。
圖10(a)至圖10(c)展示其中被動組件(在此情形中解耦電容器(組件0201))提供於晶粒之兩個邊緣上(連接於陰影矩 形墊之間)即使用於VDDH及VCC之外部墊僅沿晶粒之一個邊緣而提供之一實施例之不同視圖。圖10(a)展示上覆晶粒1004上之凸塊(例如，1002)至預模製基板之導電跡線之定向。圖10(b)展示用於連接至下伏PCB的預模製基板之導電跡線上之球、凸塊或柱(例如，1022)之圖案。圖10(c)展示下伏PCB之VX、VDDH及VSS/GND導電區域至導電平面連接至其的預模製基板之導電跡線上之球、凸塊或柱(例如，1022)之定向以及通孔至PCB之內部層之定向。
在晶粒之兩個邊緣上具有VDDH至VCC(或類比VDD)電容器之優點係在將電容器連接至所討論之晶粒中有效高頻率解耦由雜散電感限制。替代高電流要求晶片，雜散電感切換損失係重要的，此乃因其造成在1 Mhz切換頻率下使得1 nH等效於1莫姆損失之LI^2f切換損失。與晶粒之一個邊緣上之一電容器相比，在晶粒之兩個邊緣上具有兩個電容器將雜散電感切成兩半。可藉由在封裝之兩個邊緣上放置用於VDDH及VCC之外部墊達成相同結果，但彼將限制用於將調節器之切換節點路由出晶粒之位置。以此方式，雖然解耦使用內部路由提供於晶粒之兩個邊緣上，但外部路由限於在封裝之一個邊緣上具有VDDH及VCC且在封裝之另一邊緣上具有切換節點VX。此外，亦可將開機(BST)及驅動器解耦電容器共同定位於與高頻率解耦電容器相同之邊緣上。整合封裝內部之此等電容器可潛在地移除對在封裝外部具有用於此等連接件之I/O之需要(除使得其可接達以用於自動測試之需要之外)。如此，VCC-驅動器電源 及VBST-升壓電源之路由可提供於不具有在PCB可路由之要求而是僅在自動測試期間可接達之內部I/O上。整合任何種類之電容器係有利的，即使其在晶粒之僅一側上，此乃因相對於將比所展示之結構在實體上更遠離(達一習用引線框架之厚度)之一PCB安裝之電容器，至彼電容器之雜散電感減小了。本文中所闡述之預模製基板之實施例允許晶粒之兩個側上之電容器之整合，此乃因其內部路由之靈活性。相對於習用引線框架，此等預模製基板提供益處，此乃因來自導電跡線/引線之較細節距晶粒之支座可較低且電容器可較小因此允許用於電容器之較低電感連接件繞過器件。最後，電感在某種程度上由電流在閉合迴路中行進之距離及彼迴路中之返迴路徑之間的距離來界定。具有30 μm至40 μm節距之預電鍍之跡線另外增加晶粒與電容器之間的雜散電感之減小，此乃因高頻率電流將行進最近可能路徑(亦即，導體之表面)且因此導體之間距將不可避免地界定連接件之雜散電感。且雖然經整合被動組件展示於器件之邊緣處，但應理解，本發明預計其中被動組件可整合於柱之間(例如，圖6(a)至圖9中所繪示之結構中之任一者中所展示之柱之間)的此等結構中以進一步減小電感之實施例。
雖然僅電容器展示為經整合，但可將被動組件(諸如電阻器)整合至同一封裝中且因此比使用接通晶粒電阻器更容易地形成針對晶片之準確參考。此等關斷晶粒電阻器可具有受控溫度係數，但其溫度可緊密相關於晶粒溫度，此 乃因其接近於晶粒而共同封裝。再者，此等內部電阻器可僅在ATE測試期間可接達或無論如何皆不可自ATE接達而僅可透過晶粒-ATE測試介面接達。
隨著預模製基板中之導電跡線之間的距離變得較小，跡線之金屬(例如，銅)與其中跡線懸置之模製化合物之間的黏合可變成一可靠性問題。因此，本發明預計其中藉由控制跡線之厚度、跡線之寬度及/或跡線相對於彼此之間的距離改良或最佳化此黏合之實施例。另外，且根據某些實施例，可在跡線及螺柱中引入多種結構特徵以促進黏合。圖11中展示此等結構特徵之實例。在左手側圖式中，用於將預模製設備連接至PCB之跡線及螺柱兩者皆係波浪狀的以增加不同材料於其處介接之表面積量。在右手側圖式中，波浪狀跡線與直螺柱組合。各種各樣之其他跡線變化形式(例如，鋸齒狀、Z字形、不規則、邊緣穿孔、邊緣突出部等)可適合用於各種實施方案。某些結構特徵之另一優點係其可用以抑制模製材料中之裂縫沿材料傳播。亦即，導電跡線及螺柱之結構特徵可提供充當「止裂」之終止點。
根據一特定種類之實施例，一凸起器件(例如，待安裝於一預模製基板中之導電跡線上之一覆晶)上之外部連接件係如圖12及圖13(a)至13(c)中所展示之銅柱結構。應注意，此等結構亦可形成於預模製基板之導電跡線上。慣例上，此一結構之製作涉及一系列製程步驟，一「凸塊下金屬化」或UBM層藉由該等製程步驟引入於一晶粒墊開口上 方或先前形成於如圖12中所展示之晶粒墊開口上方之一銅棒重新分佈層(RDL)上。然後形成一重新鈍化(例如，聚醯亞胺(PI))，後續接著一濺鍍步驟以形成UBM來促進電鍍。然後在UBM上電鍍柱結構。除需要若干個製程步驟之外，此方法亦對可不適合用於某些應用之柱之寬度設置一限制(例如，由於配準容限等)。因此，根據一特定種類之實施例，提供用於在不具有一UBM之情形下直接在RDL銅上或直接在器件墊開口上(在具有或不具有UBM之情形下)形成銅柱之製程。
圖13(a)及圖13(b)展示直接形成於RDL銅上之一銅柱結構(此消除包含形成一UBM之製程步驟)(此乃因銅柱將易於電鍍於RDL銅上)。儘管亦可避免一鈍化之形成，但如圖13(b)中所展示，一鈍化(亦即，PI層)可跟在柱形成之後形成以抑制氧化及任何相關問題。
圖13(c)展示直接形成於器件之頂部金屬層之墊開口上但不具有習用技術中所需要之重新鈍化層(舉例而言，參見圖12之PI)且不具有其他實施例中所展示之RDL銅之銅柱結構。RDL之消除可係可行的，舉例而言，在其中器件之Rdson足夠低之實施方案(例如，圖5中所圖解說明之實施方案)中。如將瞭解，柱直接形成於墊開口上允許利用整個墊開口以用於形成柱而無一鈍化之任何侵蝕。在所繪示之實施例中，展示一UBM，此乃因其可係促進柱結構至器件之頂部金屬層之黏合所必需的。然而，本發明預計其中可不需要一UBM之實施例。如將理解，可柱形成之後視情 況應用一鈍化，圖13(b)中所展示。
根據一特定製程，可根據以下序列製作圖12之結構：
a.濺鍍Ti晶種層
b.濺鍍薄銅晶種導電層
c.放置光阻劑
d.電鍍經圖案化銅
e.剝離光阻劑
f.使用經電鍍銅作為一遮罩來剝離晶種層
g.放置聚醯亞胺(PI)
h.曝光
i.形成開口
j.固化PI
k.濺鍍Ti晶種
l.濺鍍Cu導電晶種
m.放置光阻劑
n.電鍍圖案化銅柱
o.電鍍焊料
p.剝離光阻劑
q.蝕刻晶種
上方中厚銅之存在減小對底部上厚銅之要求，因此可使銅較薄(3 μm而非12 μm)且仍得到巨大電益處，此乃因銅正使通常不厚於1 μm之一內部金屬層分流。
在可用於製作圖13(a)之結構之一替代製程流程中，消除數個步驟，此乃因最終封裝經模製。此等步驟(上文所闡 述之製程流程之g至l)之消除導致以下流程：
a.濺鍍Ti晶種層
b.濺鍍薄銅晶種導電層
c.放置第一光阻劑
d.電鍍經圖案化銅
e.放置乾式遮罩之第二光阻劑
f.電鍍銅柱
g.電鍍焊料
h.剝離兩種光阻劑
i.蝕刻單個晶種
如將瞭解，此方法相對於較早所闡述之流程消除顯著數目個處理步驟，藉此減小成本。可使用如上文流程中所闡述之所實施之銅柱或使用2010年7月27日提出申請之針對「Wafer-Level Chip Scale Package」之第12/844,649號美國專利申請案中所闡述之焊料棒結構來使預模製基板中之導電跡線更導電，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。銅與跡線串聯且因此用於有效地減小跡線之橫向導電性。可如2008年12月23日提出申請之針對「Flip Chip Power Switch With Under Bump Metallization Stack」之第12/343,372號美國專利申請案中所闡述實施在銅柱下方路由之RDL，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。可如2008年12月23日提出申請之針對「Conductive Routings in Integrated Circuits Using Under Bump Metallization」第 12/343,261號美國專利申請案中所闡述實施在不同不同電力軌之相互交叉列之間的接通晶粒連接件，該美國專利申請案之整個揭示內容出於所有目的以引用方式併入本文中。
應注意，可藉助適用於特定應用之各種各樣之組態實施根據各種實施例製作之預模製基板。舉例而言，就專用於一切換電壓調節器之端子中之各別者的預模製基板中之導電跡線而言，本文中所闡述之某些實施例具有相對不平衡組態。舉例而言，參見圖1至圖5，其中對應於VSS/GND之導電跡線數目顯著超過專用於Vin(VDDH)之彼等導電跡線。此係由於以下事實：此等設計意欲用於其中與側切換器之彼傳導時間相比調節器之低側切換器之傳導時間為大之低工作循環應用。然而，可根據本發明之實施例製作預模製基板以供與其中工作循環大得多之較平衡組態一起使用。圖14中展示其中VDDH及VSS/GND跡線之各別數目更平衡之一個此平面佈置(floor plan)組態。針對「Lead Assembly for a Flip-Chip Power Switch」之第12/344,134號美國專利申請案中闡述預模製基板可採用的更平衡之組態之其他實例，該美國專利申請案在上文以引用方式提及且併入本文中。舉例而言，參見彼應用之圖9及圖10。上文以引用方式提及且併入本文中之第6,278,264號美國專利中提供可針對其構造預模製基板的更平衡之平面佈置之其他實例。舉例而言，參見彼專利之圖3及圖8A至圖8G。另外，本發明預計其中高側切換器之傳導時間比低側切換器 之彼傳導時間長之其他實施例。因此，不應參照本文中所揭示之特定組態來限制本發明之範疇。
圖15圖解說明根據本發明之一實施例設計之一預模製基板可與其一起使用之又一平面佈置，其包含圖案VDDH/VX/GND/VX中之交替之導電跡線列。VX導電跡線與下伏PCB之一側上之一全VX平面連接。VDDH導電跡線與如所展示塑形之PCB之另一側上之一VDDH平面連接。通孔用於到達PCB之內部層。圖15中所繪示之組態之一個優點係零「電流換向損失」。亦即，無論高側切換器還是低側切換器正導電且當傳導自一者轉向至另一者時不改變，相同電流始終流動穿過VX跡線。此欲與其中電流必須透過VX跡線「重新分佈」(此在存在雜散電感之情形下致使針對切換器之某些部分之一經延遲接通時間，從而產生較高電阻及對應損失)之其他設計對比。
雖然已參照本發明特定實施例特別展示及闡述了本發明，但熟習此項技術者將理解，可在不背離本發明之精神及範疇之情形下對所揭示實施例之形式及細節做出改變。舉例而言，本文中所闡述之各種結構及技術可與多種封裝技術及基板結構相容，且保護範疇因此應不藉由參考特定技術或結構來限制。可藉助其來實踐各種本發明之實施例之其他技術及結構之實例包含(但不限於)：來自以色列之MCL有限公司之ALOX基板技術、來自加利福尼亞州雷德伍德城(Redwood City,California)之EoPlex Technologies公司之xLC基板技術、來自開曼群島(Cayman Islands)之ASM Pacific Technology有限公司之DreamPAK基板技術、來自新加坡之United Test and Assembly Center有限公司(UTAC)之高密度引線框架陣列(Hi-Density Leadframe Array，HLA)技術及來自中國東莞之ASAT有限公司之熱無引線陣列(TLA)技術(現在由香港的UTAC之母公司Global A&T Electronics有限公司擁有)。
最後，儘管本文中已參照各種實施例論述本發明之各種優點、態樣及目標，但將理解，本發明之範疇不應藉由參考此等優點、態樣及目標來限制。而是，本發明之範疇應參照隨附申請專利範圍來判定。
0201‧‧‧組件/解耦電容器/被動組件
1002‧‧‧凸塊
1004‧‧‧上覆晶粒
1022‧‧‧球/凸塊/柱
A‧‧‧細節區/區
a‧‧‧凸起器件
B‧‧‧細節區/區
b‧‧‧銅柱
C‧‧‧細節區/區
c‧‧‧焊料凸塊
d‧‧‧導電跡線
e‧‧‧螺柱
f‧‧‧焊料球
GND‧‧‧導電區域/跡線/導電跡線/圖案
M3‧‧‧金屬層3
PCB‧‧‧印刷電路板
VDDH‧‧‧導電區域/跡線/導電跡線/平面/圖案
VSS‧‧‧跡線/導電跡線/平面/導電區域
VX‧‧‧導電區域/導電跡線/跡線/導電平面/切換節點/圖案
圖1圖解說明一互連基板之一特定實施方案。
圖2圖解說明一互連基板之另一實施方案。
圖3圖解說明一互連基板之另一實施方案。
圖4圖解說明一互連基板之一特定實施方案可採用之導電凸塊之一圖案。
圖5(a)至圖5(e)圖解說明一互連基板之一特定實施方案之各種組件及導電凸塊之一對應圖案。
圖6(a)及圖6(b)圖解說明互連基板之其他實施方案及安裝於其上之對應器件。
圖7及圖8圖解說明具有安裝於其上之器件及散熱器之互連基板之實施方案。
圖9圖解說明經堆疊之互連基板及器件。
圖10(a)至圖10(c)圖解說明具有安裝於其上之被動組件 之一互連基板之一特定實施方案之各種態樣。
圖11圖解說明互連基板之特定實施方案中之導電元件之各種實施方案。
圖12及圖13(a)至圖13(c)圖解說明各種實施方案可採用之導電結構。
圖14及圖15圖解說明互連基板之特定實施方案之導電元件之特定配置。

Claims (37)

  1. 一種用於將一器件連接至一總成之互連基板，該器件由一器件節距來表徵且該總成由小於約800微米之一總成節距來表徵，該互連基板包括：複數個導電結構，該等導電結構中之每一者經組態以用於連接至該器件之複數個電路節點中之一對應者；其中對應於該器件之該等電路節點中之至少一者之該等導電結構與對應於該等電路節點中之至少另一者之該等導電結構在該互連基板中配置成一交替圖案；且其中該器件節距係該總成節距之約一半，且其中該等導電結構中之至少某些導電結構之一寬度係該等導電結構中之該至少某些導電結構之間的一間距之至少約兩倍。
  2. 如請求項1之互連基板，其中該器件之該等電路節點中之至少某些電路節點對應於一或多個功率器件之端子。
  3. 如請求項2之互連基板，其中該一或多個功率器件係一切換調節器之部分。
  4. 如請求項2之互連基板，其中該一或多個功率器件包括兩個功率器件，且其中該等端子包括兩個功率節點端子及一切換端子。
  5. 如請求項4之互連基板，其中對應於該等功率節點端子及該切換端子之該等導電結構經組態以用於連接至該總成之對應導電結構。
  6. 如請求項1之互連基板，其中該互連基板具有用於連接 至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，該等導電結構中之特定導電結構未到達該互連基板之該邊緣。
  7. 如請求項6之互連基板，其中未到達該互連基板之該邊緣之該等特定導電結構經組態以將該器件之一對應電路節點連接至該總成之一對應導電結構，該對應導電結構之至少一部分直接位於該器件下方。
  8. 如請求項6之互連基板，其中該互連基板之該等導電結構之一大部分直接位於該器件下方。
  9. 如請求項1之互連基板，其中該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，該等導電結構中之特定導電結構至少延伸至該互連基板之該邊緣。
  10. 如請求項1之互連基板，其中該等導電結構中之至少某些導電結構具有一長度及一寬度，且其中該長度係該寬度之至少四倍。
  11. 如請求項1之互連基板，其中該等導電結構中之至少某些導電結構各自在其上具有一或多個螺柱，該一或多個螺柱經組態以用於連接至該總成之一導電結構。
  12. 如請求項11之互連基板，其中該等螺柱經組態以接受焊料。
  13. 如請求項12之互連基板，其中該等螺柱包含經電鍍焊料或預形成之焊料。
  14. 如請求項11之互連基板，其中該等螺柱中之至少某些螺 柱係圓形的，且在該等導電結構中之至少某些導電結構上存在多個圓形螺柱。
  15. 如請求項14之互連基板，其中該等圓形螺柱中之至少某些螺柱包括焊料球。
  16. 如請求項11之互連基板，其中該等螺柱中之至少某些螺柱包括細長螺柱。
  17. 如請求項1之互連基板，其中對應於該器件之該等電路節點中之一第一者之該等導電結構在該互連基板之一主要平面定向中沿一第一方向延伸，且其中對應於該器件之該第一電路節點之該等導電結構藉由沿一第二方向延伸之一共同導電結構在該互連基板中彼此連接，在該互連基板之該主要平面定向中該第二方向不平行於該第一方向。
  18. 如請求項17之互連基板，其中該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且其中對應於該第一電路節點之該等導電結構及該共同導電結構未到達該互連基板之該邊緣。
  19. 如請求項17之互連基板，其中該互連基板具有用於連接至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且其中該共同導電結構安置於該互連基板之該邊緣之一部分附近，藉此允許將對應於該器件之該第一電路節點之該等導電結構連接至該總成之一單個導電結構。
  20. 如請求項17之互連基板，其中該互連基板具有用於連接 至該器件之一第一表面及用於連接至該總成之一第二表面以及一邊緣，且其中該共同導電結構安置於該互連基板之該邊緣之一第一部分附近，該互連基板進一步包括在該互連基板中連接對應於該器件之該等電路節點中之一第二者之該等導電結構之一第二共同導電結構，且其中該第二共同導電結構安置於該互連基板之該邊緣之一第二部分附近。
  21. 如請求項1之互連基板，其中對應於該等電路節點中之兩者或兩者以上之該等導電結構安置於由導電材料之一第一寬度與間距比表徵的該互連基板之一第一區域中，且其中對應於該等電路節點中之兩個或兩個以上其他電路節點之該等導電結構安置於由不同於該第一寬度與間距比的該導電材料之一第二寬度與間距比表徵的該互連基板之一第二區域中。
  22. 如請求項21之互連基板，其中該裝置包括一切換調節器之至少一部分，且其中安置於該互連基板之該第一區域中之該等導電結構對應於該切換調節器之一功率級之功率級節點，且其中安置於該互連基板之該第二區域中之該等導電結構對應於該切換調節器之控制電路之控制電路節點。
  23. 如請求項1之互連基板，其中該裝置包括一或多個功率器件及相關聯之控制電路，且其中該等導電結構中之若干第一者對應於該一或多個功率器件之若干端子，且其中該等導電結構中之若干第二者對應於該控制電路之若 干控制電路節點。
  24. 如請求項23之互連基板，其中該一或多個功率器件及該相關聯之控制電路係一切換調節器之部分。
  25. 如請求項1之互連基板，其中該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上，該互連基板進一步包括形成於該等導電結構之該等所曝露部分上且經組態以用於與該器件連接之複數個導電凸塊。
  26. 如請求項25之互連基板，其中該等導電凸塊包括球、凸塊、柱或螺柱中之任一者。
  27. 如請求項25之互連基板，其中該等導電凸塊包括直接形成於該等導電結構上之銅柱。
  28. 如請求項25之互連基板，其中該等導電凸塊包括銅柱，且其中該等銅柱形成於在該等導電結構上形成之一凸塊下金屬化(UBM)層上。
  29. 如請求項25之互連基板，其中該等導電凸塊包括銅柱，且其中該等銅柱減小該等導電結構之橫向導電性。
  30. 如請求項1之互連基板，其中該互連基板具有用於連接至該器件之一第一表面，該等導電結構中之至少某些導電結構之部分曝露於該互連基板之該第一表面上且經組態以用於連接至形成於該器件上之導電凸塊。
  31. 如請求項30之互連基板，其中該等導電凸塊包括球、凸塊、柱或螺柱中之任一者。
  32. 如請求項1之互連基板，其進一步包括經組態以用於傳 導來自該器件之熱之一導熱結構。
  33. 如請求項32之互連基板，其中該導熱結構之至少一部分延伸穿過該互連基板，藉此使得能夠將來自該器件之該熱傳導至該總成。
  34. 如請求項1之互連基板，其中該等導電結構中之至少某些導電結構經組態以用於將離散被動電路元件安裝於該互連基板上。
  35. 如請求項1之互連基板，其中該等導電結構中之至少某些導電結構包含促進與該互連基板之一介入介質之黏合之結構特徵，其中該等結構特徵包含波浪狀邊緣、鋸齒狀邊緣、Z字形邊緣、不規則邊緣、邊緣穿孔或邊緣突出部中之一或多者。
  36. 如請求項1之互連基板，其中配置成該交替圖案之該等導電結構包括分別對應於第一電路節點及第二電路節點之細長結構，該等細長結構在該互連基板中沿一第一方向定向，其中對應於該第一電路節點之該等細長結構與對應於該第二電路節點之該等細長結構交替。
  37. 如請求項36之互連基板，其中配置成該交替圖案之該等導電結構中之每一者具有係其寬度之至少四倍之一長度，對應於該第一電路節點之該等導電結構中之每一者在其上具有位於該互連基板之一第一邊緣附近的該導電結構之一端處之一或多個螺柱，且對應於該第二電路節點之該等導電結構中之每一者在其上具有位於與該第一邊緣相對的該互連基板之一第二邊緣附近的該導電結構 之一端處之一或多個螺柱，且其中對應於該第一電路節點之該等導電結構上之該等螺柱經組態以用於連接至該總成上之一第一導電平面，且對應於該第二電路節點之該等導電結構上之該等螺柱經組態以用於連接至該總成上之一第二導電平面，該第一導電平面與該第二導電平面係毗鄰而不重疊的。
TW101137026A 2011-10-07 2012-10-05 互連基板之功率管理應用 TW201322840A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161544945P 2011-10-07 2011-10-07
US13/644,693 US9099340B2 (en) 2011-10-07 2012-10-04 Power management applications of interconnect substrates

Publications (1)

Publication Number Publication Date
TW201322840A true TW201322840A (zh) 2013-06-01

Family

ID=48041350

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101137026A TW201322840A (zh) 2011-10-07 2012-10-05 互連基板之功率管理應用

Country Status (5)

Country Link
US (4) US9099340B2 (zh)
CN (1) CN103975427B (zh)
DE (1) DE112012004185T5 (zh)
TW (1) TW201322840A (zh)
WO (1) WO2013052672A2 (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103975427B (zh) 2011-10-07 2017-03-01 沃尔泰拉半导体公司 互连衬底的功率管理应用
US8624131B2 (en) * 2011-10-18 2014-01-07 Shenzhen China Star Optoelectronics Technology Co., Ltd. Chip-on-film panel structure
US9131602B2 (en) * 2012-02-24 2015-09-08 Mediatek Inc. Printed circuit board for mobile platforms
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
JP6032070B2 (ja) * 2013-03-13 2016-11-24 ソニー株式会社 半導体装置、半導体装置の製造方法
TWI552039B (zh) * 2014-06-27 2016-10-01 群創光電股份有限公司 觸控顯示裝置
US9379079B1 (en) * 2014-12-29 2016-06-28 Mediatek Inc. Flip chip scheme and method of forming flip chip scheme
KR20160124328A (ko) * 2015-04-16 2016-10-27 삼성전기주식회사 칩 부품 및 그 제조방법
US10128123B2 (en) * 2015-05-22 2018-11-13 Imec Vzw Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
US10090251B2 (en) * 2015-07-24 2018-10-02 Infineon Technologies Ag Semiconductor chip having a dense arrangement of contact terminals
JP6653541B2 (ja) * 2015-09-14 2020-02-26 ローム株式会社 半導体装置
EP3154084A3 (en) * 2015-09-16 2017-04-26 MediaTek Inc. Semiconductor package using flip-chip technology
US20170105278A1 (en) * 2015-10-13 2017-04-13 Google Inc. Integrated heat spreader and emi shield
US9875988B2 (en) 2015-10-29 2018-01-23 Semtech Corporation Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
US20170271175A1 (en) * 2016-03-16 2017-09-21 Qualcomm Incorporated Exposed die mold underfill (muf) with fine pitch copper (cu) pillar assembly and bump density
US10070562B2 (en) * 2016-05-17 2018-09-04 Ge Aviation Systems Llc Method and apparatus for heat-dissipation in an avionics chassis
US10325807B2 (en) 2016-12-14 2019-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
US10756042B2 (en) * 2016-12-26 2020-08-25 Intel IP Corporation Multi-layer redistribution layer for wafer-level packaging
CN107172826A (zh) * 2017-06-15 2017-09-15 深圳市泰和安科技有限公司 一种带有铜柱的印刷电路板的制作方法
US10163773B1 (en) * 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
US20190181115A1 (en) 2017-12-08 2019-06-13 Dialog Semiconductor (Uk) Limited Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package
US11114359B2 (en) 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
US10784199B2 (en) * 2019-02-20 2020-09-22 Micron Technology, Inc. Component inter-digitated VIAS and leads
US11069600B2 (en) 2019-05-24 2021-07-20 Infineon Technologies Ag Semiconductor package with space efficient lead and die pad design
US11552045B2 (en) 2020-08-17 2023-01-10 Micron Technology, Inc. Semiconductor assemblies with redistribution structures for die stack signal routing
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
US11562987B2 (en) 2021-04-16 2023-01-24 Micron Technology, Inc. Semiconductor devices with multiple substrates and die stacks

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2940475B2 (ja) * 1996-06-24 1999-08-25 日本電気株式会社 Ｉｃのパッケージ、ｉｃのプローバ及びそれらの製造方法
US5952726A (en) * 1996-11-12 1999-09-14 Lsi Logic Corporation Flip chip bump distribution on die
US5859474A (en) * 1997-04-23 1999-01-12 Lsi Logic Corporation Reflow ball grid array assembly
US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
US6828666B1 (en) * 1998-03-21 2004-12-07 Advanced Micro Devices, Inc. Low inductance power distribution system for an integrated circuit chip
US6278264B1 (en) * 2000-02-04 2001-08-21 Volterra Semiconductor Corporation Flip-chip switching regulator
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6713823B1 (en) * 2002-03-08 2004-03-30 Volterra Semiconductor Corporation Conductive routings in integrated circuits
US7038917B2 (en) * 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
US20040188811A1 (en) * 2003-03-24 2004-09-30 Intel Corporation Circuit package apparatus, systems, and methods
US20050045697A1 (en) 2003-08-26 2005-03-03 Lacap Efren M. Wafer-level chip scale package
KR101237172B1 (ko) * 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US7521792B2 (en) * 2004-02-03 2009-04-21 Infineon Technologies Ag Semiconductor package with heat spreader
US7269813B2 (en) * 2004-11-19 2007-09-11 Alcatel Off-width pitch for improved circuit card routing
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
DE102005036116B4 (de) * 2005-08-01 2012-03-22 Infineon Technologies Ag Leistungshalbleitermodul
US20160343593A1 (en) * 2006-05-10 2016-11-24 Amkor Technology, Inc. Semiconductor package including premold and method of manufacturing the same
JP4929857B2 (ja) * 2006-06-12 2012-05-09 株式会社日立製作所 半導体装置
DE102007034402B4 (de) 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
JP4916300B2 (ja) * 2006-12-19 2012-04-11 新光電気工業株式会社 多層配線基板
CN101675518B (zh) * 2007-05-10 2012-12-05 飞思卡尔半导体公司 芯片上功率引线球栅阵列封装
US8085553B1 (en) 2007-12-27 2011-12-27 Volterra Semiconductor Corporation Lead assembly for a flip-chip power switch
US8169081B1 (en) 2007-12-27 2012-05-01 Volterra Semiconductor Corporation Conductive routings in integrated circuits using under bump metallization
US7989953B1 (en) 2007-12-28 2011-08-02 Volterra Semiconductor Corporation Flip chip power switch with under bump metallization stack
CN101236940B (zh) * 2008-02-27 2010-08-25 威盛电子股份有限公司 重配置线路层的线路结构
US8350375B2 (en) * 2008-05-15 2013-01-08 Lsi Logic Corporation Flipchip bump patterns for efficient I-mesh power distribution schemes
US10251273B2 (en) * 2008-09-08 2019-04-02 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard
US9070662B2 (en) 2009-03-05 2015-06-30 Volterra Semiconductor Corporation Chip-scale packaging with protective heat spreader
JP5526575B2 (ja) * 2009-03-30 2014-06-18 凸版印刷株式会社 半導体素子用基板の製造方法および半導体装置
US8400784B2 (en) * 2009-08-10 2013-03-19 Silergy Technology Flip chip package for monolithic switching regulator
US20110163428A1 (en) * 2010-01-05 2011-07-07 Manolito Fabres Galera Semiconductor packages with embedded heat sink
CN103975427B (zh) 2011-10-07 2017-03-01 沃尔泰拉半导体公司 互连衬底的功率管理应用
US8823345B2 (en) 2012-10-19 2014-09-02 Linear Technology Corporation Magnetic field cancellation in switching regulators

Also Published As

Publication number Publication date
US10748845B2 (en) 2020-08-18
US10332827B2 (en) 2019-06-25
WO2013052672A2 (en) 2013-04-11
CN103975427A (zh) 2014-08-06
WO2013052672A3 (en) 2013-07-11
US9520342B2 (en) 2016-12-13
US20190341344A1 (en) 2019-11-07
CN103975427B (zh) 2017-03-01
US20130087366A1 (en) 2013-04-11
US20170125335A1 (en) 2017-05-04
US20150303132A1 (en) 2015-10-22
DE112012004185T5 (de) 2014-06-26
US9099340B2 (en) 2015-08-04

Similar Documents

Publication Publication Date Title
US10748845B2 (en) Power management application of interconnect substrates
US10861760B2 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
US11848294B2 (en) Semiconductor device
US8227910B2 (en) Apparatus for thermally enhanced semiconductor package
US7618849B2 (en) Integrated circuit package with etched leadframe for package-on-package interconnects
US8680676B1 (en) Semiconductor package with under bump metallization routing
US20140070329A1 (en) Wireless module with active and passive components
KR20150084929A (ko) 열적 및 전기적 전도성 언더필을 구비한 마이크로전자 어셈블리
US10332832B2 (en) Method of manufacturing an electronics package using device-last or device-almost last placement
TW201603223A (zh) 於半導體裝置中形成為金屬線互連之凸塊連結
US9728507B2 (en) Cap chip and reroute layer for stacked microelectronic module
TWI816063B (zh) 半導體裝置及製造方法
US9842827B2 (en) Wafer level system in package (SiP) using a reconstituted wafer and method of making
US20230317581A1 (en) Flip chip package for semiconductor devices