JP6116768B2 - スモールフォームファクタまたはウェアラブルデバイスのための集積回路パッケージ技術および構成 - Google Patents
スモールフォームファクタまたはウェアラブルデバイスのための集積回路パッケージ技術および構成 Download PDFInfo
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- JP6116768B2 JP6116768B2 JP2016559146A JP2016559146A JP6116768B2 JP 6116768 B2 JP6116768 B2 JP 6116768B2 JP 2016559146 A JP2016559146 A JP 2016559146A JP 2016559146 A JP2016559146 A JP 2016559146A JP 6116768 B2 JP6116768 B2 JP 6116768B2
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- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Description
Claims (22)
- 第1の面と、前記第1の面に対向して配置された第2の面と、前記第1の面および前記第2の面の間に配置され基板の周囲を画定する側壁と、を有する前記基板と、
前記基板の前記第1の面および前記第2の面の間に配置された複数の基板貫通ビア(TSV)と、
前記第1の面上に配置され、第1の誘電体層の面内の1または複数のダイの複数の電気信号を送信する複数の電気配線特徴部を含む、前記第1の誘電体層と、
前記第2の面上に配置され、第2の誘電体層の面内の前記1または複数のダイの複数の電気信号を送信する複数の電気配線特徴部を含む、前記第2の誘電体層とを備え、
前記側壁は、前記側壁のそれぞれの表面上の前記1または複数のダイの取り付けを受け入れる、装置。 - 前記複数のTSVのうち1または複数のTSVは、前記1または複数のダイのうち、第1のダイおよび第2のダイの間で、複数の電気信号を送信する、請求項1に記載の装置。
- 前記複数のTSVのうち1または複数のTSVは、前記基板から放熱するサーマルTSVである、請求項1に記載の装置。
- 前記側壁上に配置され、前記1または複数のダイのうち、第1のダイおよび第2のダイの間で複数の電気信号を送信する、複数の電気配線特徴部をさらに備える、請求項1に記載の装置。
- 前記側壁に取り付けられた前記1または複数のダイのうち、第1のダイと、
前記側壁に取り付けられた前記1または複数のダイのうち、第2のダイと、をさらに備え、
前記第1のダイおよび前記第2のダイは、電気的にともに結合される、請求項1から4のいずれか一項に記載の装置。 - 前記側壁は、3つまたはそれより多くの面を有し、
前記第1のダイは、前記3つまたはそれより多くの面のうち第1の面と結合され、
前記第2のダイは、前記3つまたはそれより多くの面のうち第2の面と結合される、請求項5に記載の装置。 - 前記第1のダイは、前記第1の誘電体層および/または前記第2の誘電体層の複数の電気配線特徴部によって、前記第2のダイと電気的に結合される、請求項5に記載の装置。
- 前記第1のダイは、前記側壁上に配置された複数の電気配線特徴部によって、前記第2のダイと電気的に結合される、請求項5に記載の装置。
- 前記第1のダイおよび前記第2のダイを、少なくとも部分的に封止する封止剤をさらに備える、請求項5に記載の装置。
- 前記第1のダイと、前記第2のダイと、前記封止剤との上に配置された熱スプレッダフィルムをさらに備える、請求項9に記載の装置。
- 前記第2の誘電体層と結合された、電力面またはグラウンド面をさらに備える、請求項1から4のいずれか一項に記載の装置。
- 前記基板および前記第1の誘電体層の間の、前記基板の前記第1の面上に配置されたデバイス層をさらに備え、前記デバイス層は1または複数の能動デバイスを含む、請求項1から4のいずれか一項に記載の装置。
- 前記基板は、半導体材料またはガラスを含む、請求項1から4のいずれか一項に記載の装置。
- ウェアラブルアーティクル、スマートペン、または財布を含み、
前記ウェアラブルアーティクル、前記スマートペン、前記財布は、請求項1から13のいずれか一項に記載の装置を備える、アセンブリ。 - 前記ウェアラブルアーティクルは、ボタンまたは眼鏡フレームを備える、請求項14に記載のアセンブリ。
- 第1の面と、前記第1の面に対向して配置された第2の面と、前記第1の面および第2の面の間に配置され基板の周囲を画定する側壁と、を有する基板を提供する段階と、
前記基板の前記第1の面および前記第2の面の間に複数の基板貫通ビア(TSV)を形成する段階と、
前記第1の面上に、第1の誘電体層の面内の1または複数のダイの複数の電気信号を送信する複数の電気配線特徴部を含む、前記第1の誘電体層を形成する段階と、
前記第2の面上に配置され、第2の誘電体層の面内の前記1または複数のダイの複数の電気信号を送信する複数の電気配線特徴部を含む、前記第2の誘電体層を形成する段階とを備え、
前記側壁は、前記側壁のそれぞれの表面上の前記1または複数のダイの取り付けを受け入れる、方法。 - 前記1または複数のダイのうち第1のダイを前記側壁に取り付ける段階と、
前記1または複数のダイのうち第2のダイを前記側壁に取り付ける段階とをさらに備え、
前記第1のダイおよび前記第2のダイは、前記第1の誘電体層および/または前記第2の誘電体層の前記複数の電気配線特徴部と、電気的に結合される、請求項16に記載の方法。 - 複数のダイを柔軟な封止剤に封止する段階と、
前記複数のダイ上に複数の電気配線特徴部を形成する段階と、
前記複数のダイを基板の側壁のそれぞれの表面に結合する段階とを備え、
前記基板は第1の面と、前記第1の面に対向して配置された第2の面とを有し、
前記側壁は、前記第1の面および前記第2の面の間に配置され前記基板の周囲を画定し、
複数の基板貫通ビア(TSV)は、前記基板の前記第1の面および前記第2の面の間に配置される、方法。 - 前記複数のダイを前記柔軟な封止剤に封止する段階は、
前記複数のダイのアクティブ面をキャリアに結合する段階と、
前記複数のダイ上に前記柔軟な封止剤を堆積する段階と、
前記複数のダイを前記キャリアから分離する段階とを含む、請求項18に記載の方法。 - 前記複数の電気配線特徴部を形成する段階は、
金属箔を前記複数のダイのアクティブ面上に堆積する段階と、
複数のパッドまたはトレースを形成すべく前記金属箔をパターニングする段階と、
半田マスク層を前記複数のパッドまたはトレース上に堆積する段階とを含む、請求項18に記載の方法。 - 前記複数のダイを前記基板の前記側壁のそれぞれの表面に結合する段階は、
前記柔軟な封止剤を前記基板の前記側壁を囲む前記複数のダイで包み込む段階と、
前記柔軟な封止剤を硬化すべく熱処理を適用する段階を含む、請求項18から20のいずれか一項に記載の方法。 - 前記複数のダイを前記側壁のそれぞれの表面に結合するより前に、熱スプレッダフィルムを前記複数のダイの非アクティブ面に結合する段階をさらに含む、請求項18から20のいずれか一項に記載の方法。
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