CN105590908A - 集成电路封装技术和小形状因子或可穿戴装置的配置 - Google Patents
集成电路封装技术和小形状因子或可穿戴装置的配置 Download PDFInfo
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- CN105590908A CN105590908A CN201510655101.7A CN201510655101A CN105590908A CN 105590908 A CN105590908 A CN 105590908A CN 201510655101 A CN201510655101 A CN 201510655101A CN 105590908 A CN105590908 A CN 105590908A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000010168 coupling process Methods 0.000 claims description 37
- 238000005859 coupling reaction Methods 0.000 claims description 37
- 230000008878 coupling Effects 0.000 claims description 36
- 239000000565 sealant Substances 0.000 claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 16
- 239000003795 chemical substances by application Substances 0.000 claims description 15
- 238000007789 sealing Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 3
- 238000000429 assembly Methods 0.000 claims 2
- 230000000712 assembly Effects 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 23
- 238000004891 communication Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 238000004364 calculation method Methods 0.000 description 12
- 238000003466 welding Methods 0.000 description 9
- MKYBYDHXWVHEJW-UHFFFAOYSA-N N-[1-oxo-1-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propan-2-yl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(C(C)NC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 MKYBYDHXWVHEJW-UHFFFAOYSA-N 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229920001903 high density polyethylene Polymers 0.000 description 3
- 239000004700 high-density polyethylene Substances 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003447 ipsilateral effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- -1 polysiloxanes Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920005573 silicon-containing polymer Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- A—HUMAN NECESSITIES
- A44—HABERDASHERY; JEWELLERY
- A44B—BUTTONS, PINS, BUCKLES, SLIDE FASTENERS, OR THE LIKE
- A44B1/00—Buttons
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C1/00—Purses; Money-bags; Wallets
- A45C1/06—Wallets; Notecases
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B43—WRITING OR DRAWING IMPLEMENTS; BUREAU ACCESSORIES
- B43K—IMPLEMENTS FOR WRITING OR DRAWING
- B43K29/00—Combinations of writing implements with other articles
-
- G—PHYSICS
- G02—OPTICS
- G02C—SPECTACLES; SUNGLASSES OR GOGGLES INSOFAR AS THEY HAVE THE SAME FEATURES AS SPECTACLES; CONTACT LENSES
- G02C11/00—Non-optical adjuncts; Attachment thereof
- G02C11/10—Electronic devices other than hearing aids
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/1613—Constructional details or arrangements for portable computers
- G06F1/163—Wearable computers, e.g. on a belt
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
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Abstract
本发明涉及集成电路封装技术和小形状因子或可穿戴装置的配置。本公开的实施例被指向集成电路(IC)封装技术和用于小形状因子或可穿戴装置的配置。在一个实施例中,设备可包括:衬底,其具有第一侧面和设置成与第一侧面相对的第二侧面以及设置在第一侧面和第二侧面之间的侧壁,侧壁限定衬底的周边;以及多个穿过衬底的通孔(TSV),其设置在衬底的第一侧面和第二侧面之间;以及第一介质层,其设置在第一侧面上并包括电气路由特征以在第一介质层的平面中路由一个或多个管芯的电信号。可描述和/或要求保护其它实施例。
Description
技术领域
本公开的实施例通常涉及集成电路的领域,且更具体地涉及集成电路(IC)封装技术和小形状因子可穿戴装置的配置。
背景技术
具有集成电路(IC)部件诸如例如管芯和传感器的可穿戴和小形状因子装置正在出现。然而,从在可穿戴或小形状因子装置中的这样的IC部件移除热依然是挑战。此外,传统封装可能太大而不允许这样的IC部件在小形状因子装置中被集成和电耦合在一起。
附图说明
结合附图通过下面的详细描述将容易理解实施例。为了便于这个描述,相似的参考数字指明相似的结构元件。实施例作为示例而不是作为限制在附图的图中示出。
图1A-C示意性示出根据一些实施例的示例集成电路(IC)封装组件的视图。
图2A-B示意性示出根据一些实施例的包括电源层或接地层的示例集成电路(IC)封装组件的视图。
图3A-C示意性示出根据一些实施例的包括在侧壁上的电气路由特征的示例集成电路(IC)封装组件的视图。
图4A-K示意性示出根据一些实施例的在制造的各种阶段期间的示例集成电路(IC)封装组件的视图。
图5示意性示出根据一些实施例的用于制造IC封装组件的方法的流程图。
图6示意性示出根据一些实施例的用于制造IC封装组件的另一方法的流程图。
图7-8示意性示出根据一些实施例的可合并如本文所述的集成电路(IC)封装组件的示例制造物品。
图9示意性示出根据一些实施例的包括如本文所述的IC封装组件的计算装置。
具体实施方式
本公开的实施例描述小形状因子或可穿戴装置的集成电路(IC)封装技术和配置。在下面的描述中,将使用通常由本领域中的技术人员使用的术语来描述例证性实现的各种方面以将他们的工作的实质传达给本领域中的其他技术人员。然而,对本领域中的技术人员将明显的是,本公开的实施例可在只有所述方面中的仅仅一些的情况下被实践。为了解释的目的,阐述了特定的数字、材料和配置,以便提供对例证性实现的透彻理解。然而,对本领域中的技术人员将明显的是,本公开的实施例可在没有特定细节的情况下被实践。在其它实例中,公知的特征被省略或简化以便不使例证性实现难理解。
在下面的详细描述中,参考形成其一部分的附图,其中相似的数字始终指明相似的部件,且其中作为例证示出本公开的主题可被实践的实施例。应理解,可利用其它实施例,且可做出结构或逻辑改变而不偏离本公开的范围。因此,下面的详细描述不应在限制性意义上被理解,且实施例的范围由所附权利要求及其等效形式限定。
为了本公开的目的,短语“A和/或B”意指(A)、(B)或(A和B)。为了本公开的目的,短语“A、B和/或C”意指(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。该描述可使用基于透视的描述,例如顶部/底部、在……中/在……外、在……之上/在……之下等。这样的描述仅仅用于便于讨论且并不意在将本文描述的实施例的应用限制到任何特定的取向。
该描述可使用短语“在一个实施例中”或“在各实施例中”,其可以均指相同或不同的实施例中的一个或多个。此外,如关于本公开的实施例使用的术语“包括”、“包含”、“具有”等是同义的。在本文可使用术语“与…耦合”连同其派生词。“耦合”可意指下面的内容中的一个或多个。“耦合”可意指两个或更多元件直接物理或电接触。然而,“耦合”也可意指两个或更多元件间接地彼此接触,但然而也仍然彼此协作或交互作用,并可意指一个或多个其它元件耦合或连接在被认为彼此耦合的元件之间。术语“直接耦合”可意指两个或更多元件直接接触。
在各种实施例中,短语“第一特征形成、沉积或以其它方式设置在第二特征上”可意指第一特征被形成、沉积或设置在第二特征之上,且第一特征的至少一部分可与第二特征的至少一部分直接接触(例如直接物理和/或电接触)或间接接触(例如具有在第一和第二特征之间的一个或多个其它特征)。
如在本文使用的,术语“模块”可以指的是下列项、是下列项的部分或包括下列项:专用集成电路(ASIC)、电子电路、芯片上系统(SoC)、处理器(共享、专用或组)和/或执行一个或多个软件或固件程序的存储器(共享、专用或组)、组合逻辑电路和/或提供所述功能的其它适当部件。
图1A-C示意性示出根据一些实施例的示例集成电路(IC)封装组件100的视图。图1A示意性示出IC封装组件100的顶视图。图1B示意性示出IC封装组件100的透视图。图1C示意性示出IC封装组件100的部分透明透视图。在图1C中透明地描绘衬底102和介质层102a、102b。
根据各种实施例,图1A-C的IC封装组件100可包括衬底102。在一些实施例中,衬底102可由半导体材料或玻璃组成。例如,在一些实施例中,衬底102可以是硅桥/插入机构。在其它实施例中,衬底102可由与互补金属氧化物半导体(CMOS)制造技术兼容的其它适当的材料组成以在衬底102上形成电路。
衬底102可具有第一侧面S1和设置成与第一侧面S1相对的第二侧面S2,如可看到的。在一些实施例中,一个或多个穿过衬底的通孔(在下文中“TSV104”)诸如例如穿过硅的通孔可穿过衬底102在第一侧面S1和第二侧面S2之间形成。TSV104可包括填充有导电材料诸如例如铜的管道,并可根据任何适当的工艺来形成。
在一些实施例中,一个或多个TSV104可配置成路由与衬底102耦合的一个或多个管芯(例如在下文中“管芯110”)的电信号,或可配置成在两个或更多管芯110之间路由电信号。例如,在一些实施例中,TSV104可配置成路由输入/输出(I/O)和/或电源/接地信号。在一些实施例中,TSV104中的一个或多个可以是配置成将热量从衬底102路由掉的热TSV。例如,热TSV可在与热TSV的纵长尺寸平行的方向上传导热。在一些实施例中,热TSV可以不配置成路由电信号。在一些实施例中,可在衬底102中实现热TSV和信号TSV的组合。
在一些实施例中,第一介质层102a可在第一侧面S1上形成,而第二介质层102b可在衬底102的第二侧面S2上形成。第一介质层102a和第二介质层102b中的每一个可包括在其中形成的电气路由特征106以路由(例如管芯110的)电信号。在一些实施例中,电气路由特征106可配置成在第一介质层102a或第二介质层102b的平面中(例如水平地)路由电信号。在一些实施例中,介质层102a、102b可用作钝化层。
在一些实施例中,电气路由特征106可包括例如再分布线作为迹线。在其它实施例中,电气路由特征106可包括沟槽和/或通孔。例如,在一些实施例中,介质层102a、102b中的一个或两个可代表堆叠在一起的多个介质层。在这样的实施例中,电气路由特征106可包括配置成在第一介质层102a或第二介质层102b的平面中水平地路由电信号的沟槽和在堆叠的介质层之间垂直地路由电信号的通孔。
在一些实施例中,电气路由特征106耦合TSV104中的两个或更多TSV,如可在图1A-C中描绘的示例中看到的。在一些实施例中,电气路由特征106可耦合TSV104中的一个或多个TSV与在介质层102a、102b的终止外围边缘处的管芯110中的一个管芯,如可在图1A-C中描绘的示例中看到的。电气路由特征106可由导电材料诸如例如铜组成。在其它实施例中,电气路由特征106可由其它适当的材料组成。
在一些实施例中,介质层102a、102b可由二氧化硅(SiO2)或氮化硅(SiN)组成。在其它实施例中,介质层102a、102b可由其它适当的介质材料组成。可使用在管芯上形成后端层的适当技术诸如例如CMOS制造技术来形成介质层102a、102b。衬底102可包括设置在衬底102的第一侧面S1和第二侧面S2之间的侧壁SW,如可看到的。在一些实施例中,侧壁SW可基本上与第一侧面S1和第二侧面S2垂直。侧壁可限定衬底102的周边(例如终止边缘)。在一些实施例中,在附着管芯110之前,侧壁SW可配置成接纳在侧壁SW的相应表面上的管芯110的附着。例如,相应的表面可依尺寸被制造成接纳管芯110。
根据各种实施例,管芯110可与侧壁SW的相应表面耦合。例如,管芯110可包括管芯级互连(有时被称为第一级互连(FLI)),诸如例如隆起焊盘、支柱或使管芯110与电气路由特征106和/或TSV104电耦合的其它类似的特征。在一些实施例中,管芯110的有源侧面可与侧壁SW耦合。在一些实施例中,管芯110可基本上与介质层102a、102b中的一个或两个齐平,如可看到的,或管芯110可以以其它方式与介质层102a、102b的至少一部分重叠以便于在管芯110和电气路由特征106之间的电耦合。在一些实施例中,管芯110可以是嵌入式堆叠管芯(例如,如在图1A的左侧壁上描绘的)。在一些实施例中,管芯110可以是处理器、存储器、SoC或ASIC,包括处理器、存储器、SoC或ASIC或者是处理器、存储器、SoC或ASIC的一部分。
在一些实施例中,侧壁SW可具有三个或更多侧面。在所描绘的示例中,侧壁SW具有在正方形轮廓中的四个侧面,其中管芯110耦合到不同的侧面。然而,在其它实施例中,侧壁SW可具有在三角形轮廓中的三个侧面或在多边形轮廓中的五个或更多个侧面。轮廓形状可以是对称的或非对称的。例如,在一些实施例中,侧壁SW可具有在具有不同长度的至少两个侧边的矩形形状中的四个侧面。侧面可配置成具有允许IC封装组件100实现为期望可穿戴装置或小形状因子产品的轮廓形状。侧面中的一些可具有附着的管芯110中的一个或多个,而其它侧面可以不具有附着的管芯110中的一个或多个。
在一些实施例中,管芯110可至少部分地由密封剂108封装。在一些实施例中,密封剂108可保护管芯110免受有害的环境因素诸如例如潮湿或氧化,和/或可促进到侧壁SW的粘附。在一些实施例中,密封剂108可以是柔性密封剂,其可在固化/接合密封剂108的热工艺之前在衬底102周围被包装。在一些实施例中,密封剂108可基本上与管芯110的不活动侧面齐平以允许散热器膜112与管芯110的不活动侧面进行热接触。在其它实施例中,密封剂108可完全封装管芯110。在一些实施例中,密封剂108可由聚硅氧烷、环氧树脂、丙烯酸酯(例如聚甲基丙烯酸甲酯)、聚氨基甲酸酯、苯并环丁烯(BCB)、聚酰亚胺、聚酰胺、高密度聚乙烯(HDPE)、双马来酰亚胺三嗪(BT)树脂、液晶聚合物(LCP)、芳族聚酰胺、聚二甲基硅氧烷(PDMS)或其适当的组合组成。在其它实施例中,密封剂108可由其它适当的材料组成。
在一些实施例中,散热器膜112可设置在密封剂108上,并可与管芯110的不活动侧面耦合,如可看到的。散热器膜112可由导热材料例如金属(例如铜)组成。在一些实施例中,散热器膜112可提供IC封装组件100的外表面。
根据各种实施例,器件层(未示出)可在衬底102上形成。例如,器件层可包括一个或多个有源器件,例如使用常规半导体制造技术例如CMOS制造技术形成的晶体管。在一些实施例中,器件层可设置例如在衬底102和第一介质层102a之间或在衬底102和第二介质层102b之间。在一些实施例中,衬底102可以是有源管芯的衬底。根据一些实施例,器件层的有源器件可与(多个)介质层102a、102b中的一个或两者的电气路由特征106、TSV104中的一个或多个,或与管芯110中的一个或多个电耦合。
在一些实施例中,IC封装组件100的长度L可小于或等于1厘米(cm)。在一些实施例中,长度L可小于0.5毫米(mm)。在其它实施例中,IC封装组件100可具有其它适当的尺寸。
IC封装组件100可提供可容易按照消费者需要和要求来集成功能器件(例如管芯110)的模块化小形状因子组件。在一些实施例中,IC封装组件100可包括用于提高的功率管理和在每个功能器件之间的I/O通信的垂直互连(例如TSV104)。IC封装组件100还可通过TSV104的热TSV和/或散热器膜112的方式来提供有效的热解决方案。
图2A-B示意性示出根据一些实施例的包括电源层或接地层的示例集成电路(IC)封装组件200的视图。IC封装组件200可与关于图1A-C的IC封装组件100描述的实施例一致。图2A示意性示出IC封装组件200的顶视图。图2B示意性示出IC封装组件200的透视图。散热器膜112和密封剂108的一部分被切掉且衬底102在图2A-B中是透明的以避免使基本特征模糊。
在一些实施例中,IC封装组件200可包括电源层或接地层214。电源层或接地层214可设置在衬底102上。例如,在一些实施例中,电源层或接地层214可与图1A-C的第一介质层102a耦合或设置在第一介质层102a上。
电源层或接地层214可配置成路由接地(例如Vss)信号或电力信号用于管芯110的操作。电源层或接地层214可增加噪声屏蔽并降低电磁干扰(EMI)或高速信号串扰耦合。电源层或接地层214可由与电源/接地TSV104a电耦合的导电材料组成。电源/接地TSV104a可与电源层或接地层214直接物理和电接触。虽然未示出,电源层或接地层214可与信号TSV104b且与将信号TSV104b耦合在一起或与管芯110耦合的电气路由特征106电绝缘,如可看到的。例如,介质材料例如氧化硅可设置在信号特征(例如信号TSV104b和对应的电气路由特征106)和电源层或接地层214之间。
IC封装组件200可包括在衬底102上的层202b,如可看到的。根据各种实施例,层202b可代表图1A-C的第二介质层102b。在其它实施例中,层202b可代表在衬底102上形成的器件层(例如具有有源器件,例如晶体管)。
在一些实施例中,IC封装组件200可包括设置在侧壁SW上以在管芯110之间路由电信号的电气路由特征206。关于图3A-C进一步描述电气路由特征206。
图3A-C示意性示出根据一些实施例的包括在侧壁SW上的电气路由特征206、206a、206b的示例集成电路(IC)封装组件300的视图。图3A示意性示出IC封装组件300的顶视图。图3B示意性示出IC封装组件300的透视图。图3C示意性示出IC封装组件300的侧视图。散热器膜112和密封剂108的一部分在图3A-C中被切掉以避免使基本特征模糊。密封剂108在图3B-C中被透明地描绘以避免使基本特征模糊。
IC封装组件300包括与衬底102的侧壁SW耦合的多个管芯110a、110b、110c、110d,如可看到的。管芯110a、110b、110c、110d可与关于图1A-C和2A-B的管芯110描述的实施例一致。
根据各种实施例,电气路由特征206可在侧壁SW上形成以在两个或更多管芯之间(例如在图3A-C中的所描绘的示例中的管芯110a和110b之间)路由电信号。电气路由特征206可在设置在侧壁SW的相同侧面上的管芯110a和110b之间路由电信号,如可看到的。在一些实施例中,可形成电气路由特征206a以在设置在侧壁的不同侧面上的管芯之间(例如在图3B-C中的所描绘的示例中的管芯110b和110c之间)路由电信号。电气路由特征206a可包在侧壁SW的侧面之间的拐角或其它边缘周围。在一些实施例中,可形成电气路由特征206b以在管芯110a、110b、110c、110d中的一个或多个和第一介质层102a或第二介质层102b的电气路由特征106之间(例如在图3C中的所描绘的示例中的管芯110b和第二介质层102b的电气路由特征106之间)路由电信号。在介质层102a、102b的边缘处的电气路由特征106可被称为“边缘焊盘”。
图4A-K示意性示出根据一些实施例的在制造的各种阶段期间的示例集成电路(IC)封装组件(例如在本文所述的IC封装组件100、200或300)的视图。参考图4A,描绘在使多个管芯110与载体440耦合之后的IC封装组件。在一些实施例中,载体440可具有金属表面,其上放置管芯110。管芯的有源侧面可面向下在载体440上。参考图4B,描绘在沉积密封剂108以至少部分地封装管芯之后的IC封装组件。在一些实施例中,可使用薄膜层压工艺来沉积密封剂108。密封剂108可由可在随后的操作期间包在衬底周围的柔性材料组成。参考图4C,描绘在从载体440移除密封剂108和管芯110之后的IC封装组件。可使用包括例如蚀刻或热工艺的任何适当的技术来分离载体440。管芯110的有源侧面在图4C中被描绘为面向上。
参考图4D,IC封装组件被描绘为示出用来提供用于形成电气路由特征(例如图3C的电气路由特征206、206a、206b)的材料的在管芯的有源侧面和密封剂108上的金属板406与用来提供散热器膜112的在管芯的不活动侧面上的另一金属板412的耦合。根据各种实施例,可使用金属箔层压和接合(例如热/压力)工艺来执行金属板406和/或金属板412的耦合。
参考图4E,IC封装组件被描绘为示出在金属板406上的光敏材料442的沉积。例如,光敏材料442可包括干膜抗蚀剂(DFR)或用于图案化的另一适当掩模材料。可使用任何适当的工艺(包括例如DFR层压、旋涂(spin-on)工艺等)来沉积光敏材料442。
参考图4F,IC封装组件被描绘为示出通过在掩模446中的开口由光444对光敏材料442的图案化曝光以便于光敏材料442的被曝光部分的移除。图案化的光敏材料442可限定区域,其中电气路由特征(例如图3C的电气路由特征206、206a、206b)和管芯焊盘210将在金属板406中形成。在一些实施例中,可使用光刻法和显影工艺来图案化光敏材料442。管芯焊盘210可便于在管芯110上的器件有源层和衬底102上的电气路由特征106之间的电连接。
参考图4G,描绘在执行蚀刻工艺以移除金属板406的部分来形成电气路由特征206a、206b(例如图3C的电气路由特征206、206a、206b)和在管芯110和/或密封剂108上的管芯焊盘210之后的IC封装组件。
参考图4H,描绘在沉积焊料掩模层448并形成开口449以允许电气路由特征206b和管芯焊盘210与衬底102上的对应电气路由特征106(例如焊盘或其它适当接触部)的耦合之后的IC封装组件。可通过层压工艺形成焊料掩模层448。可使用图案化工艺和/或显影工艺来形成开口449。在一些实施例中,焊料掩模层448可绝缘并保护电气路由特征206a、206b(例如图3C的电气路由特征206、206a、206b)和管芯焊盘210。
参考图4I,描绘在执行焊膏印刷或微隆起焊盘放置工艺以形成焊料隆起焊盘450之后的IC封装组件,焊料隆起焊盘450将形成在电气路由特征206b或管芯焊盘210和在衬底102上的对应电气路由特征106之间的电连接。在其它实施例中,除了焊料隆起焊盘450以外的其它适当的管芯互连结构可用于耦合电气路由特征206或管芯焊盘210和电气路由特征106。
参考图4J,描绘在提供具有第一介质层102a和/或第二介质层102b的衬底102之后的IC封装组件,电气路由特征106在其中形成。
参考图4K,描绘在使包括管芯110的组件与衬底102附着之后的IC封装组件。例如,管芯焊盘210和/或电气路由特征206a、206b可与在衬底102上的电气路由特征106对齐,且密封剂108和管芯110可使用薄膜卷绕/缠绕工艺被包或滚在衬底102周围。可应用接合和/或固化工艺以形成在电气路由特征206b或管芯焊盘210与电气路由特征106之间的焊点和/或固化密封剂108或焊料掩模层448。在一些实施例中,固化密封剂108可使密封剂在包装形状中变成刚性。
在其它实施例中,管芯110可包在衬底的比所描绘的更多或更少的侧面周围。例如在一些实施例中,具有管芯110的密封剂108可包在衬底102的整个周边周围。在一些实施例中,可从关于图4A-K描述的制造方法完全省略使用金属板406形成电气路由特征206a、206b和/或形成焊料掩模层448。可在其它实施例中使用制造IC封装组件的其它适当技术。
图5示意性示出根据一些实施例的制造IC封装组件(例如关于图1-4所述的IC封装组件)的方法500的流程图。方法500可与关于图1-4所述的实施例一致,并且反之亦然。
在502,方法500可包括提供具有第一侧面(例如图1B的第一侧面S1)和设置成与第一侧面相对的第二侧面(例如图1B的第二侧面S2)以及设置在第一侧面和第二侧面之间的侧壁(例如图1B的侧壁SW)的衬底(例如图1B或4J的衬底102),侧壁限定衬底的周边。侧壁可配置成接纳在侧壁的相应表面上的一个或多个管芯的附着。
在504,方法500可包括形成在衬底的第一侧面和第二侧面之间的多个穿过衬底的通孔(例如图1B的TSV104)。可使用任何适当的技术(包括例如用来形成穿过衬底的管道的机械或激光钻孔和用来使用金属填充管道的金属沉积工艺)来形成TSV。
在506,方法500可包括在第一侧面上形成第一介质层(例如图1B的第一介质层102a),第一介质层包括电气路由特征(例如图1B的电气路由特征106)以在第一介质层的平面中路由一个或多个管芯的电信号。可根据多种多样的适当的技术(包括例如在衬底上形成氧化物、图案化氧化物并沉积金属以填充在图案化的衬底中的开口)来形成第一介质层。可执行这样的技术以提供具有水平和/或垂直电气路由特征的介质层的堆叠。
在508,方法500可包括形成设置在第二侧面上的第二介质层(例如图1B的第二介质层102b),第二介质层包括电气路由特征以在第二介质层的平面中路由一个或多个管芯的电信号。可根据用于制造第一介质层的类似技术来形成第二介质层。
在510,方法500可包括耦合一个或多个管芯(例如图1B或图4J-K的管芯110)与侧壁的相应表面。可使用任何适当的技术来附着管芯以形成在管芯和衬底的电气路由特征之间的电连接。例如,电气路由特征可包括配置成接纳设置在管芯上的对应的管芯互连(例如隆起焊盘或支柱)的边缘焊盘。在一些实施例中,可执行焊料回流工艺以形成在管芯和电气路由特征之间的焊点。在其它实施例中,可使用用来耦合管芯与衬底的其它适当技术。
图6示意性示出根据一些实施例的用于制造IC封装组件(例如关于图1-4所述的IC封装组件)的另一方法600的流程图。方法600可与关于图1-5所述的实施例一致,并且反之亦然。
在602,方法600可包括在柔性密封剂中封装多个管芯(例如图4A-C的管芯110)。可例如根据关于图4A-C所述的技术来封装管芯。多个管芯的有源侧面可耦合到载体(例如图4A-B的载体440)。柔性密封剂可沉积在多个管芯上,且管芯可从载体解耦合。
在604,方法600可包括耦合散热器膜(例如图4E的散热器膜112)与多个管芯的不活动侧面。可例如根据关于图4D-E所述的技术使散热器膜与管芯耦合。在一些实施例中,在608,在将多个管芯耦合到侧壁的相应表面之前,可使散热器膜与多个管芯的不活动侧面耦合。
在606,方法600可包括在多个管芯上形成电气路由特征(例如图3C的电气路由特征206、206a、206b或图4G的电气路由特征206a、206b)。可例如根据关于图4D-4I所述的技术形成电气路由特征。金属箔可沉积在多个管芯的有源侧面上。金属箔可被图案化以形成焊盘或迹线。焊料掩模层(例如图4H的焊料掩模层448)可沉积在焊盘或迹线上。
在608,方法600可包括将多个管芯耦合到衬底(例如图4J-K的衬底102)的侧壁的相应表面,衬底具有第一侧面和与第一侧面相对的第二侧面,侧壁设置在第一侧面和第二侧面之间并限定衬底的周边,其中多个穿过衬底的通孔(TSV)设置在衬底的第一侧面和第二侧面之间。在一些实施例中,可例如根据关于图4J-K所述的技术将多个管芯耦合到侧壁。具有多个管芯的柔性密封剂可被包在衬底的侧壁周围。热工艺可应用于固化柔性密封剂。在一些实施例中,热工艺可以是形成在管芯和衬底上的电气路由特征之间的焊点的焊料回流工艺。
各种操作又以对理解所要求保护的主题最有帮助的方式被描述为多个分立的操作。然而,描述的次序不应被解释为暗示这些操作是必须次序相关的。
图7-8示意性示出根据一些实施例的可合并如本文所述的集成电路(IC)封装组件(例如IC封装组件100、200或300)的示例制造物品。制造物品可包括多种多样的适当的小形状因子和/或可穿戴装置。例如在一些实施例中,IC封装组件100可以是一个或多个纽扣700的部分。在一些实施例中,IC封装组件可被合并到眼镜框800、智能笔882或钱包884内,如所描绘的。
在一些实施例中,多个IC封装组件100可被堆叠在一起,使得相邻IC封装组件的电气路由特征使用任何适当的技术(例如用于倒装芯片安装的管芯的管芯互连结构)耦合在一起。堆叠的IC封装组件100可被合并到多种多样的物品(包括例如在图7-8中描绘的那些物品)中的任何一个内。例如在一些实施例中,IC封装组件100中的一个或多个可设置在眼镜框800、智能笔882或钱包884中的每一个中指示的虚线区中。本公开的实施例可使用任何适当的硬件和/或软件在系统内实现以如期望配置。图9示意性示出根据一些实施例的包括如本文所述的IC封装组件(例如图1-3的IC封装组件100、200或300或图4A-K的IC封装组件)的计算装置900。计算装置900可容纳板例如母板902(例如在壳体908中)。壳体908可以是多种多样的适当的物品中的任何一个,包括例如可穿戴装置或小形状因子装置的保护性材料。母板902可包括多个部件,包括但不限于处理器904和至少一个通信芯片906。处理器904可物理和电气地耦合到母板902。在一些实现中,至少一个通信芯片906也可物理和电气地耦合到母板902。在另外的实现中,通信芯片906可以是处理器904的部分。
根据它的应用,计算装置900可包括可以或可以不物理和电气地耦合到母板902的其它部件。这些其它部件可包括但不限于易失性存储器(例如动态随机存取存储器(DRAM))、非易失性存储器(例如只读存储器(ROM))、闪存、图形处理器、数字信号处理器、密码机处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)装置、罗盘、盖氏计数器、加速度计、陀螺仪、扬声器、摄像机和大容量存储装置(例如硬盘驱动器、光谱(CD)、数字通用盘(DVD)等)。
通信芯片906可使得能够实现数据到计算装置900和从计算装置900的传输的无线通信。术语“无线”及其衍生词可用于描述可通过使用穿过非固体媒介的经调制电磁辐射而传送数据的电路、装置、系统、方法、技术、通信通道等。该术语并不暗示相关联的装置不包含任何导线,虽然在一些实施例中它们可能不包含。通信芯片906可实现多种无线标准或协议中的任何一个,包括但不限于电气与电子工程师协会(IEEE)标准,包括Wi-Fi(IEEE802.11系列)、IEEE802.16标准(例如IEEE802.16-2005修订)、长期演进(LTE)计划连同任何修订、更新和/或修订版(例如高级LET计划、超移动宽带(UMB)计划(也被称为“3GPP2”)等)。IEEE802.16兼容宽带无线接入(BWM)网络通常被称为WiMAX网络,代表全球微波接入的互操作性的首字母缩略词,其是通过对IEEE802.16标准的符合性和互操作性测试的产品的证明标志。通信芯片906可根据全球移动通信系统(GSM)、通用分组无线服务(GPRS)、通用移动电信系统(UMTS)、高速分组接入(HSPA)、演进HSPA(E-HSPA)或LET网络来操作。通信芯片906可根据用于GSM演进的增强型数据(EDGE)、GSMEDGE无线接入网络(GERAN)、通用陆地无线接入网络(UTRAN)或演进UTRAN(E-UTRAN)来操作。通信芯片906可根据码分多址(CDMA)、时分多址(TDMA)、数字增强无绳电信(DECT)、演进数据优化(EV-DO)、其衍生物以及被指定为3G、4G、5G和更高的任何其它无线协议来操作。在其它实施例中,通信芯片906可根据其它无线协议来操作。
计算装置900可包括多个通信芯片906。例如,第一通信芯片906可专用于较短距离无线通信例如Wi-Fi和蓝牙,而第二通信芯片906可专用于较长距离无线通信例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算装置900的处理器904可以被封装在如本文所述的IC封装组件(例如图1-3的IC封装组件100、200、300或图4A-K的IC封装组件)中。例如,密封剂(例如图1-3的IC封装组件100、200、300或图4A-K的IC封装组件的密封剂108)可用作母板902,而处理器904可以是如本文所述的各管芯中的一个管芯(例如图1-3的IC封装组件100、200、300或图4A-K的IC封装组件的管芯110)。根据本文所述的实施例可实现其它适当的配置。术语“处理器”可以指的是处理例如来自寄存器和/或存储器的电子数据以将该电子数据转换成可被存储在寄存器和/或存储器中的其它电子数据的任何装置或装置的部分。
通信芯片906也可包括可被封装在如本文所述的IC封装组件(例如图1-3的IC封装组件100、200、300或图4A-K的IC封装组件)中的管芯。在另外的实现中,容纳在计算装置900内的另一部件(例如存储器装置或其它集成电路装置)可包括可被封装在如本文所述的IC封装组件(例如图1-3的IC封装组件100、200、300或图4A-K的IC封装组件)中的管芯。
在各种实现中,计算装置900可以是膝上型计算机、上网本计算机、笔记本计算机、超级笔记本计算机、智能电话、平板计算机、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在一些实施例中,计算装置900可以是移动计算装置。在另外的实现中,计算装置900可以是处理数据的任何其它电子装置。
示例
根据各种实施例,本公开描述了一种设备。该设备的示例1可包括:衬底,其具有第一侧面和设置成与第一侧面相对的第二侧面以及设置在第一侧面和第二侧面之间的侧壁,侧壁限定衬底的周边;多个穿过衬底的通孔(TSV),其设置在衬底的第一侧面和第二侧面之间;第一介质层,其设置在第一侧面上并包括电气路由特征以在第一介质层的平面中路由一个或多个管芯的电信号;以及第二介质层,其设置在第二侧面上并包括电气路由特征以在第二介质层的平面中路由一个或多个管芯的电信号,其中侧壁配置成接纳在侧壁的相应表面上的一个或多个管芯的附着。
示例2可包括示例1的设备,其中多个TSV中的一个或多个TSV配置成在一个或多个管芯中的第一管芯和第二管芯之间路由电信号。示例3可包括示例1的设备,其中多个TSV中的一个或多个TSV是配置成将热量从衬底路由掉的热TSV。示例4可包括示例1的设备,还包括设置在侧壁上并配置成在一个或多个管芯中的第一管芯和第二管芯之间路由电信号的电气路由特征。示例5可包括示例1-4中的任何一个的设备,还包括附着到侧壁的一个或多个管芯中的第一管芯和附着到侧壁的一个或多个管芯中的第二管芯,其中第一管芯和第二管芯电耦合在一起。示例6可包括示例5的设备,其中侧壁具有三个或更多侧面,且第一管芯与三个或更多侧面中的第一侧面耦合,且第二管芯与三个或更多侧面中的第二侧面耦合。示例7可包括示例5的设备,其中第一管芯通过第一介质层和/或第二介质层的电气路由特征与第二管芯电耦合。示例8可包括示例5的设备,其中第一管芯通过设置在侧壁上的电气路由特征与第二管芯电耦合。示例9可包括示例5的设备,还包括至少部分地封装第一管芯和第二管芯的密封剂。示例10可包括示例9的设备,还包括设置在第一管芯、第二管芯和密封剂上的散热器膜。示例11可包括示例1-4中的任何一个的设备,还包括与第二介质层耦合的电源层或接地层。示例12可包括示例1-4中的任何一个的设备,还包括设置在衬底和第一介质层之间的衬底的第一侧面上的器件层,器件层包括一个或多个有源器件。示例13可包括示例1-4中的任何一个的设备,其中衬底包括半导体材料或玻璃。根据各种实施例,本公开描述组件。组件的示例14可包括可穿戴物品、智能笔或钱包,其中可穿戴物品或智能笔或钱包包括示例1-13中的任何一个的设备。示例15可包括示例14的组件,其中可穿戴物品包括纽扣或眼镜框。
根据各种实施例,本公开描述一种方法。方法的示例16可包括提供衬底,其具有第一侧面和设置成与第一侧面相对的第二侧面以及设置在第一侧面和第二侧面之间的侧壁,侧壁限定衬底的周边;在衬底的第一侧面和第二侧面之间形成多个穿过衬底的通孔(TSV);形成第一介质层,其在第一侧面上并包括电气路由特征以在第一介质层的平面中路由一个或多个管芯的电信号;以及形成第二介质层,其设置在第二侧面上并包括电气路由特征以在第二介质层的平面中路由一个或多个管芯的电信号,其中侧壁配置成接纳在侧壁的相应表面上的一个或多个管芯的附着。示例17可包括示例16的方法,还包括将一个或多个管芯中的第一管芯附着到侧壁以及将一个或多个管芯中的第二管芯附着到侧壁,其中第一管芯和第二管芯与第一介质层和/或第二介质层的电气路由特征电耦合。
根据各种实施例,本公开描述另一方法。方法的示例18可包括在柔性密封剂中封装多个管芯,在多个管芯上形成电气路由特征,以及将多个管芯耦合到衬底的侧壁的相应表面,衬底具有第一侧面和设置成与第一侧面相对的第二侧面,侧壁设置在第一侧面和第二侧面之间并限定衬底的周边,其中多个穿过衬底的通孔(TSV)设置在衬底的第一侧面和第二侧面之间。示例19可包括示例18的方法,其中在柔性密封剂中封装多个管芯包括将多个管芯的有源侧面耦合到载体,在多个管芯上沉积柔性密封剂,以及使多个管芯从载体解耦合。示例20可包括示例18的方法,其中形成电气路由特征包括在多个管芯的有源侧面上沉积金属箔,图案化金属箔以形成焊盘或迹线,以及在焊盘或迹线上沉积焊料掩模层。示例21可包括示例18-20中的任何一个的方法,其中将多个管芯耦合到衬底的侧壁的相应表面包括将具有多个管芯的柔性密封剂包在衬底的侧壁周围以及应用热工艺以固化柔性密封剂。示例22可包括示例18-20中的任何一个的方法,还包括在将多个管芯耦合到侧壁的相应表面之前耦合散热器膜与多个管芯的不活动侧面。
各种实施例可包括上述实施例的任何适当组合,其包括在上面的连接形式(和)(例如“和”可以是“和/或”)中描述的实施例的替换(或)实施例。此外,一些实施例可包括一个或多个制造物品(例如非瞬态计算机可读介质),其具有在其上存储的指令,指令当被执行时导致上述实施例中的任何一个的行动。而且,一些实施例可包括具有用于执行上述实施例的各种操作的任何适当装置的设备或系统。
所图示的实现的上面的描述(包括在摘要中描述的内容)并不意在为穷尽的或将本公开的实施例限制到所公开的精确形式。虽然为了例证性目的在本文描述了特定的实现和示例,各种等效修改在本公开的范围内是可能的,如相关领域中的技术人员将认识到的。
可按照上面详述的描述对本公开的实施例进行这些修改。在下面的权利要求中使用的术语不应被解释为将本公开的各种实施例限制到在说明书和权利要求中公开的特定实现。相反,范围应完全由应根据权利要求解释的建立的教导而解释的下面的权利要求确定。
Claims (22)
1.一种设备,包括:
衬底,其具有第一侧面和设置成与所述第一侧面相对的第二侧面以及设置在所述第一侧面和所述第二侧面之间的侧壁,所述侧壁限定所述衬底的周边;
多个穿过衬底的通孔(TSV),其设置在所述衬底的所述第一侧面和所述第二侧面之间;
第一介质层,其设置在所述第一侧面上并包括电气路由特征以在所述第一介质层的平面中路由一个或多个管芯的电信号;以及
第二介质层,其设置在所述第二侧面上并包括电气路由特征以在所述第二介质层的平面中路由所述一个或多个管芯的电信号,其中所述侧壁配置成接纳在所述侧壁的相应表面上的所述一个或多个管芯的附着。
2.如权利要求1所述的设备,其中所述多个TSV中的一个或多个TSV配置成在所述一个或多个管芯中的第一管芯和第二管芯之间路由电信号。
3.如权利要求1所述的设备,其中所述多个TSV中的一个或多个TSV是配置成将热量从所述衬底路由掉的热TSV。
4.如权利要求1所述的设备,还包括:
设置在所述侧壁上并配置成在所述一个或多个管芯中的第一管芯和第二管芯之间路由电信号的电气路由特征。
5.如权利要求1-4中的任一项所述的设备,还包括:
附着到所述侧壁的所述一个或多个管芯中的第一管芯;以及
附着到所述侧壁的所述一个或多个管芯中的第二管芯,其中所述第一管芯和所述第二管芯电耦合在一起。
6.如权利要求5所述的设备,其中:
所述侧壁具有三个或更多的侧面;以及
所述第一管芯与所述三个或更多的侧面中的第一侧面耦合;以及
所述第二管芯与所述三个或更多的侧面中的第二侧面耦合。
7.如权利要求5所述的设备,其中:
所述第一管芯通过所述第一介质层和/或所述第二介质层的电气路由特征与所述第二管芯电耦合。
8.如权利要求5所述的设备,其中:
所述第一管芯通过设置在所述侧壁上的电气路由特征与所述第二管芯电耦合。
9.如权利要求5所述的设备,还包括:
至少部分地封装所述第一管芯和所述第二管芯的密封剂。
10.如权利要求9所述的设备,还包括:
设置在所述第一管芯、所述第二管芯和所述密封剂上的散热器膜。
11.如权利要求1-4中的任一项所述的设备,还包括:
与所述第二介质层耦合的电源层或接地层。
12.如权利要求1-4中的任一项所述的设备,还包括:
设置在所述衬底和所述第一介质层之间的所述衬底的所述第一侧面上的器件层,所述器件层包括一个或多个有源器件。
13.如权利要求1-4中的任一项所述的设备,其中所述衬底包括半导体材料或玻璃。
14.一种组件,包括:
可穿戴物品、智能笔或钱包,其中所述可穿戴物品或所述智能笔或所述钱包包括权利要求1-13中的任一项的设备。
15.如权利要求14所述的组件,其中所述可穿戴物品包括纽扣或眼镜框。
16.一种方法,包括:
提供衬底,所述衬底具有第一侧面和设置成与所述第一侧面相对的第二侧面以及设置在所述第一侧面和所述第二侧面之间的侧壁,所述侧壁限定所述衬底的周边;
在所述衬底的所述第一侧面和所述第二侧面之间形成多个穿过衬底的通孔(TSV);
形成第一介质层,所述第一介质层在所述第一侧面上并包括电气路由特征以在所述第一介质层的平面中路由一个或多个管芯的电信号;以及
形成第二介质层,其设置在所述第二侧面上并包括电气路由特征以在所述第二介质层的平面中路由所述一个或多个管芯的电信号,其中所述侧壁配置成接纳在所述侧壁的相应表面上的所述一个或多个管芯的附着。
17.如权利要求16所述的方法,还包括:
将所述一个或多个管芯中的第一管芯附着到所述侧壁;以及
将所述一个或多个管芯中的第二管芯附着到所述侧壁,其中所述第一管芯和所述第二管芯与所述第一介质层和/或所述第二介质层的所述电气路由特征电耦合。
18.一种方法,包括:
在柔性密封剂中封装多个管芯;
在所述多个管芯上形成电气路由特征;以及
将所述多个管芯耦合到所述衬底的侧壁的相应表面,所述衬底具有第一侧面和设置成与所述第一侧面相对的第二侧面,所述侧壁设置在所述第一侧面和所述第二侧面之间并限定所述衬底的周边,其中多个穿过衬底的通孔(TSV)设置在所述衬底的所述第一侧面和所述第二侧面之间。
19.如权利要求18所述的方法,其中在所述柔性密封剂中封装所述多个管芯包括:
将所述多个管芯的有源侧面耦合到载体;
在所述多个管芯上沉积所述柔性密封剂;以及
使所述多个管芯从所述载体解耦合。
20.如权利要求18所述的方法,其中形成所述电气路由特征包括:
在所述多个管芯的有源侧面上沉积金属箔;
图案化所述金属箔以形成焊盘或迹线;以及
在所述焊盘或迹线上沉积焊料掩模层。
21.如权利要求18-20中的任一项的方法,其中将所述多个管芯耦合到所述衬底的所述侧壁的相应表面包括:
将具有所述多个管芯的所述柔性密封剂包在所述衬底的所述侧壁周围;以及
应用热工艺以固化所述柔性密封剂。
22.如权利要求18-20中的任一项的方法,还包括:
在将所述多个管芯耦合到所述侧壁的相应表面之前耦合散热器膜与所述多个管芯的不活动侧面。
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