CN101789419A - 立方半导体封装 - Google Patents

立方半导体封装 Download PDF

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Publication number
CN101789419A
CN101789419A CN200910174948A CN200910174948A CN101789419A CN 101789419 A CN101789419 A CN 101789419A CN 200910174948 A CN200910174948 A CN 200910174948A CN 200910174948 A CN200910174948 A CN 200910174948A CN 101789419 A CN101789419 A CN 101789419A
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Prior art keywords
semiconductor chip
chip module
semiconductor
cube
encapsulation
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CN101789419B (zh
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徐敏硕
李升铉
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明提供了一种立方半导体封装。立方半导体封装包括一个或多个堆叠一起且互相连接的半导体芯片模块。立方半导体封装包括半导体芯片模块和连接构件。半导体芯片模块包括具有第一、第二表面、侧表面、焊垫的半导体芯片、穿通电极、以及重配置线。第二表面与第一表面相反并隔开。侧表面连接第一和第二表面。焊垫设置在第一表面上。穿通电极穿过第一和第二表面。重配置线设置在第一和第二表面的至少一个上，电连接到穿通电极和焊垫，并且具有与侧表面齐平的端部。连接构件设置在侧表面上，并且与重配置线的端部电连接。

Description

立方半导体封装
技术领域
本发明涉及一种立方半导体封装，其包括以立方形式连接的多个半导体封装，以增加数据存储容量并提高数据处理速度。
背景技术
半导体芯片能够存储大量数据并且能够迅速处理数据。半导体封装已经被广泛地应用于各种信息处理单元(诸如计算机)中并用于存储和处理数据。
近年来，人们致力于提供具有安装在印刷电路板上并堆叠在一起的至少两个半导体封装的堆叠半导体封装，以增加数据存储容量并提高数据处理速度。
然而，在该具有大量彼此堆叠的半导体封装的堆叠半导体封装中，堆叠半导体封装的厚度显著增加。由于堆叠半导体封装的厚度增加，信号传输路径的长度改变，使得难以以相对较高速度进行处理数据。
发明内容
本发明的实施例包括立方半导体封装，在该立方半导体封装中，半导体封装以立方形式的构造或类似块组装的形式而相互电连接，从而能够增加数据存储容量并提高数据处理速度。
在本发明的一个方面中，立方半导体封装包括半导体芯片模块和连接构件。该半导体芯片模块包括：半导体芯片，具有第一表面、与第一表面相反且隔开的第二表面、连接第一和第二表面的侧表面、以及置于第一表面上的焊垫；穿通电极，穿过第一和第二表面；以及重配置线，置于第一和第二表面的至少一个上，与穿通电极和焊垫电连接，并且具有与侧表面齐平的端部。连接构件置于侧表面上并与重配置线的端部电连接。
重配置线具有从第一表面延伸至侧表面的延伸部。
连接构件包括导电球。
立方半导体封装可以还包括粘结构件，覆盖重配置线并且具有露出该穿通电极的开口。
至少两个半导体芯片模块沿第一方向堆叠并且通过穿通电极相互电连接。
导电球连接到半导体芯片模块中的上部的半导体芯片模块和下部的半导体芯片模块的至少之一的穿通电极的端部。
半导体芯片模块可以具有相同的尺寸和形状。
半导体芯片模块可以包括具有第一尺寸的第一半导体芯片模块和具有比第一尺寸小的第二尺寸的第二半导体芯片模块，第一和第二半导体芯片模块的侧表面相互齐平。
立方半导体封装还包括附加的半导体芯片模块，该附加的半导体芯片模块具有：半导体芯片，沿与第一方向垂直的第二方向设置在半导体芯片模块的至少一个侧表面上并具有焊垫；以及穿通电极，该穿通电极穿过沿第二方向设置的半导体芯片并且与焊垫和连接构件电连接。
堆叠至少两个附加的半导体芯片模块，该附加的半导体芯片模块的穿通电极相互电连接。
附加的半导体芯片模块包括用于存储数据的数据存储半导体芯片和用于处理数据的数据处理半导体芯片。
至少两个附加的半导体芯片模块被设置，并可以具有相同尺寸和形状。
至少两个附加的半导体芯片模块被设置，并可以具有不同尺寸。
连接构件连接到附加的半导体芯片模块的穿通电极的暴露到外部的端部。
立方半导体封装还可以包括插设在半导体芯片模块和附加的半导体芯片模块之间的隙填充构件。
重配置线可以由导电材料形成，优选为具有第一硬度和第一熔化温度的第一金属。置于半导体芯片的侧表面上的连接构件可以由导电材料形成，优选为具有比第一硬度低的第二硬度和比第一熔化温度低的第二熔化温度的第二金属。
第一金属可以优选包括铜，第二金属优选包括焊料。
附图说明
图1是示出根据本发明第一实施例的立方半导体封装的平面图。
图2是沿着图1的I-I’线截取的剖面图。
图3是示出根据本发明第二实施例的立方半导体封装的平面图。
图4是沿着图3的II-II’线截取的剖面图。
图5是示出根据本发明第三实施例的立方半导体封装的剖面图。
图6是示出根据本发明第四实施例的立方半导体封装的平面图。
具体实施方式
图1是示出根据本发明第一实施例的立方半导体封装的平面图。图2是沿着图1的I-I’线截取的剖面图。
参照图1和图2，根据本发明实施例的立方半导体封装300示出为包括半导体芯片模块100和连接构件200。立方半导体封装300可以还包括粘结构件350。
图1所示的半导体芯片模块100包括半导体芯片10、穿通电极20以及重配置线(redistribution line)30。
在图1-2中，半导体芯片10示出为具有长方六面体形状，但是本领域技术人员应当理解，半导体芯片可以具有任何已知的几何形状。如图2所示，示出为具有长方六面体形状的半导体芯片10包括第一表面1、第二表面3、侧表面5、及焊垫7。此外，该半导体芯片10还可以包括绝缘层9。在半导体芯片10中形成电路区(circuit section)(未示出)。电路区可以包括任何已知的电路区，例如用于存储数据的数据存储单元(未示出)和/或用于处理数据的数据处理单元(未示出)。
半导体芯片10的第一表面1和第二表面3示出为彼此相反且隔开。半导体芯片10的侧表面5示出为与第一表面1和第二表面3相接或邻接。焊垫7示出为设置在第一表面1上。焊垫7示出为布置在沿第一表面1的中央部分的两个基本线性的行上，但是本领域技术人员应当理解，焊垫7还可以以其他的构造来布置。各焊垫7与形成在半导体芯片10中的电路区(未示出)电连接。
绝缘层9示出为设置在半导体芯片10的第一表面1的一部分上，从而焊垫7经由绝缘层9并通过重配置线30暴露于而外部。
重配置线30设置于绝缘层9上。重配置线30可以由任何具有第一硬度和第一熔化温度的导电材料(例如铜或铜合金)构成。重配置线30示出为以线条形式形成在绝缘层9上，但是应当理解这只是示例，重配置线30还可以以许多其他的形状或构造来设置。各重配置线30的第一端电连接至各自的焊垫7，各重配置线30的第二端(与第一端相反)示出为与半导体芯片10的侧表面5平齐地终止。
在此实施例中，重配置线30可以以任何已知的导电材料构成，只要重配置线30的端部可以形成为与半导体芯片10的侧表面5齐平。例如，重配置线30可以由铜、镍或金形成。包括镍和金的至少一种的重配置线30使连接构件200和重配置线30之间的粘着力显著增大，从而阻碍(inhibit)或者防止(prevent)连接构件200从重配置线30松开。
根据本发明的实施例，各重配置线30的第二端可以延伸至半导体芯片10的多个侧表面5的至少一个。举例而言，当半导体芯片10具有四个侧表面5时，重配置线30的第二端可以与半导体芯片10的至少一个侧表面5齐平或最多与半导体芯片10的全部四个侧表面5齐平。
如图2所示，粘结构件350设置于绝缘层9上方。粘结构件350覆盖设置于绝缘层9上的重配置线30并且使其电绝缘。粘结构件350可包括粘着物质或双面胶带。
如图2所示，穿通电极20穿过粘结构件350、重配置线30、绝缘层9、及半导体芯片10的第一表面1和第二表面3。根据本发明的实施例，穿通电极20可以为柱状，并且可以由导电材料(例如铜和其他金属)形成。在此实施例中，穿通电极20构造为穿过重配置线30并与其电耦接。
只要连接构件与它们各自的重配置线30电耦接，连接构件200可以设置于半导体芯片模块100上的任何地方。优选地，连接构件20设置于半导体芯片10的侧表面5上。优选地，连接构件200与重配置线30的第二端电耦接，该第二端与半导体芯片10的侧表面5齐平。如图2所示，连接构件200可为球形连接构件，但是其他形状也是可以的。在此实施例中，连接构件200可以包括例如焊球，该焊球包含具有比第一硬度小的第二硬度和比第一熔化温度低的第二熔化温度的焊料。
图3示出根据本发明的第二实施例的立方半导体封装的平面图。图4是沿图3的II-II’线的剖面图。除了重配置线以外，根据图3和4所示的实施例的立方半导体封装300基本上与参照图1和2描述的立方半导体封装300相同。因此，相同的元件以相同的附图标记表示，并将其详细描述省略。
现在参照图3和4，为了增加连接构件200和重配置线30之间的接触面积，重配置线30可以配置为具有选用的延伸部35。如上所述，重配置线30的第一端与焊垫7电耦接。延伸部35从第一表面1延伸至半导体芯片10的侧表面5。也就是说，由于延伸部35的存在，重配置线30具有L形截面，如图4所示。
镍层和/或金层(未示出)可以形成在重配置线30的延伸部35的表面上，球形的连接构件200可以设置在延伸部35上。该连接构件200可以含有焊料。如上所述，球形的连接构件200仅为示例，本发明并不局限于此。
在此实施例中，由于重配置线30的延伸部35形成在半导体芯片10的侧表面5上，可以增大连接构件200和重配置线30之间的接触面积，因此可以防止或至少阻碍连接构件200从重配置线30松开。
图5示出根据本发明第三实施例的立方半导体封装的剖面图。在此实施例中，立方半导体封装300的每个半导体芯片模块100a、100b、100c包括与图1和2所示的半导体芯片模块100基本相同的组件部分。因此，将省略基本相同的组件部分的重复解释，并且使用相同的术语和附图标记来表示相同的组件部分。
参照图5，立方半导体封装300包括多个半导体芯片模块100a、100b、100c以及多个连接构件200、210、220。
在此实施例中，立方半导体封装300示出为包括三个半导体模块100a、100b、100c，但是本领域技术人员应当理解，根据本发明实施例的立方半导体封装300可以包括许多的半导体芯片模块。这里，将三个半导体芯片模块称作第一半导体芯片模块100a、第二半导体芯片模块200b以及第三半导体芯片模块100c。
如图5所示，第二半导体芯片模块100b设置于第一半导体芯片模块100a上，第三半导体芯片模块100c设置于第二半导体芯片模块100b上。
第一至第三半导体芯片模块100a、100b、100c的每个包括半导体芯片10、穿通电极20以及重配置线30。
第一至第三半导体芯片模块100a、100b、100c的每个的半导体芯片10具有长方六面体形状，但是应当理解本发明并不局限于此，半导体芯片10可具有许多形状。半导体芯片10包括第一表面1、第二表面3、侧表面5、及焊垫7。此外，半导体芯片10还可以包括绝缘层9。在半导体芯片10中形成电路区(未示出)。电路区可以包括用于存储数据的数据存储单元(未示出)和用于处理数据的数据处理单元(未示出)。
半导体芯片10的第一表面1和第二表面3基本上彼此相反并隔开，半导体芯片10的侧表面5邻接第一表面1和第二表面3。焊垫7布置在半导体芯片10的第一表面1上。如图5所示，焊垫7可以布置在沿第一表面1的中央部分的两行上，但是根据本发明还可以考虑其它的构造。各焊垫7与形成在半导体芯片10中的电路区电耦接。
在此实施例中，第一至第三半导体芯片模块100a、100b、100c的半导体芯片10可以包括执行相同功能的相同类型半导体芯片，或者，第一至第三半导体芯片模块100a、100b、100c的半导体芯片10可以包括执行不同功能的不同类型半导体芯片。
在此实施例中，第一至第三半导体芯片模块100a、100b、100c的半导体芯片10可以具有相同尺寸，或者，第一至第三半导体芯片模块100a、100b、100c的半导体芯片10可以具有不同尺寸。
如图5所示，绝缘层9可以设置在半导体芯片10的第一表面1的一部分上，使得焊垫7经由绝缘层9暴露于外部。
重配置线30示出为置于绝缘层9上。重配置线30包括导电材料，优选为铜或铜合金。如图5所示，重配置线30可以以线条形式形成在绝缘层9上，但是应当理解线条形状仅是示例，根据本发明实施例还可以考虑重配置线30的其他形状和构造。重配置线30的第一端与各焊垫7电连接，重配置线30的第二端(与第一端相反)形成为与半导体芯片10的侧表面5齐平地终止。
在此实施例中，重配置线30可以由例如任何导电材料形成，优选为铜或铜合金。此外，镍层和/或金层(未示出)可以形成在重配置线30的与半导体芯片10的侧表面5齐平的第二端。镍层和/或金层可以显著地增大连接构件200和重配置线30之间的粘着力，从而防止连接构件200从重配置线30松开。
在此实施例中，各重配置线30的第二端延伸至半导体芯片10的多个侧表面5的至少一个，然而，重配置线可以延伸至存在于半导体芯片上的所有侧表面。举例而言，当半导体芯片10有四个侧表面5，重配置线30的第二端可以仅与半导体芯片10的一个侧表面齐平或者最多与半导体芯片10的四个侧表面5齐平。
在此实施例中，重配置线30还可以包括从第一表面1延伸至侧表面5的延伸部，如图4所示。延伸部增大了重配置线30和连接构件200之间的接触面积，将在后面详细描述。
如图5所示，粘结构件350设置在绝缘层9上方。粘结构件350覆盖置于绝缘层9上的重配置线30并且使其绝缘。粘结构件350可以包括例如含有粘着物质或双面胶带的粘着层。
粘结构件350示出为分别插设在第一半导体芯片模块100a和第二半导体芯片模块100b之间以及第二半导体芯片模块100b和第三半导体芯片模块100c之间。另一个粘结构件350设置在第三半导体芯片模块100c的半导体芯片10的第一表面1上。粘结构件350用于将第一至第三半导体芯片模块100a、100b、100c物理固定。
穿通电极20穿过第一至第三半导体芯片模块100a、100b、100c。在此实施例中，穿通电极20与第一至第三半导体芯片模块100a、100b、100c的各重配置线30电耦接。在此实施例中，穿通电极20的长度与第一至第三半导体芯片模块100a、100b、100c的总厚度一致。
用于穿通电极的连接构件210、220可以与穿通电极20的两端电耦接，附加的半导体封装(未示出)通过用于穿通电极的连接构件210、220而电连接到立方半导体封装300。
连接构件200示出为形成在第一至第三半导体芯片模块100a、100b、100c的侧表面5上。连接构件200与重配置线30的第二端电耦接，该第二端与第一至第三半导体芯片模块100a、100b、100c的侧表面5齐平。在此实施例中，连接构件200可以为球形的连接构件。在此实施例中，连接构件200可以包括例如含有焊料的焊球，但是应当理解，根据本发明连接构件200可以由其他的材料以其他的形状形成。
图6是根据本发明第四实施例的立方半导体封装的平面图。
参照图6，立方半导体封装300示出为包括多个水平半导体芯片模块100a、100b、100c、多个垂直半导体芯片模块100d、100e、100f、以及多个连接构件200、210、220。
此实施例示出具有三个水平半导体芯片模块100a、100b、100c及三个垂直半导体芯片模块100d、100e、100f的立方半导体封装300，但是应当理解这仅为示例，本发明并不局限于此。三个水平半导体芯片模块称为第一水平半导体芯片模块100a、第二水平半导体芯片模块100b、以及第三水平半导体芯片模块100c。此外，三个垂直半导体芯片模块称为第一垂直半导体芯片模块100d、第二垂直半导体芯片模块100e、及第三垂直半导体芯片模块100f。
第二水平半导体芯片模块100b示出为置于第一水平半导体芯片模块100a上，第三水平半导体芯片模块100c示出为置于第二水平半导体芯片模块100b上。
第一至第三水平半导体芯片模块100a、100b、100c的每个包括半导体芯片10、穿通电极20、及重配置线30。
第一至第三水平半导体芯片模块100a、100b、100c的各半导体芯片10可以具有任何的几何形状，例如并优选为长方六面体。半导体芯片10包括第一表面1、第二表面3、侧表面5、以及焊垫7。此外，半导体芯片10还可以包括绝缘层9。在第一至第三水平半导体芯片模块100a、100b、100c的各半导体芯片10中形成电路区(未示出)。电路区可以设置许多电路功能，例如包括用于存储数据的数据存储单元(未示出)和用于处理数据的数据处理单元(未示出)。
半导体芯片10的第一表面1和第二表面3彼此相反地面对，半导体芯片10的侧表面5与第一表面1和第二表面3邻接。焊垫7置于第一表面1上。焊垫7可以布置在沿第一表面1的中央部分的两行上。各焊垫7与形成在半导体芯片10中的电路区(未示出)电耦接。
在此实施例中，第一至第三水平半导体芯片模块100a、100b、100c的半导体芯片10可以包括执行相同功能的相同类型的半导体芯片，或者第一至第三水平半导体芯片模块100a、100b、100c的半导体芯片10可以包括许多执行不同功能的不同类型的半导体芯片。
在此实施例中，第一至第三水平半导体芯片模块100a、100b、100c的半导体芯片10可以具有相同尺寸和形状，或者第一至第三水平半导体芯片模块100a、100b、100c的半导体芯片10可以具有一个或更多的不同尺寸和形状。
绝缘层9设置在半导体芯片10的第一表面1的一部分上，使得焊垫7经由绝缘层9而暴露于外部。
重配置线30置于绝缘层9上，并且可以由任何的导电材料制成，例如并优选为铜或铜合金。重配置线30以线条的形式形成在绝缘层9上，但是应当理解，根据本发明的实施例重配置线其他构造也是可以的。重配置线30的第一端与各焊垫7电耦接，重配置线30的第二端(与第一端相反)与半导体芯片10的侧表面5基本齐平。
在此实施例中，重配置线30可以由例如铜制成，镍层和/或金层(未示出)可以形成在重配置线30的与半导体芯片10的侧表面5齐平的第二端上。注意到镍层和/或金层(未示出)可以明显增大连接构件200和重配置线30之间的粘着力，从而可以防止或者至少阻碍连接构件200从重配置线30松开。
在此实施例中，重配置线30的第二端可以延伸至半导体芯片10的多个侧表面5的至少一个，或者重配置线30可以延伸至全部的侧表面5。举例而言，当半导体芯片10具有四个侧表面5，重配置线30的第二端可以至少与半导体芯片10的一个侧表面5齐平或者至多与半导体芯片10的四个侧表面5齐平。
在此实施例中，重配置线30可以具有从第一表面1延伸至侧表面5的延伸部。延伸部增大了重配置线30和连接构件200之间的接触面积，将在后面详细描述。
粘结构件350设置于绝缘层9上方。粘结构件350覆盖置于绝缘层9上的重配置线30并且使其绝缘。粘结构件350可以包括例如粘着物质或双面胶带。
粘结构件350分别插设在第一水平半导体芯片模块100a和第二水平半导体芯片模块100b之间以及第二水平半导体芯片模块100b和第三水平半导体芯片模块100c之间。另一个粘结构件350置于第三水平半导体芯片模块100c的半导体芯片10的第一表面1上。粘结构件350用于将第一至第三水平半导体芯片模块100a、100b、100c物理固定。
穿通电极20穿过第一至第三水平半导体芯片模块100a、100b、100c。在此实施例中，穿通电极20与第一至第三水平半导体芯片模块100a、100b、100c的各重配置线30电耦接。在此实施例中，穿通电极20的长度与第一至第三水平半导体芯片模块100a、100b、100c的总厚度一致。
用于穿通电极的连接构件210、220可以与穿通电极20的两端电连接，附加的半导体封装(未示出)可以通过用于穿通电极的连接构件210、220而与立方半导体封装300电连接。
连接构件200置于第一至第三水平半导体芯片模块100a、100b、100c的侧表面5上。连接构件200与重配置线30的第二端电耦接，该第二端与第一至第三水平半导体芯片模块100a、100b、100c的侧表面5齐平。在此实施例中，连接构件200可以为球形，然而本发明并不局限于此，其他形状也被认为是在本发明的范围内。在此实施例中，连接构件200可以包括例如含有焊料的焊球。
同时，第一至第三垂直半导体芯片模块100d、100e、100f可以设置于第一至第三水平半导体芯片模块100a、100b、100c的侧表面5的连接构件200上。
根据图6所示的本发明的实施例，第一至第三垂直半导体芯片模块100d、100e、100f的每个包括具有焊垫(未示出)的半导体芯片12和穿通电极22。在此实施例中，诸如焊球的连接构件22a可以设置于第一至第三垂直半导体芯片模块100d、100e、100f的穿通电极22中暴露于外部的这些穿通电极22上。附加的半导体封装可以连接至连接构件22a。
在此实施例中，第一和第二垂直半导体芯片模块100d、100e与置于第一至第三水平半导体芯片模块100a、100b、100c的侧表面5上的连接构件200连接。
在此实施例中，第一和第二垂直半导体芯片模块100d、100e的穿通电极22与置于第一至第三水平半导体芯片模块100a、100b、100c的侧表面5上的连接构件200电耦接。在此实施例中，第一和第二垂直半导体芯片模块100d、100e示出为具有相同形状和尺寸，但是应当理解，第一和第二垂直半导体芯片模块100d、100e也可以包括具有不同形状和尺寸的半导体芯片。
第三垂直半导体芯片模块100f置于第二垂直半导体芯片模块100e上。第三垂直半导体芯片模块100f和第二垂直半导体芯片模块100e的穿通电极22通过连接构件200(例如焊球等)相互电耦接。
在此实施例中，间隙填充构件370可以置于限定在第一至第三水平半导体芯片模块100a、100b、100c的侧表面5与第一和第二垂直半导体芯片模块100d、100e之间的间隔中。另一个间隙填充构件370可以置于限定在第二垂直半导体芯片模块100e与第三垂直半导体芯片模块100f之间的间隔中。
在此实施例中，第一和第二垂直半导体芯片模块100d、100e可以包括例如用于存储数据的数据存储半导体芯片，第三垂直半导体芯片模块100f可以包括用于处理数据的数据处理半导体芯片，但是这仅为示例，本发明并不局限于此。
由上述描述可以知道，在本发明，多个半导体芯片沿第一方向(垂直方向)堆叠，从而形成水平半导体芯片模块，多个半导体芯片沿第二方向(水平方向)堆叠在堆叠的水平半导体芯片模块的侧表面，从而可以以立方形式制造半导体封装。因此，在本发明中，可以增加数据存储容量并提高数据处理速度。
虽然出于示例的目的描述了本发明的具体实施例，但是本领域的技术人员应该知道各种修改、增加及替换都是可能的，而不会脱离在权利要求中披露的本发明的范围和精神。
本发明要求2009年1月23日提交的韩国专利申请No.10-2009-0006134的优选权，其全部内容通过引用全部结合于此。

Claims (20)

1.一种立方半导体封装，包括：
第一半导体芯片模块，包括：
第一半导体芯片，包括：
焊垫，设置在第一表面上；
穿通电极，穿过所述半导体芯片的所述第一表面和与所述第一表面相反的第二表面；及
重配置线，设置于所述第一表面和所述第二表面的至少一个上，所述重配置线电耦接到所述穿通电极和所述焊垫，其中所述重配置线的端部与连接所述第一表面和所述第二表面的侧表面齐平；以及
设置于所述侧表面上的连接构件，电耦接到所述重配置线。
2.如权利要求1所述的立方半导体封装，其中所述重配置线包括延伸部，该延伸部从所述第一表面延伸至所述侧表面的至少一个。
3.如权利要求1所述的立方半导体封装，其中所述连接构件包括导电球。
4.如权利要求1所述的立方半导体封装，还包括粘结构件，覆盖所述重配置线并具有限定在其中的用于暴露所述穿通电极的开口。
5.如权利要求1所述的立方半导体封装，还包括堆叠在所述第一半导体芯片模块上的第二半导体芯片模块，所述第一半导体芯片模块和所述第二半导体芯片模块通过所述穿通电极而相互电耦接。
6.如权利要求5所述的立方半导体封装，其中导电球耦接到所述第一半导体芯片模块或所述第二半导体芯片模块的至少一个的穿通电极的端部。
7.如权利要求5所述的立方半导体封装，其中所述第一半导体芯片模块和所述第二半导体芯片模块具有基本上相同的尺寸和相同的形状。
8.如权利要求5所述的立方半导体封装，其中所述第一半导体芯片模块具有第一尺寸，所述第二水平半导体芯片模块具有与所述第一尺寸不同的第二尺寸，其中所述第一水平半导体芯片模块和所述第二水平半导体芯片模块的至少一个侧表面基本上相互齐平。
9.如权利要求5所述的立方半导体封装，还包括：
第三半导体芯片模块，沿着所述第一半导体芯片模块和所述第二半导体芯片模块的侧表面设置，使得所述第三半导体芯片模块与所述第一半导体芯片模块和所述第二水平半导体芯片模块基本上垂直，所述第三半导体芯片模块包括：
焊垫；以及
穿通电极，沿第二方向穿过所述第三半导体芯片模块，其中所述第三半导体芯片模块电耦接到所述第一半导体芯片模块和所述第二半导体芯片模块的焊垫和连接构件。
10.如权利要求9所述的立方半导体封装，还包括堆叠到所述第三半导体芯片模块上的第四半导体芯片模块，使得所述第三半导体芯片模块和所述第四半导体芯片模块的穿通电极相互电连接。
11.如权利要求9所述的立方半导体封装，其中所述第三半导体芯片模块包括用于存储数据的数据存储半导体芯片和用于处理数据的数据处理半导体芯片中的一个。
12.如权利要求9所述的立方半导体封装，其中所述第三半导体芯片模块的尺寸和形状大致与所述第一半导体芯片模块相同。
13.如权利要求9所述的立方半导体封装，其中所述第三半导体芯片模块具有与所述第一半导体芯片模块不同的尺寸和形状。
14.如权利要求9所述的立方半导体封装，其中所述第一半导体芯片模块和所述第二半导体芯片模块的连接构件耦接到所述第三半导体芯片模块的穿通电极。
15.如权利要求9所述的立方半导体封装，还包括插设在所述第一半导体芯片模块和所述第二半导体芯片模块与所述第三半导体芯片模块之间的间隙填充构件。
16.如权利要求1所述的立方半导体封装，其中所述重配置线由具有第一硬度和第一熔化温度的第一金属形成，所述连接构件由具有第二硬度和第二熔化温度的第二金属形成，其中所述第二硬度小于所述第一硬度，并且所述第二熔化温度低于所述第一熔化温度。
17.一种立方半导体封装，包括：
多个半导体芯片模块，每个所述半导体芯片模块包括：
焊垫，设置在第一表面上；
穿通电极，穿过所述半导体模块的第一表面和第二表面，所述第二表面与所述第一表面相反，以及
重配置线；以及
连接构件，设置于连接所述第一表面和所述第二表面的侧表面上，所述连接构件电耦接到所述重配置线。
18.如权利要求17所述的立方半导体封装，其中一部分所述半导体芯片模块水平堆叠，另一部分所述半导体芯片模块垂直附着于所述半导体芯片模块的水平堆叠部分。
19.如权利要求17所述的立方半导体封装，其中第一部分所述半导体芯片模块具有相互基本相同的形状和尺寸，另一部分所述半导体芯片模块具有与第一部分所述半导体芯片模块不同的形状和尺寸。
20.如权利要求18所述的立方半导体封装，其中一些垂直附着的半导体芯片模块相互附着。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253100A (zh) * 2013-06-28 2014-12-31 精材科技股份有限公司 晶片封装体
CN105023917A (zh) * 2014-04-30 2015-11-04 台湾积体电路制造股份有限公司 晶圆上芯片封装件及其形成方法
CN105590908A (zh) * 2014-11-12 2016-05-18 英特尔公司 集成电路封装技术和小形状因子或可穿戴装置的配置
CN106206499A (zh) * 2015-01-07 2016-12-07 台湾积体电路制造股份有限公司 半导体器件和方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101226270B1 (ko) * 2010-12-20 2013-01-25 에스케이하이닉스 주식회사 스택 패키지 및 스택 패키지의 칩 선택방법
US9190371B2 (en) * 2010-12-21 2015-11-17 Moon J. Kim Self-organizing network with chip package having multiple interconnection configurations
US9105562B2 (en) 2011-05-09 2015-08-11 Infineon Technologies Ag Integrated circuit package and packaging methods
US9425116B2 (en) 2011-05-09 2016-08-23 Infineon Technologies Ag Integrated circuit package and a method for manufacturing an integrated circuit package
US9269685B2 (en) 2011-05-09 2016-02-23 Infineon Technologies Ag Integrated circuit package and packaging methods
JP2013012685A (ja) * 2011-06-30 2013-01-17 Canon Inc 半導体装置
KR20130044052A (ko) * 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 적층 반도체 패키지
ITVI20120060A1 (it) 2012-03-19 2013-09-20 St Microelectronics Srl Sistema elettronico avente un' aumentata connessione tramite l'uso di canali di comunicazione orizzontali e verticali
US8933715B2 (en) 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
KR102076044B1 (ko) 2013-05-16 2020-02-11 삼성전자주식회사 반도체 패키지 장치
KR102099878B1 (ko) * 2013-07-11 2020-04-10 삼성전자 주식회사 반도체 패키지
KR102186203B1 (ko) 2014-01-23 2020-12-04 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9704830B1 (en) * 2016-01-13 2017-07-11 International Business Machines Corporation Semiconductor structure and method of making
CN107305861B (zh) * 2016-04-25 2019-09-03 晟碟信息科技（上海）有限公司 半导体装置及其制造方法
MY192051A (en) * 2016-12-29 2022-07-25 Intel Corp Stacked dice systems
KR102508552B1 (ko) * 2018-04-30 2023-03-10 에스케이하이닉스 주식회사 쓰루 몰드 비아를 포함하는 스택 패키지
US10854763B2 (en) 2018-09-17 2020-12-01 Gbt Technologies Inc. Multi-dimensional integrated circuit having multiple planes and memory architecture having a honeycomb or bee hive structure
US11862736B2 (en) 2018-09-17 2024-01-02 GBT Tokenize Corp. Multi-dimensional photonic integrated circuits and memory structure having optical components mounted on multiple planes of a multi-dimensional package
TWI740625B (zh) * 2020-08-27 2021-09-21 欣興電子股份有限公司 封裝結構及其製造方法
US20230071476A1 (en) * 2021-09-03 2023-03-09 Cisco Technology, Inc. Optimized power delivery for multi-layer substrate
US11809797B1 (en) 2022-07-31 2023-11-07 Gbt Technologies Inc. Systems and methods of predictive manufacturing of three-dimensional, multi-planar semiconductors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US20080274603A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw
US20080315388A1 (en) * 2007-06-22 2008-12-25 Shanggar Periaman Vertical controlled side chip connection for 3d processor package

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847448A (en) 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
US5235672A (en) * 1991-02-06 1993-08-10 Irvine Sensors Corporation Hardware for electronic neural network
US5561593A (en) * 1994-01-27 1996-10-01 Vicon Enterprises, Inc. Z-interface-board
US5781413A (en) 1996-09-30 1998-07-14 International Business Machines Corporation Method and apparatus for directing the input/output connection of integrated circuit chip cube configurations
US6034438A (en) * 1996-10-18 2000-03-07 The Regents Of The University Of California L-connect routing of die surface pads to the die edge for stacking in a 3D array
JP3012555B2 (ja) * 1997-05-29 2000-02-21 神戸日本電気ソフトウェア株式会社 多面体ｉｃパッケージ
KR200182574Y1 (ko) * 1997-12-30 2000-06-01 김영환 적층형 패키지
DE19801312A1 (de) * 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP4361670B2 (ja) * 2000-08-02 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
US6721187B2 (en) 2001-03-16 2004-04-13 International Business Machines Corporation Multi-layered high density connections
US6555920B2 (en) * 2001-07-02 2003-04-29 Intel Corporation Vertical electronic circuit package
US6433413B1 (en) * 2001-08-17 2002-08-13 Micron Technology, Inc. Three-dimensional multichip module
US6747347B2 (en) 2001-08-30 2004-06-08 Micron Technology, Inc. Multi-chip electronic package and cooling system
US6686654B2 (en) 2001-08-31 2004-02-03 Micron Technology, Inc. Multiple chip stack structure and cooling system
US6611052B2 (en) * 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10308855A1 (de) * 2003-02-27 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil und Halbleiterwafer, sowie Verfahren zur Herstellung derselben
DE102005030465B4 (de) 2005-06-28 2007-12-20 Infineon Technologies Ag Halbleiterstapelblock mit Halbleiterchips und Verfahren zur Herstellung desselben
KR100809696B1 (ko) * 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US7928549B2 (en) * 2006-09-19 2011-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit devices with multi-dimensional pad structures
KR100832845B1 (ko) * 2006-10-03 2008-05-28 삼성전자주식회사 반도체 패키지 구조체 및 그 제조 방법
KR100817073B1 (ko) * 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
KR100842921B1 (ko) * 2007-06-18 2008-07-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
TWI362102B (en) 2007-07-11 2012-04-11 Ind Tech Res Inst Three-dimensional dice-stacking package structure and method for manufactruing the same
US7767494B2 (en) * 2008-06-30 2010-08-03 Headway Technologies, Inc. Method of manufacturing layered chip package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US20080274603A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Package Having Through-Hole Via on Saw Streets Formed with Partial Saw
US20080315388A1 (en) * 2007-06-22 2008-12-25 Shanggar Periaman Vertical controlled side chip connection for 3d processor package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253100A (zh) * 2013-06-28 2014-12-31 精材科技股份有限公司 晶片封装体
CN104253100B (zh) * 2013-06-28 2017-04-12 精材科技股份有限公司 晶片封装体
CN105023917A (zh) * 2014-04-30 2015-11-04 台湾积体电路制造股份有限公司 晶圆上芯片封装件及其形成方法
CN105023917B (zh) * 2014-04-30 2018-02-27 台湾积体电路制造股份有限公司 晶圆上芯片封装件及其形成方法
CN105590908A (zh) * 2014-11-12 2016-05-18 英特尔公司 集成电路封装技术和小形状因子或可穿戴装置的配置
CN105590908B (zh) * 2014-11-12 2018-09-21 英特尔公司 集成电路封装技术和小形状因子或可穿戴装置的配置
CN106206499A (zh) * 2015-01-07 2016-12-07 台湾积体电路制造股份有限公司 半导体器件和方法
CN106206499B (zh) * 2015-01-07 2019-01-11 台湾积体电路制造股份有限公司 半导体器件和方法
US10269761B2 (en) 2015-01-07 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

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