CN104253100A - 晶片封装体 - Google Patents

晶片封装体 Download PDF

Info

Publication number
CN104253100A
CN104253100A CN201410299061.2A CN201410299061A CN104253100A CN 104253100 A CN104253100 A CN 104253100A CN 201410299061 A CN201410299061 A CN 201410299061A CN 104253100 A CN104253100 A CN 104253100A
Authority
CN
China
Prior art keywords
turning point
live width
line part
wafer encapsulation
passivation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410299061.2A
Other languages
English (en)
Other versions
CN104253100B (zh
Inventor
张义民
刘沧宇
何彦仕
温英男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN104253100A publication Critical patent/CN104253100A/zh
Application granted granted Critical
Publication of CN104253100B publication Critical patent/CN104253100B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

本发明提供一种晶片封装体，包含半导体晶片、绝缘层、重布局金属层以及焊接垫。半导体晶片具有导电垫、内连线结构以及电子元件。电子元件通过内连线结构电性连接导电垫。绝缘层设置于半导体晶片的表面上且具有第一开口以暴露出部分导电垫。重布局金属层设置于绝缘层上且具有对应导电垫的重布局金属线路，重布局金属线路通过第一开口与导电垫连接。焊接垫配置于绝缘层上且位于半导体晶片的一侧。其中，重布局金属线路延伸至焊接垫，使配置于半导体晶片的表面上的导电垫电性连接于该侧的焊接垫。本发明的晶片封装体不仅能够提升焊线打接的效率和良率，还具有较现有技术更长的元件寿命以及更佳的可靠度。

Description

晶片封装体
技术领域
本发明关于一种晶片封装体，且特别是有关于一种具有单侧焊接以及特殊焊接垫结构的晶片封装体。
背景技术
为了因应当代对于电子设备多功能、高效能等消费者要求，对于半导体晶片所制作的晶片封装体所展现的可靠度(reliability)要求亦日益严峻。在晶片封装体中，通常以重布局层(redistribution layer，RDL)的各线路两端分别对应连接至半导体晶片中各输入/输出(I/O)导电垫和晶片封装体的各焊接垫，再将焊线(bonding wire)打接至各焊接垫上，通过焊线使晶片封装体与印刷电路板整合，以印刷电路板进行信号的输入/输出，信号经由焊线以及重布局层中各金属线路，到达半导体晶片中各输入/输出(I/O)导电垫，以对半导体晶片进行控制，使半导体晶片发挥其预定的效能应用。
在现有技术中，通常焊接垫配置于晶片封装体的侧边以提供焊线打接制程的便利性，又为配合半导体晶片各处的输入/输出(I/O)导电垫位置，而将各焊接垫配置分布于晶片封装体的四周，如此便形成晶片四周均是焊接垫的典型结构。众所周知的是，通常晶片封装体元件中最易产生问题的位置就在于焊线打接处。若其中有一处失效，往往会造成整体晶片封装体元件故障的问题。因此提高焊线打接处的可靠性及寿命是电子业界相当重要的一个课题。
发明内容
本发明提供一种晶片封装体，具有仅需在晶片封装体单侧焊接的设计，能有效简化焊线打接制程，从而提升焊线打接的效率和良率。此外本发明的晶片封装体还具有特殊的焊接垫结构，能进一步减低焊线打接处产生氧化变质的问题，具有较现有技术更长的元件寿命以及更佳的可靠度。
本发明提出一种晶片封装体，包含半导体晶片、绝缘层、重布局金属层以及至少一焊接垫。半导体晶片，具有导电垫、内连线结构以及电子元件，导电垫设置于半导体晶片的表面，内连线结构与电子元件设置于半导体晶片内部，且电子元件通过内连线结构电性连接导电垫。绝缘层设置于半导体晶片的表面上，其中绝缘层具有第一开口以暴露出部分导电垫。重布局金属层设置于绝缘层上且具有对应导电垫的重布局金属线路，重布局金属线路通过第一开口与导电垫连接。焊接垫配置于绝缘层上且位于半导体晶片的一侧。其中，重布局金属线路延伸至焊接垫，使配置于半导体晶片的表面上的导电垫电性连接于该侧的焊接垫。
在本发明的一实施方式中，进一步包含第一钝化层，第一钝化层覆盖绝缘层、重布局金属层以及焊接垫，其中第一钝化层具有第二开口以暴露出部分焊接垫。
在本发明的一实施方式中，第一钝化层包含氧化硅。
在本发明的一实施方式中，重布局金属线路由至少二直线部以及至少一转折部所组成，其中二直线部沿不同方向延伸，转折部连接二直线部，二直线部的线宽小于转折部的线宽。
在本发明的一实施方式中，二直线部的线宽是30～35微米，转折部的线宽是80～85微米。
在本发明的一实施方式中，进一步包含第二钝化层，第二钝化层配置于第一钝化层上，其中第二钝化层亦具有第二开口以暴露出部分焊接垫。
在本发明的一实施方式中，第一钝化层包含氧化硅，第二钝化层包含氮化硅。
在本发明的一实施方式中，进一步包含第一焊点底层金属，第一焊点底层金属配置于第二开口内。
在本发明的一实施方式中，第一焊点底层金属包含镍金属层、钯金属层以及金金属层。镍金属层配置于焊接垫上。钯金属层配置于镍金属层上。金金属层配置于钯金属层上。
在本发明的另一实施方式中，进一步包含第二焊点底层金属，第二焊点底层金属完整覆盖焊接垫。
在本发明的另一实施方式中，第二焊点底层金属包含包含镍金属层、钯金属层以及金金属层。镍金属层配置于焊接垫上。钯金属层配置于镍金属层上。金金属层配置于钯金属层上。
在本发明的又一实施方式中，第二焊点底层金属完整覆盖重布局金属线路。
在本发明的又一实施方式中，进一步包含第三钝化层，第三钝化层覆盖绝缘层以及第二焊点底层金属，其中第三钝化层具有第三开口以暴露出部分第二焊点底层金属。
在本发明的又一实施方式中，进一步包含第四钝化层配置于第三钝化层上，其中第四钝化层亦具有第三开口以暴露出部分第二焊点底层金属。
在本发明的又一实施方式中，焊接垫的位置低于导电垫所在的半导体晶片的表面。
本发明还提出一种晶片封装体，包含一半导体晶片、一绝缘层以及一重布局金属层。该半导体晶片具有至少一导电垫、一内连线结构以及一电子元件，该导电垫设置于该半导体晶片的一表面，该内连线结构与该电子元件设置于该半导体晶片内部，且该电子元件通过该内连线结构电性连接该导电垫。该绝缘层设置于该半导体晶片的该表面上，其中该绝缘层具有至少一第一开口以暴露出部分该导电垫。该重布局金属层设置于该绝缘层上且具有对应该导电垫的至少一重布局金属线路，该重布局金属线路通过该第一开口与该导电垫连接，并延伸至该半导体晶片的一侧，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
附图说明
本发明的上述和其他态样、特征及其他优点参照说明书内容并配合附加图式得到更清楚的了解，其中：
图1绘示本发明的一实施方式的半导体晶片封装体的俯视图。
图2绘示沿图1中线段2的剖面图。
图3绘示沿图1中线段3的剖面图。
图4绘示图2中局部4的侧视图。
图5绘示本发明另一实施方式对应图1中线段3的剖面图。
图6绘示本发明又一实施方式对应图1中线段3的剖面图。
图7绘示本发明又一实施方式对应图1中线段3的剖面图。
图8绘示本发明又一实施方式对应图1中线段3的剖面图。
附图中符号的简单说明如下：
100：晶片封装体                 112：第二开口
102：半导体晶片                 114：第二钝化层
102a：导电垫                    116：第一焊点底层金属
102b：内连线结构                116a：镍金属层
102c：电子元件                  116b：钯金属层
104：绝缘层                     116c：金金属层
104a：第一开口                  118：第二焊点底层金属
106：重布局金属层               118a：镍金属层
106a：重布局金属线路            118b：钯金属层
106a1：直线部                   118c：金金属层
106a2：转折部                   120：第三钝化层
108：焊接垫                     122：第三开口
110：第一钝化层                 124：第四钝化层。
具体实施方式
请先同时参照图1以及图2，图1是本发明的一实施方式半导体晶片封装体100的俯视图。图2绘示沿图1中线段2的剖面图。
如图1以及图2所示，本发明的一实施方式的晶片封装体100包含半导体晶片102、绝缘层104、重布局金属层106以及焊接垫108。如图2所示，半导体晶片102具有至少一导电垫102a、内连线结构102b以及电子元件102c。导电垫102a设置于半导体晶片102的一表面，内连线结构102b与电子元件102c设置于半导体晶片102内部，且电子元件102c通过内连线结构102b电性连接导电垫102a。其中，半导体晶片102例如可以是硅基底(silicon base)半导体晶片、锗基底(germanium base)半导体晶片或其他III-V族基底的半导体晶片，但不以此为限。导电垫102a作为半导体晶片102的输入/输出(I/O)导电垫，其形状、数目以及位置分布可如图2所示，但不以此为限，可依实际需求作对应的设计变更。导电垫102a的材质例如可以是铜、铝、钨等所组成的单层或多层金属导体或导电高分子，但不以此为限。内连线结构102b例如可以是铜、铝、钨等所形成的金属线路作为电性导通路径，而电子元件102c例如可以是有源元件(active element)或无源元件(passive elements)、数字电路或模拟电路等集成电路的电子元件(electronic components)、光电元件(opto electronicdevices)、微机电系统(Micro Electro Mechanical Systems,MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)、或喷墨头(ink printer heads)等，但亦不以此为限。内连线结构102b和电子元件102c形成于半导体晶片102内部，内连线结构102b两端分别电性连接电子元件102c与导电垫102a，使位于半导体晶片102表面的导电垫102a作为输入/输出(I/O)导电垫，以对位于半导体晶片102内部的电子元件102c进行控制。
请继续参照图2所示，绝缘层104设置于半导体晶片102的该表面上，绝缘层104具有至少一第一开口104a以暴露出部分导电垫102a。绝缘层104例如可以是氧化硅(silicon oxide)、氮化硅(silicon nitride)、氮氧化硅(siliconoxynitride)或其它合适的绝缘材料，形成绝缘层104的方式例如可以是以化学气相沉积法(chemical vapor deposition，CVD)、旋转涂布法(spin coating)等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料全面沉积于半导体晶片102的该表面上并覆盖半导体晶片102表面的导电垫102a，再搭配微影蚀刻制程，将半导体晶片102表面的导电垫102a上方的绝缘层104蚀刻出第一开口104a，以暴露出导电垫102a的一部分，而该部分暴露出的导电垫102a作为导电垫102a与后续重布局金属层106电性连接处。
请继续参照图2所示，重布局金属层106设置于绝缘层104上且具有对应第一导电垫102a的重布局金属线路106a，重布局金属线路106a通过第一开口104a与导电垫102a连接。重布局金属层106的材质例如可以采用铝(aluminum)、铜(copper)或镍(nickel)或其他合适的金属材料，以溅镀(sputtering)、蒸镀(evaporation)或其他适当的制程方法，将重布局金属层106全面沉积于绝缘层104上，再以微影蚀刻的方式图案化，于绝缘层104上留下重布局金属线路106a，如图1所示，本实施例方式中各第一导电垫102a均分别对应有一条重布局金属线路106a。
请继续参照图2并搭配图1。焊接垫108亦配置于绝缘层104上且位于半导体晶片102的一侧。焊接垫108作为本实施方式的晶片封装体100打接焊线(wire-bonding)处，焊接垫108的材质例如可以采用铝(aluminum)、铜(copper)或镍(nickel)或其他合适的金属材料，焊接垫108形成的方式例如可以和前述的重布局金属层106同时或分别形成：将铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料，以溅镀(sputtering)、蒸镀(evaporation)或其他适当的制程方法沉积于绝缘层104上，再以微影蚀刻的方式图案化，于绝缘层104上留下仅位于半导体晶片102一侧的焊接垫108。其中值得注意的是，重布局金属线路106a延伸至仅位于半导体晶片102一侧的焊接垫108，使配置于半导体晶片102的表面的导电垫102a电性连接于该侧的焊接垫108，而这些仅位于半导体晶片102一侧的焊接垫108例如可以作为后续焊线打接处。打接的焊线可进一步连接印刷电路板，使得本实施方式的半导体晶片封装体100可通过焊接垫108以及重布局金属线路106a，电性导通半导体晶片102表面的导电垫102a，使半导体晶片102通过导电垫102a(输入/输出(I/O)导电垫)和印刷电路板之间进行信号输入或输出；或是打接的焊线亦可进一步连接其他半导体晶片或是其他半导体中介片(interposer)，使半导体晶片102可和其他半导体晶片或是其他半导体中介片整合而成立体晶片堆叠(3D-IC stacking)结构。本发明的一特征为：通过特殊图案的重布局金属层106，即例如利用微影蚀刻形成的各重布局金属线路106a，将分布于半导体晶片102表面各处的各导电垫102a的电性连接路径，全数集中至半导体晶片102的一侧的各焊接垫108。据此本实施方式的半导体晶片封装体100具有打线位置集中且统一于单一侧的特征，这将带来焊线打接制程亦可集中且统一地在单一侧进行，使得本实施方式的半导体晶片封装体100的制程较为简化并具有更高产出率(through put)的特点。
请参照图3并搭配图1以及图2，图3绘示图1中线段3的剖面图。在本发明的一实施方式中，进一步包含第一钝化层110覆盖绝缘层104、重布局金属层106以及焊接垫108，其中第一钝化层110具有至少一第二开口110a以暴露出部分焊接垫108。第一钝化层110例如可以是氧化硅(silicon oxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)或其它合适的绝缘材料，形成第一钝化层110的方式例如可以是以化学气相沉积法(chemical vapordeposition，CVD)、旋转涂布法(spin coating)等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料全面沉积，并覆盖半导体晶片102表面上的绝缘层104、重布局金属层106以及焊接垫108，再搭配微影蚀刻制程，将焊接垫108上方的第一钝化层110蚀刻出第二开口112，以暴露出焊接垫108的一部分，而该部分暴露出的焊接垫108作为后续焊线打接处。值得注意的是，本实施方式中的第一钝化层110因为覆盖住半导体晶片102表面的重布局金属层106，据此，水气或其它污染便隔绝于重布局金属层106之外，避免了各重布局金属线路106a产生氧化或变质的问题。此外更重要的是，第一钝化层110尚覆盖了部分的焊接垫108，仅留下第二开口112供后续焊线打接，明确言之，焊接垫108减少了暴露于水气或其它污染的面积，即降低了焊接垫108产生氧化或变质的机会，同时，第一钝化层110尚能提供焊接垫108于后续焊线打接过程中更良好的稳定性。众所周知的是，通常晶片封装体元件中最易产生问题的位置即在众多焊接处，若有一处失效，就易造成整个晶片封装体元件故障。据此，本实施方式的晶片封装体100因为具有不易氧化、稳定度高的焊接垫108，此即提供了后续焊线打接更好的焊接环境，因此本实施方式的晶片封装体100具有较现有技术更长的元件寿命以及更佳的可靠度(reliability)。
请参照图4并搭配图2，图4绘示图2中局部4的侧视图。在本发明的一实施方式中，重布局金属线路106a由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如图2所示，重布局金属线路106a由导电垫102a延伸至焊接垫108的路径上，会经过多个彼此之间具有高低差的平面(例如图2中的局部4)，这样的地形高度差异例如可以是由于导电垫102a出现的位置会垫高后续绝缘层104在此处的高度所致，但不以此为限。重布局金属线路106a在经过这样的地形高度差异时，在转折处(如图2中局部4所示的a、b平面)特别容易产生断线的问题，这是因为重布局金属层106全面沉积于绝缘层104上，再以微影蚀刻的方式图案化留下重布局金属线路106a的过程中，不论对于金属膜沉积制程或微影蚀刻制程，在不同方向的平面上维持相同的制程均匀性是具有高度制程挑战性的。换言之，膜沉积或是微影蚀刻制程在两个彼此相邻却不同方向的平面之间，较容易产生制程变异(process variation)，而使预订在两个彼此相邻却不同方向的平面上所形成的重布局金属线路106a，彼此偏移错位而无法衔接的情形，此即产生断线的问题。对此，如图4所示，在本发明的一实施方式中，重布局金属线路106a由三段相邻但位于不同平面的直线部106a1，以及衔接此三段不同平面的直线部106a1的转折部106a2所构成。值得注意的是，转折部106a2的线宽W2较直线部106a1的线宽W1更宽，在本发明的一实施方式中，直线部106a1的线宽W1实质上是30～35微米，转折部106a2的线宽W2是80～85微米。据此，即便位于不同平面的直线部106a1彼此偏移错位(如图4箭头所示)，线宽大的转折部106a2依然可使发生偏移错位的各直线部106a1连接起来。明确言之，本实施方式中特殊的重布局金属线路106a形态设计提供了更大的制程边际(process margin)。当制程变异(process variation)发生，使在不同方向的平面上的金属线路发生位置偏移时，仍能彼此顺利连接而不致断线。本实施方式中特殊的重布局金属线路106a形态可在特殊设计的光罩下，进行微影蚀刻制作，光罩的设计可以根据不同的电路设计，对应可能产生地形高度差异之处(例如图2中的局部4)设计较宽的线宽。转折部106a2的形状亦可针对不同需求作适当的调整，并不以图4所例示的态样为限。
此外，为更进一步地提升本发明的晶片封装体的元件寿命以及可靠度(reliability)，在焊接垫108的设计上可有以下各种不同的实施方式，以提供后续焊线打接更好的焊接环境。
请先参照图5并搭配图1，图5绘示本发明的另一实施方式对应图1中线段3的剖面图。在本实施方式的晶片封装体中，进一步包含第二钝化层114配置于第一钝化层110上，其中第二钝化层114亦具有第二开口112以暴露出部分焊接垫108。制作的方式例如可以是先以化学气相沉积法(chemical vapordeposition，CVD)、或旋转涂布法(spin coating)等制程方法将氧化硅(siliconoxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)或其它合适的绝缘材料沉积形成第一钝化层110，第一钝化层110覆盖半导体晶片102表面上的绝缘层104、重布局金属层106以及焊接垫108。接着再于第一钝化层110上，以化学气相沉积法、或旋转涂布法等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料沉积形成第二钝化层114。最后，再以微影蚀刻制程，将焊接垫108上方的第一钝化层110以及第二钝化层114蚀刻出第二开口112，以暴露出焊接垫108的一部分，而该部分暴露出的焊接垫108即作为后续焊线打接处。在本实施方式中，第一钝化层110例如可以包含氧化硅，而第二钝化层114包含氮化硅，但不以此为限。值得注意的是，本实施方式的晶片封装体较前述实施方式的晶片封装体多了一层第二钝化层114，能够更进一步地降低焊接垫108产生氧化或变质的机会，同时，更能提供焊接垫108于后续焊线打接过程中更良好的稳定性。据此，本实施方式的晶片封装体相较于前述实施方式的晶片封装体，具有更不易氧化、稳定度更高的焊接垫108，此即提供了后续焊线打接更好的焊接环境，因此能更进一步地提高元件寿命以及可靠度。此外，本实施方式的晶片封装体中，重布局金属线路106a的态样亦可参照前述实施方式(如图4所示)，即重布局金属线路106a可由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如前所述，本实施方式可同样采用特殊的重布局金属线路106a形态设计，以提供更大的制程边际(process margin)，当制程变异(processvariation)发生，导致不同方向的平面上的金属线路位置偏移时，仍能彼此顺利连接而不致断线。
请接着参照图6并搭配图1，图6绘示本发明又一实施方式对应图1中线段3的剖面图。在本实施方式的晶片封装体中，进一步包含第一焊点底层金属(Under Bump Metallurgy，UBM)116配置于第二开口112内。和前述各实施方式的晶片封装体不同的是，本实施方式的晶片封装体较前述实施方式的晶片封装体多了第一焊点底层金属116配置于第二开口112内，第一焊点底层金属116可避免焊线与焊接垫108发生反应导致元件失效的问题。第一焊点底层金属116例如可包含低消耗速率的镍(nickel，Ni)作为适当的阻障层材料，用以阻挡焊接垫与焊线之间扩散而形成脆性的金属间化合物(intermetalliccompound)，避免焊接处降低机械强度从而产生易断裂的问题。然镍对氧的活性较高，故尚可于镍层上再镀金(gold，Au)作为抗氧化层。如图6所示，在本发明的一实施方式中，第一焊点底层金属116包含镍(Ni)金属层116a、钯(Pd)金属层116b以及金(Au)金属层116c。镍(Ni)金属层116a配置于焊接垫108上；钯(Pd)金属层116b配置于镍金属层116a上；金(Au)金属层116c配置于钯金属层116b上。为使第一焊点底层金属116与焊接垫108具有良好的欧姆接触(Ohmic contact)，所以在沉积第一焊点底层金属116之前，可先使用干式或湿式化学蚀刻清洗法，将焊接垫108表面的氧化物加以清洗去除。制作第一焊点底层金属116的方式，例如可以是先以蒸镀(evaporation)、溅镀(sputtering)、或化镀(chemical plating)等金属成膜制程沉积所欲的金属膜层，再搭配微影蚀刻制程完成适当的图案，但不以此方式为限。此外，本实施方式的晶片封装体中，重布局金属线路106a的态样亦可参照前述实施方式(如图4所示)，即重布局金属线路106a可由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如前所述，本实施方式同样可采用特殊的重布局金属线路106a形态设计，以提供更大的制程边际(process margin)，当制程变异(process variation)发生，导致不同方向的平面上的金属线路位置偏移时，仍能彼此顺利连接而不致断线。
请接着参照图7并搭配图1，图7绘示本发明又一实施方式对应图1中线段3的剖面图。在本实施方式的晶片封装体中，进一步包含第二焊点底层金属118完整覆盖焊接垫108。本实施方式的第二焊点底层金属118相较于前述实施方式的第一焊点底层金属116的不同点在于：第二焊点底层金属118将焊接垫108完整覆盖，而前述实施方式的第一焊点底层金属116配置于第二开口112内，因此本实施方式中，第二焊点底层金属118的面积大于焊接垫108的面积；而前述实施方式之中，焊接垫108的面积大于第一焊点底层金属116的面积。第二焊点底层金属118同样可避免焊线与焊接垫108发生反应导致元件失效的问题。第二焊点底层金属118例如可包含镍作为适当的阻障层材料，用以阻挡焊接垫与焊线之间扩散而形成脆性的金属间化合物，避免焊接处降低机械强度从而产生易断裂的问题。然镍对氧的活性较高，故尚可于镍层上再镀金作为抗氧化层。如图7所示，在本发明的一实施方式中，第二焊点底层金属118包含镍(Ni)金属层118a、钯(Pd)金属层118b以及金(Au)金属层118c。镍(Ni)金属层118a完整覆盖焊接垫108；钯(Pd)金属层118b完整覆盖镍金属层118a；金(Au)金属层完整覆盖钯金属层118c。同样地，为使第二焊点底层金属118与焊接垫108具有良好的欧姆接触，所以在沉积第二焊点底层金属118之前，可先使用干式或湿式化学蚀刻清洗法，将焊接垫108表面的氧化物加以清洗去除。制作第二焊点底层金属118的方式，例如可以是先以蒸镀(evaporation)、溅镀(sputtering)、或化镀(chemical plating)等金属成膜制程沉积所欲的金属膜层，再搭配微影蚀刻制程完成适当的图案，但不以此方式为限。值得注意的是，在本发明的一实施方式中，第二焊点底层金属118完整覆盖重布局金属线路116a。制作的方式例如可以是在金属成膜制程之后，在微影制程使用对应重布局金属线路116a图案的光罩，如此不仅焊接垫108被第二焊点底层金属118完整覆盖，重布局金属线路116a亦被第二焊点底层金属118完整覆盖。据此本实施方式的晶片封装体不仅具有避免焊线与焊接垫108发生反应导致元件失效的功效，尚可保护晶片封装体中所有重布局金属线路116a。此外，本实施方式的晶片封装体中，重布局金属线路106a的态样亦可参照前述实施方式(如图4所示)，即重布局金属线路106a可由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如前所述，本实施方式同样可采用特殊的重布局金属线路106a形态设计，以提供更大的制程边际(process margin)，当制程变异(processvariation)发生，导致不同方向的平面上的金属线路位置偏移时，仍能彼此顺利连接而不致断线。
请接着参照图8并搭配图1，图8绘示本发明又一实施方式对应图1中线段3的剖面图。与图7所示本发明另一实施方式的晶片封装体不同之处在于：本实施方式的晶片封装体中，进一步包含第三钝化层120覆盖绝缘层104以及第二焊点底层金属118，其中第三钝化层120具有至少第三开口122以暴露出部分第二焊点底层金属118。第三钝化层120例如可以是氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料，形成第三钝化层120的方式例如可以是以化学气相沉积法、旋转涂布法等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料全面沉积，并覆盖半导体晶片102表面上的绝缘层104以及第二焊点底层金属118，再搭配微影蚀刻制程，将第二焊点底层金属118上方的第三钝化层120蚀刻出第三开口122，以暴露出第二焊点底层金属118的一部分，而该部分暴露出的第二焊点底层金属118作为后续焊线打接处。值得注意的是，本实施方式中的第三钝化层120因为覆盖住半导体晶片102表面的第二焊点底层金属118(包含焊接垫108上的第二焊点底层金属118部分以及重布局金属线路106a上的第二焊点底层金属118部分)，据此，水气或其它污染更可进一步隔绝于焊接垫108以及重布局金属线路106a之外，避免焊接垫108以及重布局金属线路106a产生氧化或变质的问题。同时，第一钝化层110尚能提供焊接垫108以及第二焊点底层金属118于后续焊线打接过程中更良好的稳定性。据此，本实施方式的晶片封装体因为具有更不易氧化、稳定度更高的焊接环境，因此本实施方式的晶片封装体相较于图7所绘示本发明另一实施方式，具有更长的元件寿命以及更佳的可靠度(reliability)。此外，本实施方式的晶片封装体中，重布局金属线路106a的态样亦可参照前述实施方式(如图4所示)，即重布局金属线路106a可由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如前所述，本实施方式同样可采用特殊的重布局金属线路106a形态设计，以提供更大的制程边际(process margin)，当制程变异(process variation)发生，导致不同方向的平面上的金属线路位置偏移时，仍能彼此顺利连接而不致断线。
再参照图8所示，在本发明的另一实施方式中，进一步包含第四钝化层124配置于第三钝化层120上，其中第四钝化层124亦具有第三开口122以暴露出部分第二焊点底层金属118。制作的方式例如可以是先以化学气相沉积法、或旋转涂布法等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料沉积形成第三钝化层120，第三钝化层120覆盖半导体晶片102表面上的绝缘层104以及第二焊点底层金属118。接着再于第三钝化层120上，以化学气相沉积法、或旋转涂布法等制程方法将氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料沉积形成第四钝化层124。最后，再以微影蚀刻制程，将第二焊点底层金属118(覆盖焊接垫108的部分)上方的第一钝化层110以及第二钝化层114蚀刻出第二开口112，以暴露出第二焊点底层金属118的一部分，而此部分暴露出的第二焊点底层金属118即作为后续焊线打接处。值得注意的是，本实施方式的晶片封装体较前述实施方式的晶片封装体多了第二钝化层114，能够更进一步地降低第二焊点底层金属118产生氧化或变质的机会，同时，更能提供后续焊线打接过程中更良好的稳定性。据此，本实施方式的晶片封装体相较于前述实施方式的晶片封装体，具有更不易氧化、稳定度更高的焊接环境，因此能更进一步地提高元件寿命以及可靠度。此外，本实施方式的晶片封装体中，重布局金属线路106a的态样亦可参照前述实施方式(如图4所示)，即重布局金属线路106a可由至少二直线部106a1以及至少一转折部106a2所组成，其中二直线部106a1沿不同方向延伸，转折部106a2连接二直线部106a1，二直线部106a1的线宽W1小于转折部106a2的线宽W2。如前所述，本实施方式可同样采用特殊的重布局金属线路106a形态设计，以提供更大的制程边际(process margin)，当制程变异(process variation)发生，导致不同方向的平面上的金属线路位置偏移时，仍能彼此顺利连接而不致断线。
最后要强调的是，在半导体晶片尺寸微缩而执行功能却须增加的驱势下，通过本发明所揭示的晶片封装体的特殊结构，可有效缩减或免除现有技术中所必须具有的打线间距(wire-bonding area)，使得一定面积的半导体晶片封装体中，半导体晶片所保留的可供布线的晶片空间更大，进而使半导体晶片发挥更高的效能。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (28)

1.一种晶片封装体，其特征在于，包含：
一半导体晶片，具有至少一导电垫、一内连线结构以及一电子元件，该导电垫设置于该半导体晶片的一表面，该内连线结构与该电子元件设置于该半导体晶片内部，且该电子元件通过该内连线结构电性连接该导电垫；
一绝缘层，设置于该半导体晶片的该表面上，其中该绝缘层具有至少一第一开口以暴露出部分该导电垫；
一重布局金属层，设置于该绝缘层上且具有对应该导电垫的至少一重布局金属线路，该重布局金属线路通过该第一开口与该导电垫连接；以及
至少一焊接垫，配置于该绝缘层上且位于该半导体晶片的一侧，
其中，该重布局金属线路延伸至该焊接垫，使配置于该半导体晶片的该表面上的该导电垫电性连接于该侧的该焊接垫。
2.根据权利要求1的晶片封装体，其特征在于，进一步包含一第一钝化层，该第一钝化层覆盖该绝缘层、该重布局金属层以及该焊接垫，其中该第一钝化层具有至少一第二开口以暴露出部分该焊接垫。
3.根据权利要求2的晶片封装体，其特征在于，该第一钝化层包含氧化硅。
4.根据权利要求2的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
5.根据权利要求4的晶片封装体，其特征在于，该至少二直线部的线宽是30～35微米，该至少一转折部的线宽是80～85微米。
6.根据权利要求2的晶片封装体，其特征在于，进一步包含一第二钝化层，该第二钝化层配置于该第一钝化层上，其中该第二钝化层亦具有该第二开口以暴露出部分该焊接垫。
7.根据权利要求6的晶片封装体，其特征在于，该第一钝化层包含氧化硅，该第二钝化层包含氮化硅。
8.根据权利要求6的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该至少二直线部沿不同方向延伸，该至少一转折部连接该至少二直线部，该至少二直线部的线宽小于该至少一转折部的线宽。
9.根据权利要求8的晶片封装体，其特征在于，该至少二直线部的线宽是30～35微米，该至少一转折部的线宽是80～85微米。
10.根据权利要求7的晶片封装体，其特征在于，进一步包含一第一焊点底层金属，该第一焊点底层金属配置于该第二开口内。
11.根据权利要求10的晶片封装体，其特征在于，该第一焊点底层金属包含：
一镍金属层，配置于该焊接垫上；
一钯金属层，配置于该镍金属层上；以及
一金金属层，配置于该钯金属层上。
12.根据权利要求11的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该至少二直线部沿不同方向延伸，该至少一转折部连接该至少二直线部，该至少二直线部的线宽小于该至少一转折部的线宽。
13.根据权利要求12的晶片封装体，其特征在于，该至少二直线部的线宽是30～35微米，该至少一转折部的线宽是80～85微米。
14.根据权利要求1的晶片封装体，其特征在于，进一步包含一第二焊点底层金属，该第二焊点底层金属完整覆盖该焊接垫。
15.根据权利要求14的晶片封装体，其特征在于，该第二焊点底层金属包含：
一镍金属层，完整覆盖该焊接垫；
一钯金属层，完整覆盖该镍金属层；以及
一金金属层，完整覆盖该钯金属层上。
16.根据权利要求14的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
17.根据权利要求16的晶片封装体，其特征在于，该二直线部的线宽是30～35微米，该转折部的线宽是80～85微米。
18.根据权利要求14的晶片封装体，其特征在于，该第二焊点底层金属，该第二焊点底层金属完整覆盖该重布局金属线路。
19.根据权利要求18的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
20.根据权利要求19的晶片封装体，其特征在于，该二直线部的线宽是30～35微米，该转折部的线宽是80～85微米。
21.根据权利要求18的晶片封装体，其特征在于，进一步包含一第三钝化层，该第三钝化层覆盖该绝缘层以及该第二焊点底层金属，其中该第三钝化层具有至少一第三开口以暴露出部分该第二焊点底层金属。
22.根据权利要求21的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
23.根据权利要求22的晶片封装体，其特征在于，该二直线部的线宽是30～35微米，该转折部的线宽是80～85微米。
24.根据权利要求19的晶片封装体，其特征在于，进一步包含一第四钝化层，该第四钝化层配置于该第三钝化层上，其中该第四钝化层亦具有该第三开口以暴露出部分该第二焊点底层金属。
25.根据权利要求24的晶片封装体，其特征在于，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
26.根据权利要求25的晶片封装体，其特征在于，该二直线部的线宽是30～35微米，该转折部的线宽是80～85微米。
27.根据权利要求1的晶片封装体，其特征在于，该焊接垫的位置低于该导电垫所在的该半导体晶片的表面。
28.一种晶片封装体，其特征在于，包含：
一半导体晶片，具有至少一导电垫、一内连线结构以及一电子元件，该导电垫设置于该半导体晶片的一表面，该内连线结构与该电子元件设置于该半导体晶片内部，且该电子元件通过该内连线结构电性连接该导电垫；
一绝缘层，设置于该半导体晶片的该表面上，其中该绝缘层具有至少一第一开口以暴露出部分该导电垫；以及
一重布局金属层，设置于该绝缘层上且具有对应该导电垫的至少一重布局金属线路，该重布局金属线路通过该第一开口与该导电垫连接，并延伸至该半导体晶片的一侧，该重布局金属线路由至少二直线部以及至少一转折部所组成，其中该二直线部沿不同方向延伸，该转折部连接该二直线部，该二直线部的线宽小于该转折部的线宽。
CN201410299061.2A 2013-06-28 2014-06-27 晶片封装体 Active CN104253100B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361841087P 2013-06-28 2013-06-28
US61/841,087 2013-06-28

Publications (2)

Publication Number Publication Date
CN104253100A true CN104253100A (zh) 2014-12-31
CN104253100B CN104253100B (zh) 2017-04-12

Family

ID=52114802

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410299061.2A Active CN104253100B (zh) 2013-06-28 2014-06-27 晶片封装体

Country Status (3)

Country Link
US (1) US9236320B2 (zh)
CN (1) CN104253100B (zh)
TW (1) TWI563607B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI674649B (zh) * 2015-11-19 2019-10-11 精材科技股份有限公司 晶片封裝體及其製造方法
CN116895573A (zh) * 2023-07-21 2023-10-17 鑫祥微电子(南通)有限公司 一种免焊线芯片封装结构及其封装方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9640683B2 (en) 2013-11-07 2017-05-02 Xintec Inc. Electrical contact structure with a redistribution layer connected to a stud
TWI564961B (zh) * 2015-03-06 2017-01-01 精材科技股份有限公司 半導體結構及其製造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1183169A (zh) * 1995-04-05 1998-05-27 北卡罗来纳州微电子中心 用于微电子衬底的焊料突点结构
US5946552A (en) * 1996-08-20 1999-08-31 International Business Machines Corporation Universal cost reduced substrate structure method and apparatus
TW516139B (en) * 2001-08-30 2003-01-01 Chipmos Technologies Inc Flip chip semiconductor device and method for forming the redistribution traces of the same
US20080185738A1 (en) * 2007-02-01 2008-08-07 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN101789419A (zh) * 2009-01-23 2010-07-28 海力士半导体有限公司 立方半导体封装
CN102800650A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于ic钝化结构的均匀度控制
US8431479B2 (en) * 2009-10-30 2013-04-30 Samsung Electronics Co., Ltd. Semiconductor devices having redistribution structures and packages, and methods of forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI528514B (zh) * 2009-08-20 2016-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
US8084871B2 (en) * 2009-11-10 2011-12-27 Maxim Integrated Products, Inc. Redistribution layer enhancement to improve reliability of wafer level packaging
US9099396B2 (en) * 2011-11-08 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1183169A (zh) * 1995-04-05 1998-05-27 北卡罗来纳州微电子中心 用于微电子衬底的焊料突点结构
US5946552A (en) * 1996-08-20 1999-08-31 International Business Machines Corporation Universal cost reduced substrate structure method and apparatus
TW516139B (en) * 2001-08-30 2003-01-01 Chipmos Technologies Inc Flip chip semiconductor device and method for forming the redistribution traces of the same
US20080185738A1 (en) * 2007-02-01 2008-08-07 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN101789419A (zh) * 2009-01-23 2010-07-28 海力士半导体有限公司 立方半导体封装
US8431479B2 (en) * 2009-10-30 2013-04-30 Samsung Electronics Co., Ltd. Semiconductor devices having redistribution structures and packages, and methods of forming the same
CN102800650A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于ic钝化结构的均匀度控制

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI674649B (zh) * 2015-11-19 2019-10-11 精材科技股份有限公司 晶片封裝體及其製造方法
CN116895573A (zh) * 2023-07-21 2023-10-17 鑫祥微电子(南通)有限公司 一种免焊线芯片封装结构及其封装方法
CN116895573B (zh) * 2023-07-21 2024-03-05 鑫祥微电子(南通)有限公司 一种免焊线芯片封装设备及其封装方法

Also Published As

Publication number Publication date
US20150001710A1 (en) 2015-01-01
CN104253100B (zh) 2017-04-12
TW201501250A (zh) 2015-01-01
US9236320B2 (en) 2016-01-12
TWI563607B (en) 2016-12-21

Similar Documents

Publication Publication Date Title
TWI662670B (zh) 電子元件封裝體及其製造方法
US8120176B2 (en) Semiconductor device having a conductive bump
US8952501B2 (en) Chip package and method for forming the same
US8728871B2 (en) Method for fabricating electronic device package
US7663222B2 (en) Semiconductor device and method for producing same
KR101008512B1 (ko) 웨이퍼-레벨의 볼 그리드 어레이 패키징을 위한 고 신뢰성저 비용 구조체
US11735555B2 (en) Manufacturing method of semiconductor structure
US9437478B2 (en) Chip package and method for forming the same
US8975755B2 (en) Chip package
US9355975B2 (en) Chip package and method for forming the same
CN104900607A (zh) 晶片封装体及其制造方法
US20120184070A1 (en) Method for forming chip package
CN105047619A (zh) 晶片堆叠封装体及其制造方法
CN104253100A (zh) 晶片封装体
US8786093B2 (en) Chip package and method for forming the same
US8697566B2 (en) Bump structure and manufacturing method thereof
US20120104445A1 (en) Chip package and method for forming the same
KR100789571B1 (ko) 반도체 소자 및 그 제조방법
CN104112717A (zh) 晶片封装体及其制造方法
TWI482253B (zh) 晶片封裝體
CN105742193A (zh) 晶圆与晶圆接合的工艺及结构
TWI434440B (zh) 晶片封裝體及其形成方法
TWI539568B (zh) 電子元件封裝體及其製造方法
TW201537674A (zh) 晶片封裝體及其製造方法
JP5936903B2 (ja) 加速度信号処理装置および電子デバイス

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant