TWI482253B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TWI482253B
TWI482253B TW098145253A TW98145253A TWI482253B TW I482253 B TWI482253 B TW I482253B TW 098145253 A TW098145253 A TW 098145253A TW 98145253 A TW98145253 A TW 98145253A TW I482253 B TWI482253 B TW I482253B
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Taiwan
Prior art keywords
conductive pads
chip package
wafer
metal
gap
Prior art date
Application number
TW098145253A
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English (en)
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TW201123393A (en
Inventor
Chia Lun Tsai
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Xintec Inc
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Publication date
Application filed by Xintec Inc filed Critical Xintec Inc
Priority to TW098145253A priority Critical patent/TWI482253B/zh
Priority to US12/766,362 priority patent/US9269732B2/en
Publication of TW201123393A publication Critical patent/TW201123393A/zh
Application granted granted Critical
Publication of TWI482253B publication Critical patent/TWI482253B/zh

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Description

晶片封裝體
本發明係有關於晶片封裝體，特別有關於一種晶片封裝體的密封環結構。
目前業界針對晶片的封裝已發展出一種晶圓級封裝技術，於晶圓級封裝體完成之後，需在各晶片之間進行切割步驟，以分離各晶片，為了降低切割步驟中產生的裂縫延伸至晶片內的機率，在各晶片之間需設置密封環，以提高晶片封裝體的可靠度。此外，密封環如佔用額外的面積，則晶圓上的晶粒總數可能減少。
本發明之一實施例提供一種晶片封裝體，包括：一晶片，具有複數個導電墊，設置於晶片周圍；以及一密封環，包括複數個金屬條狀物，設置於兩鄰接導電墊所圍的空間範圍內，且每一金屬條狀物不同時與兩鄰接的導電墊電性連接。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
以下以實施例並配合圖式詳細說明本發明，在圖式或說明書描述中，相似或相同之部分係使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖式中各元件之部分將以描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明係以一製作影像感測元件封裝體(image sensor package)的實施例作為說明。然而，可以了解的是，在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1圖係顯示依據本發明之一實施例的晶片封裝體之密封環所在區域的上視圖，在各晶片30的周圍由一密封環32圍繞，兩密封環32之間為切割道c。第2A圖為第1圖中框線3B處的放大上視圖，由第2A圖中可清楚看出多個導電墊沿著晶片周圍設置，密封環32則包括兩鄰接導電墊34之間的金屬條狀物40。在一實施例中，金屬條狀物40整體可位於由兩鄰接導電墊34所圍之空間範圍內，因此，本實施例之密封環結構可利用導電墊34本身以及兩相鄰導電墊之間的空間完成。在另一實施例中，如密封環32之寬度不超過兩鄰接導電墊34之寬度，則兩相鄰密封環32之間的寬度如需約為80μm，則所需的切割道寬度c亦僅80μm，以8吋的晶圓而言，晶粒總數可因此增加。此外，本實施例之密封環結構設計還可以適用於板上晶片封裝(chip on board，簡稱COB)及晶片級封裝(chip scale package，簡稱CSP)製程。
在一實施例中，導電墊34可以為延伸接觸墊，其係利用連接部36與晶片上的接合墊電性連接，在延伸接觸墊與接合墊之間不需保留空間設置內密封環，因此可進一步縮小晶片的面積。
在一實施例中，導電墊34的寬度w例如約為50μm，而金屬條狀物40的寬度例如約為10μm，因此如第2A圖所示，在導電墊34之間可設置3條互相平行的金屬條狀物41、43和45。此外，在另一實施例中，於導電墊34之間也可以設置3條以上或以下的金屬條狀物，端視實際需求而定。值得注意的是，每一個金屬條狀物41、43和45兩端不會同時與相鄰的兩導電墊34電性連接，亦即至少具有一間隙，其位於每一個金屬條狀物與兩端之導電墊之間，以避免短路，其中，至少一外間隙位於兩導電墊所圍空間的外側；而至少一內間隙位於兩導電墊所圍空間的內側。舉例而言，鄰接晶片外部如切割道c之金屬條狀物41與導電墊34之間包括一外間隙41a，鄰接晶片30內部之金屬條狀物45與導電墊34之間包括一內間隙45a。在另一實施例中，外間隙41a與內間隙45a兩者可形成一彎曲通道，其大於此外間隙41a與內間隙45a兩者之直線間距d，亦即，可藉由金屬條狀物41、43及/或45使切割步驟所產生的應力必須沿著兩金屬條狀物如41、43或43、45之間的彎曲通道才能進入，避免上述應力自外間隙直接穿過內間隙而形成延伸至晶片內部的裂縫。
接著，請參閱第2B圖，其係顯示密封環32的局部結構立體圖，在此實施例中，導電墊34具有三層金屬層341、342和343，並且從導電墊34延伸至與接合墊(未繪出)電性連接的連接部36也具有三層金屬層361、362和363。在此實施例中，導電墊係以三層金屬層與接合墊電性連接，然而，在另一實施例中，也可以只利用一層金屬層連接至接合墊，例如利用中間的金屬層362連接至接合墊。在一實施例中，導電墊34的三層金屬層341、342和343之間具有多個導孔42，以電性連接各金屬層，導孔42的位置並不限定，同時導孔42還可以阻擋部分的裂縫，避免其延伸至晶片內部。
在一實施例中，兩導電墊34之間的各金屬條狀物41、43和45也可以具有三層金屬層，如第2B圖中所示，金屬條狀物41具有三層金屬層411、412和413，並且在各金屬層411、412和413之間具有多個導孔42，以電性連接各金屬層，導孔42的位置可任意設置。在一實施例中，由於在製程上可選擇導電墊的金屬層與金屬條狀物的金屬層同時形成，因此，導電墊之金屬層的層數與金屬條狀物之金屬層的層數可以相同。值得注意的是，在一實施例中，金屬條狀物41的金屬層411、412和413之間至少具有一應力擋牆44，該應力擋牆44除可以更加強化密封環32的結構外，更可以有效地阻擋裂縫，避免其延伸至晶片內部。在另一實施例中，每一金屬條狀物41、43和45的金屬層之間至少具有一應力擋牆，亦即金屬條狀物41、43和45都各自具有一應力擋牆，如第2B圖所示，此應力擋牆與導電墊間之間隙可依上述第2A圖所述方式設置，以使切割步驟所產生的應力必須沿著兩應力擋牆之間的延伸通道進入，避免上述應力自外間隙直接穿過內間隙而形成延伸至晶片內部的裂縫。
在本實施例之密封環結構中，導電墊34之間的金屬條狀物40之設置方式可以有許多種型態，第2A圖所示為其中一種型態。另外，第3A至3B圖係顯示其他兩種型態，請參閱第3A圖，在一實施例中，導電墊34之間具有兩個互相平行的金屬條狀物401和403，金屬條狀物401和403的一端與導電墊34連接，另一端則與導電墊之間保持一間隙，金屬條狀物401和403與導電墊34之間的間隙交錯排列，使切割步驟所產生的應力必須沿著兩金屬條狀物401和403之間的延伸通道S進入，可避免裂縫直接延伸至晶片內部。
接著，請參閱第3B圖，在此實施例中，導電墊34之間具有三個金屬條狀物405、407和408，其中的金屬條狀物405和407位於同一直線上，其所排列的直線方向係垂直於導電墊34，且金屬條狀物405和407的一端與導電墊34連接，在金屬條狀物405和407之間具有一間隙。另一金屬條狀物408則與405、407平行排列，且金屬條狀物408的兩端皆與導電墊34保持一間隙。值得注意的是，第3B圖中的這些間隙也是交錯排列。
雖然在本發明說明書中僅列舉幾種金屬條狀物的排列方式，然而，可以理解的是，在導電墊之間的金屬條狀物還可以有其他種排列方式，只要這些金屬條狀物不會使導電墊之間產生短路，並且其與兩導電墊之間的間隙或各金屬條狀物之間的間隙彼此呈交錯排列即可。
第4A-4F圖係顯示依據本發明一實施例之製作晶片封裝體的各製程步驟之剖面示意圖，這些剖面圖係顯示沿著第2A圖中線X-X’之切斷面，其係在導電墊34的位置上，因此不會顯示金屬條狀物40。請參閱第4A圖，首先，提供一基底100，例如為半導體晶圓，在半導體晶圓100上具有複數個晶片(未顯示)，例如為影像感測元件，並且在影像感測元件上可具有對應的微透鏡陣列110做為影像感測面。半導體晶圓之基底上具有一介電層104，例如為氧化矽，每一晶片具有對應的導電墊(conductive pad)102，設置於此介電層104中。
接著，將半導體晶圓100的正面，亦即具有晶片的表面與封裝層200黏接，封裝層係做為封裝的承載結構，其可以是例如玻璃、石英(quartz)、蛋白石(opal)、塑膠或其它任何可供光線進出的透明基板。值得一提的是，也可以選擇性地形成濾光片(filter)及/或抗反射層(anti-reflective layer)於封裝層上。在封裝層200與半導體晶圓100之間可設置間隔層(spacer)106，使半導體晶圓100與封裝層200之間形成間隙(cavity)107，間隙107被間隔層106所圍繞。
上述間隔層106可以是環氧樹脂(epoxy)、防銲層(solder mask)或其它適合之絕緣物質，例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物或其組合，或者是有機高分材料之聚醯亞胺樹脂(polyimide;PI)、苯環丁烯(butylcyclobutene;BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等，且此間隔層106可以是利用塗佈方式，例如旋轉塗佈(spin coating)、噴塗(spray coating)或淋幕塗佈(curtain coating)，或者是其它適合之沈積方式，例如液相沈積(liquid phase deposition)、物理氣相沈積(physical vapor deposition;PVD)、化學氣相沈積(chemical vapor deposition;CVD)、低壓化學氣相沈積(low pressure chemical vapor deposition;LPCVD)、電漿增強式化學氣相沈積(plasma enhanced chemical vapor deposition;PECVD)、快速熱化學氣相沈積(rapid thermal-CVD;RTCVD)或常壓化學氣相沈積(atmospheric pressure chemical vapor deposition;APCVD)的方式形成，以隔絕環境污染或避免水氣侵入。
在一實施例中，上述影像感測元件可以是互補式金氧半導體元件(CMOS)或電荷耦合元件(charge-couple device;CCD)。此外，上述導電墊102也可以是延伸接合墊(extension pad)，且較佳可以由銅(copper;Cu)、鋁(aluminum;Al)或其它合適的金屬材料所製成。
接著，請參閱第4B圖，從半導體晶圓100的背面薄化半導體晶圓，成為一具有預定厚度的半導體晶圓100’，該薄化製程可以是蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)等方式。接著，以刻痕製程在薄化後的半導體晶圓100’之背面形成凹口(notch)109。在此凹口109形成後，半導體晶圓100’會被隔離出多顆半導體晶片(chip)
請參閱第4C圖，蝕刻凹口109底部的介電層104至暴露出導電墊102的接觸表面。接著，請參閱第4D圖，形成絕緣層112以覆蓋凹口109的側部區以及半導體晶圓100’的背面。在一實施例中，上述絕緣層112可以是環氧樹脂、防銲層或其它適合之絕緣物質，例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物或其組合，或者是有機高分材料之聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯等，且此絕緣層112可以利用塗佈方式，例如旋轉塗佈、噴塗或淋幕塗佈，或者是其它適合之沈積方式，例如液相沈積、物理氣相沈積、化學氣相沈積、低壓化學氣相沈積、電漿增強式化學氣相沈積、快速熱化學氣相沈積或常壓化學氣相沈積的方式形成，以隔離半導體晶圓100’與後續形成之導線層114。
接著，在凹口109內及半導體晶圓100’的背面上形成導線層114，可藉由例如是物理氣相沈積法(PVD)或濺鍍法(sputtering)，順應性地沈積例如是銅、鋁、銀(silver;Ag)、鎳(nickel;Ni)或其合金的導電層在凹口109內及半導體晶圓100’的背面上，再藉由微影蝕刻製程圖案化導電層，以形成導線層114。導線層114與導電墊102的表面接觸，形成一L型接觸，並延伸至半導體晶圓100’背面上的終端接觸(未繪出)。
接著，請參閱第4E圖，形成保護層(passivation)116於導線層114上，覆蓋半導體晶圓100’的背面以及凹口，保護層例如為阻焊膜(solder mask)。然後，請參閱第4F圖，形成導電凸塊(conductive bump)118穿過保護層116與導線層14電性連接。在一實施例中，於形成上述保護層116後，圖案化此保護層116，以形成一暴露部分導線層114的開口，接著，藉由電鍍或網版印刷(screen printing)的方式，將一銲料(solder)填入於上述開口中，且進行一迴銲(re-flow)製程，以形成例如是銲球(solder ball)或銲墊(solder paste)的導電凸塊118。接著，沿切割道(scribe line)分割上述晶片的晶圓級封裝體，以分離各晶片，完成本發明之晶片封裝體。
依據本發明一實施例之晶片封裝體的製造方法，導電墊102並未被蝕刻，導電墊102僅露出接觸面與導線層114接觸，以形成L型接觸。因此，由導電墊以及導電墊之間的金屬條狀物所組成的密封環在晶片封裝體的製造過程中不會受到損害，可以達到密封環之功效。
綜上所述，本發明之密封環結構包含各種實施例。例如在一實施例中，其係利用導電墊本身以及兩導電墊之間的空間。在另一實施例中，密封環結構的寬度不會超過導電墊的寬度。或在另一實施例中，密封環包括多個金屬條狀物，其與兩相鄰導電墊間具有至少一外間隙及一內間隙，兩者形成之彎曲通道可降低應力。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
30．．．晶片
36．．．連接部
32．．．密封環
34．．．導電墊
40、41、43、45、401-408．．．金屬條狀物
41a．．．外間隙
45a．．．內間隙
w．．．導電墊的寬度
d．．．外間隙與內間隙之間距
42．．．導孔
44．．．應力擋牆
341、342、343．．．導電墊之金屬層
411、412、413．．．金屬條狀物之金屬層
361、362、363．．．連接部之金屬層
100．．．晶圓基板
100’．．．薄化的晶圓基底
102．．．導電墊
104．．．介電層
106．．．間隔層
107．．．空穴
109．．．凹口
110．．．微透鏡陣列
112．．．絕緣層
114．．．導線層
116．．．保護層
118．．．導電凸塊
200．．．封裝層
c．．．切割道
S．．．兩金屬條狀物之間的彎曲通道
第1圖為依據本發明一實施例之晶片封裝體之密封環結構所在區域的上視圖；
第2A圖為第1圖中框線3B處之放大示意圖；
第2B圖為依據本發明一實施例之密封環結構的局部結構立體圖；
第3A圖為依據本發明一實施例之密封環結構的上視圖；
第3B圖為依據本發明另一實施例之密封環結構的上視圖；以及
第4A-4F圖為依據本發明一實施例之製作晶片封裝體的各製程步驟之剖面示意圖。
32．．．密封環
34．．．導電墊
36．．．連接部
40、41、43、45．．．金屬條狀物
41a．．．外間隙
45a．．．內間隙
w．．．導電墊的寬度
d．．．外間隙與內間隙之間距

Claims (14)

  1. 一種晶片封裝體，包括：一晶片，具有複數個導電墊，設置於該晶片周圍；及一密封環，包括複數個金屬條狀物，設置於兩鄰接導電墊所圍的空間範圍內，每一該金屬條狀物不同時與上述兩鄰接的導電墊電性連接，並且上述兩鄰接的導電墊不互相電性連接。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中，該些導電墊具有一寬度，且該些金屬條狀物位於上述兩相鄰導電墊之寬度所圍的空間範圍內，且該些金屬條狀物彼此平行排列。
  3. 如申請專利範圍第1項或第2項所述之晶片封裝體，其中每一該金屬條狀物至少與上述兩相鄰導電墊之一相隔一間隙。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中，上述兩相鄰導電墊之寬度所圍的空間外側更包括一外間隙，且上述兩相鄰導電墊之寬度所圍的空間內側更包括一內間隙，該外間隙與該內間隙所形成的彎曲通道，係大於該外間隙與該內間隙兩者之直線間距。
  5. 如申請專利範圍第3項所述之晶片封裝體，其中該些間隙係錯位排列。
  6. 如申請專利範圍第4項所述之晶片封裝體，其中該彎曲通道包括一沿著兩金屬條狀物之間的空間作為連通通道。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該導電墊包括複數層金屬層。
  8. 如申請專利範圍第7項所述之晶片封裝體，更包括複數個導孔設置於該導電墊的該些金屬層之間。
  9. 如申請專利範圍第7項所述之晶片封裝體，其中該金屬條狀物包括複數層金屬層。
  10. 如申請專利範圍第9項所述之晶片封裝體，該金屬條狀物的該些金屬層之層數與該導電墊的該些金屬層之層數相同。
  11. 如申請專利範圍第9項所述之晶片封裝體，更包括至少一應力擋牆設置於該金屬條狀物的該些金屬層之間。
  12. 如申請專利範圍第9項所述之晶片封裝體，其中每一該金屬條狀物的各金屬層之間具有一應力擋牆。
  13. 如申請專利範圍第3項所述之晶片封裝體，更包括：一封裝層，設置於該晶片之上，與該晶片的一第一表面接合；一導線層，設置於該晶片中相對於該第一表面之一第二表面上，延伸至與該些導電墊的一表面接觸；一保護層，設置於該導線層之上，具有一開口暴露出一部份的該導線層；以及一導電凸塊，設置於該開口上，與該導線層電性連接。
  14. 一種晶片封裝體，包括： 一晶片，具有複數個導電墊，設置於該晶片周圍，該些導電墊具有一寬度；以及一密封環，包括複數個金屬條狀物，設置於兩鄰接導電墊所圍的空間範圍內，該密封環之寬度不大於該些導電墊之寬度，每一該金屬條狀物不同時與上述兩鄰接的導電墊電性連接，並且上述兩鄰接的導電墊不互相電性連接；其中上述兩相鄰導電墊之寬度所圍的空間外側更包括一外間隙，且上述兩相鄰導電墊之寬度所圍的空間內側更包括一內間隙，該外間隙與該內間隙所形成的彎曲通道，係大於該外間隙與該內間隙兩者之直線間距。
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