JP5324822B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5324822B2 JP5324822B2 JP2008136999A JP2008136999A JP5324822B2 JP 5324822 B2 JP5324822 B2 JP 5324822B2 JP 2008136999 A JP2008136999 A JP 2008136999A JP 2008136999 A JP2008136999 A JP 2008136999A JP 5324822 B2 JP5324822 B2 JP 5324822B2
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- Prior art keywords
- wiring
- film
- interlayer insulating
- bonding
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Description
12 シールリング
13 ボンディングパッド
22 半導体層
23 配線層
24〜31 層間絶縁膜
51 第1シール配線
52 第2シール配線
53 第3シール配線
54 第4シール配線
Claims (7)
- 複数の半導体素子を含む半導体層と、
前記半導体層上に設けられた絶縁膜と、
前記複数の半導体素子が形成された領域の外側の前記絶縁膜上に離間して設けられた複数の外部接続端子と、
前記絶縁膜を貫通して前記複数の外部接続端子と前記複数の半導体素子とを接続する複数の配線と、を含む半導体装置であって、
前記配線の各々が貫通する開口部を有して前記絶縁膜内に延在して前記複数の半導体素子の全体を囲み、かつ前記複数の外部接続端子の内側に配置された筒状ダミー配線を更に有し、
前記複数の外部接続端子のうちの隣接する前記外部接続端子にそれぞれ接続される前記配線が貫通する隣接する前記開口部は、前記筒状ダミー配線の前記絶縁膜の積層方向において互いに異なる高さに設けられていることを特徴とする半導体装置。 - 前記絶縁膜は、低誘電率膜とシリコン酸化膜とからなる少なくとも2層以上の構造であることを特徴とする請求項1記載の半導体装置。
- 前記低誘電率膜からなる層が、前記シリコン酸化膜からなる層よりも下層にあることを特徴とする請求項2に記載された半導体装置。
- 前記低誘電率膜は、比誘電率が3以下であることを特徴とする請求項2又は3記載の半導体装置。
- 前記開口部は、前記筒状ダミー配線の前記シリコン酸化膜内を延在する部分に形成されていることを特徴とする請求項2乃至4のいずれか1に記載の半導体装置。
- 前記筒状ダミー配線は銅からなることを特徴とする請求項1乃至5のいずれか1に記載の半導体装置。
- 前記筒状ダミー配線の上端の界面が、前記外部接続端子の下端の界面以下であることを特徴とする請求項1乃至6のいずれか1に記載された半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008136999A JP5324822B2 (ja) | 2008-05-26 | 2008-05-26 | 半導体装置 |
US12/470,522 US8513778B2 (en) | 2008-05-26 | 2009-05-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008136999A JP5324822B2 (ja) | 2008-05-26 | 2008-05-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009283858A JP2009283858A (ja) | 2009-12-03 |
JP5324822B2 true JP5324822B2 (ja) | 2013-10-23 |
Family
ID=41430368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008136999A Active JP5324822B2 (ja) | 2008-05-26 | 2008-05-26 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8513778B2 (ja) |
JP (1) | JP5324822B2 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8624346B2 (en) | 2005-10-11 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Exclusion zone for stress-sensitive circuit design |
US8125052B2 (en) * | 2007-05-14 | 2012-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structure with improved cracking protection |
US8643147B2 (en) * | 2007-11-01 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal ring structure with improved cracking protection and reduced problems |
US8334582B2 (en) | 2008-06-26 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protective seal ring for preventing die-saw induced stress |
US7906836B2 (en) * | 2008-11-14 | 2011-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat spreader structures in scribe lines |
US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) * | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8791549B2 (en) | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
TWI482253B (zh) * | 2009-12-28 | 2015-04-21 | Xintec Inc | 晶片封裝體 |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
CN102214614B (zh) * | 2010-04-01 | 2013-06-12 | 精材科技股份有限公司 | 芯片封装体 |
US8946877B2 (en) * | 2010-09-29 | 2015-02-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor package including cap |
JP5595977B2 (ja) * | 2011-05-27 | 2014-09-24 | 株式会社東芝 | 半導体記憶装置、その製造方法及びコンタクト構造の形成方法 |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
US20130087925A1 (en) * | 2011-10-05 | 2013-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Structures of Integrated Circuits |
JP6128787B2 (ja) * | 2012-09-28 | 2017-05-17 | キヤノン株式会社 | 半導体装置 |
JP6093556B2 (ja) * | 2012-11-13 | 2017-03-08 | 富士通株式会社 | 半導体装置および半導体集積回路装置、電子装置 |
JP6133611B2 (ja) * | 2013-02-06 | 2017-05-24 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
US9620460B2 (en) | 2014-07-02 | 2017-04-11 | Samsung Electronics Co., Ltd. | Semiconductor chip, semiconductor package and fabricating method thereof |
US9812389B2 (en) * | 2015-10-01 | 2017-11-07 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Isolation device |
JP6706520B2 (ja) * | 2016-03-24 | 2020-06-10 | シナプティクス・ジャパン合同会社 | 半導体集積回路チップ及び半導体集積回路ウェーハ |
DE102016125686A1 (de) * | 2016-12-23 | 2018-06-28 | Infineon Technologies Ag | Halbleiteranordnung mit einer dichtstruktur |
US10804184B2 (en) * | 2018-11-30 | 2020-10-13 | Nanya Technology Corporation | Semiconductor device and method of manufacturing the same |
CN117293091A (zh) * | 2021-09-06 | 2023-12-26 | 长江存储科技有限责任公司 | 半导体结构 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003037178A (ja) * | 2001-07-25 | 2003-02-07 | Nec Corp | 半導体集積回路装置 |
JP4502173B2 (ja) * | 2003-02-03 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP3778445B2 (ja) * | 2003-03-27 | 2006-05-24 | 富士通株式会社 | 半導体装置 |
JP2005142553A (ja) | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
US7049701B2 (en) | 2003-10-15 | 2006-05-23 | Kabushiki Kaisha Toshiba | Semiconductor device using insulating film of low dielectric constant as interlayer insulating film |
JP2005142262A (ja) * | 2003-11-05 | 2005-06-02 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP3962402B2 (ja) | 2003-11-10 | 2007-08-22 | 松下電器産業株式会社 | 半導体装置 |
US7453128B2 (en) | 2003-11-10 | 2008-11-18 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
JP4659355B2 (ja) * | 2003-12-11 | 2011-03-30 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
JP4636839B2 (ja) * | 2004-09-24 | 2011-02-23 | パナソニック株式会社 | 電子デバイス |
JP2006140404A (ja) * | 2004-11-15 | 2006-06-01 | Renesas Technology Corp | 半導体装置 |
JP2006324265A (ja) * | 2005-05-17 | 2006-11-30 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US7482675B2 (en) * | 2005-06-24 | 2009-01-27 | International Business Machines Corporation | Probing pads in kerf area for wafer testing |
JP2007059449A (ja) * | 2005-08-22 | 2007-03-08 | Fujitsu Ltd | 半導体装置 |
WO2007083366A1 (ja) * | 2006-01-18 | 2007-07-26 | Fujitsu Limited | 半導体装置、半導体ウエハ構造、及び半導体ウエハ構造の製造方法 |
JP2007335429A (ja) * | 2006-06-12 | 2007-12-27 | Toshiba Corp | 半導体装置 |
US7622364B2 (en) * | 2006-08-18 | 2009-11-24 | International Business Machines Corporation | Bond pad for wafer and package for CMOS imager |
JP4642908B2 (ja) * | 2008-03-11 | 2011-03-02 | パナソニック株式会社 | 半導体集積回路装置 |
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2008
- 2008-05-26 JP JP2008136999A patent/JP5324822B2/ja active Active
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2009
- 2009-05-22 US US12/470,522 patent/US8513778B2/en active Active
Also Published As
Publication number | Publication date |
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JP2009283858A (ja) | 2009-12-03 |
US8513778B2 (en) | 2013-08-20 |
US20090315184A1 (en) | 2009-12-24 |
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