JP5622433B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5622433B2 JP5622433B2 JP2010103362A JP2010103362A JP5622433B2 JP 5622433 B2 JP5622433 B2 JP 5622433B2 JP 2010103362 A JP2010103362 A JP 2010103362A JP 2010103362 A JP2010103362 A JP 2010103362A JP 5622433 B2 JP5622433 B2 JP 5622433B2
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Description
本実施の形態1による半導体装置を図1および図2を用いて以下に説明する。図1は半導体装置の要部断面図、図2は半導体装置の要部平面図である。
前述した実施の形態1では、ガードリングGRの周りを囲むように形成されたスリットSLの内壁(側面と底面)を第2パッシベーション膜32により覆うことにより、水分がスリットSLを介して素子形成領域に収入することを防止した。また、ボンディングパッドBPに用いる第6層目の配線M6の上面が露出するように形成された開口部31の側面を第2パッシベーション膜32により覆い、TiN膜28の露出を防ぐことにより、酸化によるTiN膜28の体積膨張に起因した第1パッシベーション膜30におけるクラックの発生を防止して、水分がクラックを介して素子形成領域に侵入することを防止した。
本実施の形態3による半導体装置について図16および図17を用いて説明する。図16は素子形成領域およびスリット領域の一例を説明する上層配線の要部断面図、図17は素子形成領域およびスリット領域の他の例を説明する上層配線の要部断面図である。
2 分離部
3 pウェル
4 nウェル
5 ゲート絶縁膜
6n,6p ゲート電極
7 サイドウォール
8 n型半導体領域
9 p型半導体領域
10 層間絶縁膜
10a 下層絶縁膜
10b 上層絶縁膜
11 接続孔
12 プラグ
13 ストッパ絶縁膜
14 配線形成用絶縁膜
15 配線溝
16,16a ストッパ絶縁膜
17,17a 層間絶縁膜
18,18a 接続孔
19,19a 配線形成用絶縁膜(第1絶縁膜)
20,20a キャップ絶縁膜
21,21a 配線溝
22 バリア絶縁膜(第2絶縁膜)
23 層間絶縁膜(第3絶縁膜)
24 接続孔
25 プラグ
26 Al(アルミニウム)膜
27,28 TiN(窒化チタン)膜
29 接着用絶縁膜
30 第1パッシベーション膜
30a 酸化シリコン膜
30A 下層パッシベーション膜(下層膜)
30b 窒化シリコン膜
30B 上層パッシベーション膜(上層膜)
31 開口部
32 第2パッシベーション膜
51 最上層の配線
52 Cu(銅)配線
100 スクライブライン
BP ボンディングパッド
DA 素子形成領域
GR ガードリング(シーリング)
M1 第1層目の配線
M2 第2層目の配線
M3 第3層目の配線
M4 第4層目の配線
M5 第5層目の配線
M6 第6層目の配線
RP1,RP2,RP3,RP4 レジストパターン
SC 半導体チップ
SL スリット(溝部、溝パターン)
Claims (12)
- 半導体基板の主面上に形成された第1絶縁膜と、
前記第1絶縁膜に形成された配線溝と、
前記配線溝の内部に形成された、銅を主導電材料とする第1導体膜からなる第1配線と、
前記第1配線および前記第1絶縁膜の上に形成された第1厚さの炭窒化シリコン膜と、
前記炭窒化シリコン膜の上に形成された、前記第1厚さよりも厚い第2厚さの第3絶縁膜と、
前記炭窒化シリコン膜および第3絶縁膜に形成され、前記第1配線に接続される、前記第1導体膜とは異なる主導電材料からなるプラグと、
前記プラグに接続して形成され、前記第1導体膜とは異なる主導電材料からなる第2配線と、
前記第2配線および前記第3絶縁膜を覆うように形成された第1パッシベーション膜と、
前記第2配線の上面を露出する前記第1パッシベーション膜に形成された開口部と、
素子形成領域とダイシング領域との間に、前記第3絶縁膜および前記第1パッシベーション膜に形成された溝部と、
前記開口部の側面を覆うように形成された第2パッシベーション膜と、
を有する半導体装置であって、
前記溝部の底部と前記炭窒化シリコン膜との間に前記第3絶縁膜をはさむことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2パッシベーション膜は、前記溝部の側面および底面を覆うように形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第3絶縁膜は酸化シリコン膜であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2パッシベーション膜は窒化シリコン膜であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜の比誘電率は、SiO2の比誘電率よりも低いことを特徴とする半導体装置。 - 半導体基板の主面上に形成された第1絶縁膜と、
前記第1絶縁膜に形成された配線溝と、
前記配線溝の内部に形成された、銅を主導電材料とする第1導体膜からなる第1配線と、
前記第1配線および前記第1絶縁膜の上に形成された第1厚さの炭窒化シリコン膜と、
前記炭窒化シリコン膜の上に形成された、前記第1厚さよりも厚い第2厚さの第3絶縁膜と、
前記炭窒化シリコン膜および第3絶縁膜に形成され、前記第1配線に接続される、前記第1導体膜とは異なる主導電材料からなるプラグと、
前記プラグに接続して形成され、前記第1導体膜とは異なる主導電材料からなる第2配線と、
前記第2配線および前記第3絶縁膜を覆うように形成された、下層膜と上層膜との積層構造の第1パッシベーション膜と、
前記第2配線の上面を露出する前記第1パッシベーション膜に形成された開口部と、
素子形成領域とダイシング領域との間に、前記第3絶縁膜および前記第1パッシベーション膜に形成された溝部と、
前記開口部の側面および前記溝部の側面および底面を覆うように形成された第2パッシベーション膜と、
を有する半導体装置であって、
前記第1パッシベーション膜を構成する前記上層膜および前記第2パッシベーション膜は、窒化シリコン膜であり、
前記溝部の底部と前記炭窒化シリコン膜との間に前記第3絶縁膜をはさむことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第3絶縁膜は酸化シリコン膜であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1絶縁膜の比誘電率は、SiO2の比誘電率よりも低いことを特徴とする半導体装置。 - (a)半導体基板の主面上に第1絶縁膜を形成する工程と、
(b)前記第1絶縁膜に配線溝を形成し、前記配線溝の内部に、銅を主導電材料とする第1導体膜からなる第1配線を形成する工程と、
(c)前記第1配線および前記第1絶縁膜の上に、第1厚さの炭窒化シリコン膜および前記第1厚さよりも厚い第2厚さの第3絶縁膜を形成する工程と、
(d)前記第3絶縁膜および前記炭窒化シリコン膜を順次加工して、前記第1配線に達する接続孔を形成する工程と、
(e)前記接続孔の内部に、前記第1導体膜とは異なる主導電材料からなるプラグを形成する工程と、
(f)前記プラグに接続され、前記第1導体膜とは異なる主導電材料からなる第2配線を形成する工程と、
(g)前記第2配線および前記第3絶縁膜を覆うように形成された第1パッシベーション膜を形成する工程と、
(h)前記第1パッシベーション膜および前記第3絶縁膜を順次加工して、前記第2配線の上面を露出する開口部を形成し、素子形成領域とダイシング領域との間に溝部を形成する工程と、
(i)平面視における前記第1パッシベーション膜の上面、前記開口部の側面および底面、ならびに前記溝部の側面および底面に第2パッシベーション膜を形成する工程と、
(j)平面視における前記第1パッシベーション膜の上面、前記開口部の側面、ならびに前記溝部の側面および底面をレジストパターンにより覆い、前記レジストパターンにより覆われていない前記開口部の底面の前記第2パッシベーション膜をエッチングする工程と、
を有し、
前記工程(h)においては、前記溝部の底部が、前記第3絶縁膜の膜厚方向において前記炭窒化シリコン膜との間に前記第3絶縁膜を残すように、前記溝部を形成することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第3絶縁膜は酸化シリコン膜であることを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第2パッシベーション膜は窒化シリコン膜であることを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1絶縁膜の比誘電率は、SiO2の比誘電率よりも低いことを特徴とする半導体装置の製造方法。
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