JP7277248B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP7277248B2 JP7277248B2 JP2019086104A JP2019086104A JP7277248B2 JP 7277248 B2 JP7277248 B2 JP 7277248B2 JP 2019086104 A JP2019086104 A JP 2019086104A JP 2019086104 A JP2019086104 A JP 2019086104A JP 7277248 B2 JP7277248 B2 JP 7277248B2
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- semiconductor
- semiconductor layer
- insulator
- semiconductor device
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Description
本発明の第1実施形態による半導体装置の概略構成について、図1及び図2を用いて説明する。図1は、本実施形態による半導体装置の上面図である。図2は、本実施形態による半導体装置の概略断面図である。図2は、図1のA-A′線断面図である。
以上により、接合前の第1部品100が完成する。
以上により、接合前の第2部品200が完成する。
本発明の第2実施形態による半導体装置及びその製造方法について、図10乃至図16を用いて説明する。第1実施形態による半導体装置と同様の構成要素には同一の符号を付し、説明を省略し或いは簡潔にする。
以上により、接合前の第2部品200が完成する。
本発明の第3実施形態による半導体装置及びその製造方法について、図17乃至図23を用いて説明する。第1及び第2実施形態による半導体装置と同様の構成要素には同一の符号を付し、説明を省略し或いは簡潔にする。
以上により、接合前の第2部品200が完成する。
本発明は、上記実施形態に限らず種々の変形が可能である。
例えば、いずれかの実施形態の一部の構成を他の実施形態に追加した例や、他の実施形態の一部の構成と置換した例も、本発明の実施形態である。
12…スクライブ領域
14…半導体素子部
16…アライメントマーク
100…第1部品
110,210…半導体層
200…第2部品
224…半導体領域
230,232…絶縁体部
234…絶縁体部材
264…外部接続電極
274…構造体
276…開口部
300…接合面
Claims (20)
- 第1面と、前記第1面と反対の第2面と、を有する半導体層と、前記半導体層の前記第1面の側に設けられた配線構造体と、を有し、
前記半導体層に、複数の半導体素子が設けられた半導体素子部と、各々が前記第2面の側から前記半導体層を貫く複数の開口部と、が設けられた半導体装置であって、
前記第2面に沿った仮想面内において前記複数の開口部のうちの少なくとも1つの開口部を囲うように設けられ、且つ、前記半導体層の厚さをTとして、前記半導体層の前記第1面からT/2より大きくTより小さい深さに渡って設けられた絶縁体部を有し、
前記半導体層は、
前記仮想面内において前記絶縁体部に対して前記1つの開口部とは反対側に設けられた第1導電型の第1半導体領域と、
前記第2面に垂直な方向において前記絶縁体部の前記第2面の側の面から前記第2面に渡って前記半導体層に設けられた第2導電型の第2半導体領域と、を有する
ことを特徴とする半導体装置。 - 前記半導体層は、前記仮想面内において前記絶縁体部と前記1つの開口部との間に設けられた前記第1導電型の第3半導体領域を有する
ことを特徴とする請求項1記載の半導体装置。 - 前記絶縁体部は、前記1つの開口部と前記半導体素子部との間に位置する第1絶縁体部を含む
ことを特徴とする請求項1又は2記載の半導体装置。 - 前記第1絶縁体部は、前記複数の開口部のうちの前記1つの開口部とは別の開口部と、前記1つの開口部との間に位置する
ことを特徴とする請求項3記載の半導体装置。 - 前記絶縁体部は、
前記仮想面内において前記複数の開口部及び前記半導体素子部を囲うように設けられた第2絶縁体部を含み、
前記半導体層は、
前記第2絶縁体部の前記第2面の側の面から前記第2面に渡って前記半導体層に設けられた前記第2導電型の半導体領域を有する
ことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。 - 前記絶縁体部は、
前記1つの開口部と前記半導体素子部との間に位置する第1絶縁体部と、
前記半導体層の端面と前記第1絶縁体部との間に位置する第2絶縁体部と、を有し、
前記第1面からT/2の深さにおける前記第2絶縁体部の幅は、前記第1面からT/2の深さにおける前記第1絶縁体部の幅よりも広い
ことを特徴とする請求項1又は2記載の半導体装置。 - 前記半導体層の前記第1面から前記第2面に渡って設けられた絶縁体部材を更に有する
ことを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。 - 前記第1面からT/2の深さにおける前記絶縁体部材の幅は、前記第1面からT/2の深さにおける前記絶縁体部の幅よりも広い
ことを特徴とする請求項7記載の半導体装置。 - 前記絶縁体部材は、アライメントマークを構成する
ことを特徴とする請求項7又は8記載の半導体装置。 - 前記開口部の中に設けられた導電体部材を更に有する
ことを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置。 - 前記配線構造体は、前記導電体部材が接続された電極を有する
ことを特徴とする請求項10記載の半導体装置。 - 基板を更に有し、前記半導体層と前記基板との間に前記配線構造体が位置する
ことを特徴とする請求項1乃至11のいずれか1項に記載の半導体装置。 - 前記配線構造体は、前記半導体層に接続された配線を含む第1配線構造体と、前記基板に接続された配線を含む第2配線構造体とを有する
ことを特徴とする請求項12記載の半導体装置。 - 前記開口部の中に設けられた導電体部材を更に有し、
前記導電体部材が接続された電極が、前記第1配線構造体に設けられている
ことを特徴とする請求項13記載の半導体装置。 - 前記開口部の中に設けられた導電体部材を更に有し、
前記導電体部材が接続された電極が、前記第2配線構造体に設けられている
ことを特徴とする請求項13記載の半導体装置。 - 前記半導体層の前記第2面の側に設けられた光学構造体を更に有する
ことを特徴とする請求項1乃至15のいずれか1項に記載の半導体装置。 - 前記半導体層の前記第1面からT/2より小さい深さに渡って絶縁体によって構成され、前記半導体素子部に設けられた素子分離部を更に有する
ことを特徴とする請求項1乃至12のいずれか1項に記載の半導体装置。 - 前記半導体素子部には複数の光電変換素子が配列されている
ことを特徴とする請求項1乃至17のいずれか1項に記載の半導体装置。 - 第1面と前記第1面とは反対の第2面とを有する半導体基板の前記第1面の側に、第1溝と第2溝を形成する工程と、
前記第1溝の底部において前記半導体基板に不純物を導入して、第1半導体領域を形成し、前記第2溝の底部において前記半導体基板に不純物を導入して、第2半導体領域を形成する工程と、
前記第1溝に絶縁材料を埋め込むことにより第1絶縁体部を形成し、前記第2溝に絶縁材料を埋め込むことにより第2絶縁体部を形成す工程と、
前記半導体基板の前記第1面の上に、配線構造体を形成する工程と、
前記半導体基板の前記第2面の側から前記半導体基板を薄化することにより、前記半導体基板から半導体層を形成する工程と、を有し、
前記第1溝と前記第2溝を形成する工程では、前記第2溝の幅は前記第1溝の幅よりも広く、前記第2溝の深さは前記第1溝の深さよりも深く、
前記薄化する工程では、前記半導体層の前記配線構造体の側とは反対側の面に、前記第1半導体領域及び前記第2絶縁体部が露出し、
前記第1溝の深さは、前記薄化の後における前記半導体層の厚さをTとして、T/2より大きくTより小さい
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至18のいずれか1項に記載の半導体装置と、
前記半導体装置から出力される信号を処理する信号処理装置と
を有することを特徴とする機器。
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