TW201537674A - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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TW201537674A
TW201537674A TW104104374A TW104104374A TW201537674A TW 201537674 A TW201537674 A TW 201537674A TW 104104374 A TW104104374 A TW 104104374A TW 104104374 A TW104104374 A TW 104104374A TW 201537674 A TW201537674 A TW 201537674A
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metal lines
chip package
semiconductor wafer
disposed
trenches
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TW104104374A
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TWI563598B (en
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Yen-Shih Ho
Chia-Ming Cheng
Shu-Ming Chang
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Xintec Inc
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Abstract

本發明提供一種晶片封裝體，包含半導體晶片、至少一溝槽、複數條第一重佈局金屬線路、以及至少一凸起。半導體晶片具有複數個導電墊設置於該半導體晶片之上表面。溝槽自上表面朝半導體晶片之下表面延伸，溝槽配置於半導體晶片之側邊。複數條第一重佈局金屬線路設置於上表面，第一重佈局金屬線路分別與導電墊電性連接，且第一重佈局金屬線路分別延伸至溝槽內。凸起設置於溝槽內且位於相鄰第一重佈局金屬線路之間。

Description

晶片封裝體及其製造方法
本發明係關於一種封裝體及其製造方法，且特別是有關於一種晶片封裝體及其製造方法。
在各項電子產品要求多功能且外型尚須輕薄短小的需求之下，各項電子產品所對應的半導體晶片，不僅其尺寸微縮化，當中之佈線密度亦隨之提升，因此後續在製造半導體晶片封裝體的挑戰亦漸趨嚴峻。其中，晶圓級晶片封裝是半導體晶片封裝方式的一種，係指晶圓上所有晶片生產完成後，直接對整片晶圓上所有晶片進行封裝製程及測試，完成之後才切割製成單顆晶片封裝體的晶片封裝方式。在半導體晶片尺寸微縮化、佈線密度提高的情形之下，晶片封裝體在結構設計以及其製造方法上亦漸趨複雜。因此，不僅對各項在晶片封裝體製造過程中所涉及製程要求提高，導致成本增加，尚具有良率降低的風險。據此，一種更可靠、更適於量產的晶片封裝體及其製造方法，是當今晶片封裝工藝重要的研發方向之一。
本發明係提供一種晶片封裝體及其製造方法，晶片封裝體之溝槽內具有凸起，而凸起設置於相鄰各自需獨立訊 號的重佈局金屬線路之間。因此凸起可確保相鄰各自需獨立訊號重佈局金屬線路彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的現象。據此，能有效提升各自需獨立訊號重佈局金屬線路製作時，微影蝕刻製程之製程邊際，更能提高晶片封裝體的製程良率，有效降低生產成本。此外，凸起實質上係與溝槽同時製作完成，而無須增加額外光罩及其微影蝕刻製程，因此更能具有製作簡便且能有效降低生產成本之特殊功效。
本發明之一態樣係提出一種晶片封裝體，包含半導體晶片、至少一溝槽、複數條第一重佈局金屬線路、以及至少一凸起。半導體晶片具有複數個導電墊設置於該半導體晶片之上表面。溝槽自上表面朝半導體晶片之下表面延伸，溝槽配置於半導體晶片之側邊。複數條第一重佈局金屬線路設置於上表面，第一重佈局金屬線路分別與導電墊電性連接，且第一重佈局金屬線路分別延伸至溝槽內。凸起設置於溝槽內且位於相鄰第一重佈局金屬線路之間。
在本發明之一實施方式中，晶片封裝體進一步包含複數條第二重佈局金屬線路設置於上表面，半導體晶片具有複數個接地墊設置於該上表面，第二重佈局金屬線路分別與接地墊電性連接，且第二重佈局金屬線路分別延伸至溝槽內。
在本發明之一實施方式中，上述第二重佈局金屬線路於溝槽內彼此電性連接。
在本發明之一實施方式中，晶片封裝體進一步包含複數條第三重佈局金屬線路設置於上表面，第三重佈局金屬線路分別延伸至溝槽內且於溝槽內彼此電性連接。
在本發明之一實施方式中，晶片封裝體進一步包含複數個焊球設置於溝槽內且焊球分別位於第一重佈局金屬線路上。
在本發明之一實施方式中，上述焊球包含錫。
在本發明之一實施方式中，上述凸起包含矽、鍺、氧化矽、氮化矽或該等之組合。
在本發明之一實施方式中，上述凸起具有高度不高於上表面。
本發明之另一態樣係提出一種晶圓級晶片封裝體的製造方法，包含：提供半導體晶圓具有至少二半導體晶片相鄰排列，半導體晶片具有上表面及下表面，半導體晶片具有具有複數個導電墊設置於上表面；形成至少一溝槽以及複數個凸起，溝槽位於半導體晶片之間，凸起於溝槽內；全面形成金屬層覆蓋上表面、溝槽以及凸起；微影蝕刻金屬層以形成複數條第一重佈局金屬線路，第一重佈局金屬線路分別與導電墊電性連接，且第一重佈局金屬線路分別延伸至溝槽內，使溝槽內之凸起將第一重佈局金屬線路分別隔離開來。
在本發明之一實施方式中，上述形成溝槽以及凸起的步驟係由同一步驟之微影蝕刻所形成。
100‧‧‧晶片封裝體
110‧‧‧半導體晶片
111‧‧‧上表面
130‧‧‧第一重佈局金屬線路
140‧‧‧凸起
150‧‧‧第二重佈局金屬線路
112‧‧‧導電墊
113‧‧‧下表面
114‧‧‧接地墊
120‧‧‧溝槽
160‧‧‧第二重佈局金屬線路
170‧‧‧焊球
180‧‧‧焊線
本發明之上述和其他態樣、特徵及其他優點參照說明書內容並配合附加圖式得到更清楚的了解，其中：第1圖係根據本發明一實施方式晶片封裝體的局部上視示意圖。
第2圖係沿第1圖中剖線2之側視示意圖。
第3圖係根據本發明另一實施方式晶片封裝體的局部上視示意圖。
第4圖係沿第3圖中剖線4之側視示意圖。
第5圖係根據本發明另一實施方式晶片封裝體的局部上視示意圖。
第6圖係根據本發明一些實施方式晶片封裝體針對溝槽之局部側視示意圖。
為了使本揭示內容的敘述更加詳盡與完備，下文針對了本發明的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。在以下描述中，將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而，可在無此等特定細節之情況下實踐本發明之實施例。
第1圖係根據本發明一實施方式晶片封裝體100的局部上視示意圖。請參照第1圖，晶片封裝體100包含半導體晶片110、至少一溝槽120、複數條第一重佈局金屬線路130以及至少一凸起140。半導體晶片110具有複數個導電墊112設置於半導體晶片之上表面111。半導體晶片110例如可以是在矽(silicon)、鍺(germanium)或其它III-V族元素半導體晶圓基材上所製作之半導體晶片110。半導體晶片110例如可以具有電子元件(圖未繪示)位於半導體晶片110之內部，電子元件與配置於半導體晶片110之上表面111的 各導電墊112之間具有電性連接。電性連接的方式例如可以是透過位於半導體晶片110內部之內連線結構(圖未繪示)電性連接於電子元件。據此，導電墊112即作為晶片封裝體100中電子元件信號控制的輸入(input)/輸出(output)端，導電墊112的材質例如可以是鋁(aluminum)、銅(copper)或鎳(nickel)或其他合適的導電材料。在本發明中電子元件例如可以是主動元件(active element)或被動元件(passive elements)、數位電路或類比電路等積體電路的電子元件(electronic components)、微機電系統(Micro Electro Mechanical Systems,MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(physical sensor)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件、壓力感測器(pressure sensors)，但不以此為限。
第2圖係沿第1圖中剖線2之側視示意圖。請參照第2圖搭配第1圖。溝槽120自上表面111朝半導體晶片110之下表面113延伸。溝槽120配置於半導體晶片110之一側。換言之，溝槽120係配置於半導體晶片110之邊緣。如第1圖所示，在本發明之一些實施方式中，晶片封裝體100包含一個溝槽120配置半導體晶片110之一側。但本發明並不以此為限，在本發明之一些實施方式中，晶片封裝體100尚可包含兩個以上之溝槽120均配置半導體晶片110之同一側，或是包含兩個以上之溝槽120分別配置半導體晶片110之不同側的情形。溝槽120製作的方式可以是由半導體晶片110之上表面111朝半導體晶片110之下表面113，以 微影蝕刻的方式所形成。溝槽120可作為晶片封裝體100對外以焊球或焊線電性連接時，焊球或焊線之打接處。
請繼續參照第1圖搭配第2圖，複數條第一重佈局金屬線路130設置於上表面111，第一重佈局金屬線路130分別與導電墊112電性連接，且第一重佈局金屬線路130分別延伸至溝槽120內。如第1圖所示，各第一重佈局金屬線路130分別電性連接各導電墊112，因此各第一重佈局金屬線路130可視為彼此獨立之訊號線路，分別控制半導體晶片110中不同導電墊112之訊號輸入或輸出。第一重佈局金屬線路130所使用的材料可以是鋁、銅或其它合適之導電材料。第一重佈局金屬線路130製作的方式可以是先以濺鍍(sputtering)或蒸鍍(evaporation)製程先沉積導電薄膜，再將導電薄膜以微影蝕刻的方式形成具有預定重佈局線路圖案的第一重佈局金屬線路130。此外，本發明之晶片封裝體100尚可進一步包含絕緣層(圖未繪示)夾設於半導體晶片110之上表面111與第一重佈局金屬線路130之間，絕緣層所使用的材料可以是氧化矽、氮化矽、氮氧化矽或其它合適之絕緣材料，以化學氣相沉積法(chemical vapor deposition)順應地(conformally)沿著半導體晶片110之上表面111、溝槽120之側壁以及底部形成絕緣薄膜，再以微影蝕刻的方式對應導電墊112的位置形成開口以暴露出導電墊112，使接下來製作的第一重佈局金屬線路130可透過絕緣層之開口，電性連接於導電墊112。值得注意的是，如第2圖所示，凸起140設置於溝槽120內且位於相鄰第一重佈局金屬線路130之間。凸起140可確保相鄰第一重佈局金屬線路130彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的 現象。綜合上述，本發明各實施方式之晶片封裝體的製造方法包含提供半導體晶圓具有至少二半導體晶片110相鄰排列，半導體晶片具有上表面111及下表面113，半導體晶片110具有具有複數個導電墊112設置於上表面111。接著，形成至少一溝槽120以及複數個凸起140，溝槽120位於半導體晶片110之間，凸起140於溝槽120內。接著全面形成金屬層覆蓋上表面111、溝槽120以及凸起140。接著微影蝕刻金屬層以形成複數條第一重佈局金屬線路130，第一重佈局金屬線路130分別與導電墊112電性連接，且第一重佈局金屬線路130分別延伸至溝槽120內，使溝槽120內之凸起140將第一重佈局金屬線路130分別隔離開來。由此可知，第一重佈局金屬線路130之形成是在溝槽120以及凸起140製作完畢後，溝槽120內之凸起140可確保相鄰第一重佈局金屬線路130彼此之間能夠確實被隔離。據此，能有效提升第一重佈局金屬線路130製作時，微影蝕刻製程之製程邊際(process margin)，更能提高晶片封裝體100的製程良率，有效降低生產成本。在本發明之一些實施方式中，凸起140包含矽(silicon)、鍺(germanium)、氧化矽(silicon oxide)、氮化矽(silicon nitride)或該等之組合。凸起140的製作方式例如可以是與前述溝槽120於同一微影蝕刻步驟中同時形成。在本發明的一些實施方式中，形成溝槽以及凸起的步驟係由同一步驟之微影蝕刻所形成。舉例來說，半導體晶片110可以是由矽基材上所製作，如前所述，溝槽120製作的方式可以是由半導體晶片110之上表面111朝半導體晶片110之下表面113，以微影蝕刻的方式所形成，微影製程所使用的光罩除了具有對應溝槽120形成位置的圖案之外，尚 具有對應凸起140形成位置的圖案，因此溝槽120與凸起140實質上係在同一張光罩下完成曝光，而於後續顯影以及蝕刻後同時形成。換言之，凸起140實質上係與溝槽120同時製作完成，而無須增加額外之微影蝕刻，因此更能具有製作簡便且能有效降低生產成本之特殊功效。此外如第2圖所示，在本發明的一些實施方式中，凸起140具有高度H不高於上表面111。據此，凸起140除具有前述確保相鄰第一重佈局金屬線路130彼此之間被隔離，不會產生電性連接而短路的現象之外，亦不會妨礙後續焊球或焊線之製作。
再參照第1圖，在本發明的一些實施方式中，晶片封裝體100進一步包含複數條第二重佈局金屬線路150設置於上表面111，半導體晶片110具有複數個接地墊114設置於上表面111，第二重佈局金屬線路150分別與接地墊114電性連接，且第二重佈局金屬線路150分別延伸至溝槽120內。如第1圖所示，接地墊114設置於上表面111，可透過內連線結構電性連接於半導體晶片110內部電子元件之部分部件或是接地貫孔(ground via)，使其電性接地(grounding)。接地墊114例如可以是和導電墊112完全相同的材質並於相同步驟中製作，因此接地墊114材質例如可以是鋁、銅或鎳或其他合適的導電材料。如第1圖所示，接地墊114可作為半導體晶片110內部電子元件之檢測端或是其他需要電性接地的情況，藉由與接地墊114電性連接之第二重佈局金屬線路150，將電性接地之導電路徑延伸至溝槽120內。此外，隨著各式電子元件及攜帶式電子元件愈來愈普及與輕巧化，使得晶片封裝體的尺寸也日益微縮化，來因應各類積體電路製程的微小化以及多功能性整合晶片之趨 勢發展。使半導體晶片封裝體內部各元件彼此連結的密度愈來愈高，走線之間越來越緊密，彼此的耦合現象也越趨嚴重，使得訊號在傳輸時經常會有電磁干擾的問題。因此，接地墊114以及第二重佈局金屬線路150也具有藉電性接地來改善上述耦合現象之特殊功效。如第1圖以及第2圖所示，在本發明的一些實施方式中，第二重佈局金屬線路150於該溝槽120內彼此電性連接。換言之，各第二重佈局金屬線路150可在延伸至溝槽120內後匯流，而非如第一重佈局金屬線路130之間由凸起140相互隔開，據此可簡化電性接地的連接方式。
此外，又如第1圖以及第2圖所示，在本發明的一些實施方式中，晶片封裝體100進一步包含複數條第三重佈局金屬線路160設置於上表面111，第三重佈局金屬線路160分別延伸至溝槽120內且於溝槽160內彼此電性連接。如第1圖所示，各第三重佈局金屬線路160亦分別對應電性連接於各導電墊112，第三重佈局金屬線路160與第一重佈局金屬線路130之不同點在於：各第一重佈局金屬線路130可視為彼此獨立之訊號線路，分別控制半導體晶片110中不同導電墊112之訊號輸入或輸出，因此凸起140設置於溝槽120內且位於相鄰第一重佈局金屬線路130之間，以確保相鄰第一重佈局金屬線路130彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的現象；而第三重佈局金屬線路160可以是相同輸入或輸出訊號於不同導電墊112之線路，因此不須凸起140設置於相鄰第三重佈局金屬線路160之間，換言之各第三重佈局金屬線路160可於溝槽120內匯流，據此便將需要相同訊號導電墊112整合在一起，可進一步簡化訊 號輸入或輸出。
第3圖係根據本發明另一實施方式晶片封裝體200的局部上視示意圖。第4圖係沿第3圖中剖線4之側視示意圖。請參照第3圖搭配第4圖，晶片封裝體200包含半導體晶片110、溝槽120、複數條第一重佈局金屬線路130以及凸起140。其中有關半導體晶片110、溝槽120、第一重佈局金屬線路130以及凸起140的製作方式、材料以及各元件之間的相對位置與連接關係大致與前述實施方式晶片封裝體100相同，在此即不重複贅述。晶片封裝體200與前述實施方式晶片封裝體100不同之處在於，晶片封裝體200具有二溝槽120配置於半導體晶片110之同一側。如第3圖所示，一部分之第一重佈局金屬線路130延伸至左側之溝槽120內；而另一部分之第一重佈局金屬線路130延伸至右側之溝槽120內。據此，第一重佈局金屬線路130的圖案可針對半導體晶片110之上表面111不同導電墊112位置作適當的彈性調整，更可簡化第一重佈局金屬線路130圖案在設計以及製作上的難度。如第4圖所示，凸起140設置於溝槽120內且位於相鄰第一重佈局金屬線路130之間。凸起140可確保相鄰第一重佈局金屬線路130彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的現象。據此，能有效提升第一重佈局金屬線路130製作時，微影蝕刻製程之製程邊際，更能提高晶片封裝體200的製程良率，有效降低生產成本。此外，溝槽120製作的方式可以是由半導體晶片110之上表面111朝半導體晶片110之下表面113，以微影蝕刻的方式所形成，微影製程所使用的光罩除了具有對應溝槽120形成位置的圖案之外，尚具有對應凸起140形成位置 的圖案，因此溝槽120與凸起140實質上係在同一張光罩下完成曝光，而於後續顯影以及蝕刻後同時形成。換言之，凸起140實質上係與溝槽120同時製作完成，而無須增加額外之微影蝕刻，因此更能具有製作簡便且能有效降低生產成本之特殊功效。
第5圖係根據本發明另一實施方式晶片封裝體300的局部上視示意圖。請參照第5圖，晶片封裝體300包含半導體晶片110、溝槽120、複數條第一重佈局金屬線路130以及凸起140。其中有關半導體晶片110、溝槽120、第一重佈局金屬線路130以及凸起140的製作方式、材料以及各元件之間的相對位置與連接關係大致與前述實施方式晶片封裝體100相同，在此即不重複贅述。晶片封裝體300與前述實施方式晶片封裝體100不同之處在於，晶片封裝體200具有二溝槽120配置於半導體晶片110之不同側。如第5圖所示，一部分之第一重佈局金屬線路130延伸至下側之溝槽120內；而另一部分之第一重佈局金屬線路130延伸至右側之溝槽120內。與前述實施方式晶片封裝體200相似的是，第一重佈局金屬線路130的圖案亦可針對半導體晶片110之上表面111不同導電墊112位置作適當的彈性調整，更可簡化第一重佈局金屬線路130圖案在設計以及製作上的難度。此外，凸起140亦設置於溝槽120內且位於相鄰第一重佈局金屬線路130之間。凸起140可確保相鄰第一重佈局金屬線路130彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的現象。據此，能有效提升第一重佈局金屬線路130製作時，微影蝕刻製程之製程邊際，更能提高晶片封裝體200的製程良率，有效降低生產成本。此外，溝槽120製 作的方式可以是由半導體晶片110之上表面111朝半導體晶片110之下表面113，以微影蝕刻的方式所形成，微影製程所使用的光罩除了具有對應溝槽120形成位置的圖案之外，尚具有對應凸起140形成位置的圖案，因此溝槽120與凸起140實質上係在同一張光罩下完成曝光，而於後續顯影以及蝕刻後同時形成。換言之，凸起140實質上係與溝槽120同時製作完成，而無須增加額外之微影蝕刻，因此更能具有製作簡便且能有效降低生產成本之特殊功效。
第6圖係根據本發明一些實施方式晶片封裝體針對溝槽120之局部側視示意圖。在本發明的一些實施方式中，晶片封裝體進一步包含複數個焊球170設置於溝槽120內且焊球170分別位於第一重佈局金屬線路130上。因此，焊球170與第一重佈局金屬線路130電性連接。焊球170的材料例如可以是錫或其他適合於焊接的金屬或合金。在本發明的一些實施方式中，其中焊球170包含錫。焊球170作為晶片封裝體外接於印刷電路板或其他中介片(interposer)之連接橋樑，據此由印刷電路板或其他中介片的輸入/輸出的電流訊號即可透過焊球170、第一重佈局金屬線路130以及導電墊112，對晶片封裝體內的電子元件進行訊號輸入/輸出控制。然而本發明並不以此為限。在本發明另一些實施方式中，晶片封裝體亦可進一步包含焊球170以及連接於焊球170的焊線180，如此焊球170以及焊線180即作為晶片封裝體外接於印刷電路板或其他中介片之連接橋樑，據此由印刷電路板或其他中介片的輸入/輸出的電流訊號即可透過焊球170、焊線180、第一重佈局金屬線路130以及導電墊112，對晶片封裝體內的電子元件進行訊號輸入/輸出控制。此 外，本發明之晶片封裝體尚可包含封裝層覆蓋半導體晶片110之上表面111、第一重佈局金屬線路130、溝槽120以及凸起140。封裝層150所使用的材料可以是綠漆(solder mask)或其它合適之封裝材料，順應地沿著半導體晶片110之上表面111、第一重佈局金屬線路130、溝槽120以及凸起140以塗佈方式形成。
最後要強調的是，本發明所提供之晶片封裝體，於晶片封裝體之溝槽內具有凸起，而凸起設置於相鄰各自需獨立訊號的重佈局金屬線路之間。據此，凸起可確保相鄰各自需獨立訊號重佈局金屬線路彼此之間能夠確實被隔離，而不會產生彼此電性連接而短路的現象。據此，能有效提升各自需獨立訊號重佈局金屬線路製作時，微影蝕刻製程之製程邊際，更能提高晶片封裝體的製程良率，有效降低生產成本。此外，本發明所提供之晶片封裝體的製造方法，凸起實質上係與溝槽同時製作完成，而無須增加額外之微影蝕刻，因此更能具有製作簡便且能有效降低生產成本之特殊功效。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110‧‧‧半導體晶片
111‧‧‧上表面
113‧‧‧下表面
120‧‧‧溝槽
130‧‧‧第一重佈局金屬線路
140‧‧‧凸起
150‧‧‧第二重佈局金屬線路
160‧‧‧第二重佈局金屬線路

Claims (10)

  1. 一種晶片封裝體，包含：一半導體晶片，具有複數個導電墊設置於該半導體晶片之一上表面；至少一溝槽自該上表面朝該半導體晶片之一下表面延伸，該溝槽配置於該半導體晶片之一側邊；複數條第一重佈局金屬線路設置於該上表面，該些第一重佈局金屬線路分別與該些導電墊電性連接，且該些第一重佈局金屬線路分別延伸至該溝槽內；以及至少一凸起設置於該溝槽內且位於相鄰第一重佈局金屬線路之間。
  2. 如請求項1所述之晶片封裝體，進一步包含複數條第二重佈局金屬線路設置於該上表面，該半導體晶片具有複數個接地墊設置於該上表面，該些第二重佈局金屬線路分別與該些接地墊電性連接，且該些第二重佈局金屬線路分別延伸至該溝槽內。
  3. 如請求項2所述之晶片封裝體，其中該些第二重佈局金屬線路於該溝槽內彼此電性連接。
  4. 如請求項1所述之晶片封裝體，進一步包含複數條第三重佈局金屬線路設置於該上表面，該些第三重佈局金屬線路分別延伸至該溝槽內且於該溝槽內彼此電性連接。
  5. 如請求項1所述之晶片封裝體，進一步包含複數個 焊球設置於該溝槽內且該些焊球分別位於該些第一重佈局金屬線路上。
  6. 如請求項5所述之晶片封裝體，其中該焊球包含錫。
  7. 如請求項1所述之晶片封裝體，其中該凸起包含矽、鍺、氧化矽、氮化矽或該等之組合。
  8. 如請求項1所述之晶片封裝體，其中該凸起具有一高度不高於該上表面。
  9. 一種晶片封裝體的製造方法，包含：提供一半導體晶圓具有至少二半導體晶片相鄰排列，該半導體晶片具有一上表面及一下表面，該半導體晶片具有具有複數個導電墊設置於該上表面；形成至少一溝槽以及複數個凸起，該溝槽位於該至少二半導體晶片之間，該些凸起於該溝槽內；全面形成一金屬層覆蓋該上表面、該溝槽以及該些凸起；微影蝕刻該金屬層以形成複數條第一重佈局金屬線路，該些第一重佈局金屬線路分別與該些導電墊電性連接，且該些第一重佈局金屬線路分別延伸至該溝槽內，使該溝槽內之該些凸起將該些第一重佈局金屬線路分別隔離開來。
  10. 如請求項9所述之晶片封裝體的製造方法，其中形成該溝槽以及該些凸起的步驟係由同一步驟之微影蝕刻所 形成。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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