CN104934397A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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CN104934397A
CN104934397A CN201510087272.4A CN201510087272A CN104934397A CN 104934397 A CN104934397 A CN 104934397A CN 201510087272 A CN201510087272 A CN 201510087272A CN 104934397 A CN104934397 A CN 104934397A
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groove
metallic circuit
rerouting office
encapsulation body
semiconductor wafer
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CN104934397B (zh
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何彦仕
郑家明
张恕铭
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其制造方法。该晶片封装体包含半导体晶片、至少一沟槽、多条第一重布局金属线路以及至少一凸起。半导体晶片具有设置于该半导体晶片的上表面的多个导电垫。沟槽自上表面朝半导体晶片的下表面延伸，且配置于半导体晶片的侧边。多条第一重布局金属线路设置于上表面，所述第一重布局金属线路分别与导电垫电性连接，且分别延伸至沟槽内。凸起设置于沟槽内且位于相邻的第一重布局金属线路之间。本发明能提高晶片封装体的制程良率，并有效降低生产成本。

Description

晶片封装体及其制造方法
技术领域
本发明关于一种封装体及其制造方法，且特别是有关于一种晶片封装体及其制造方法。
背景技术
在各项电子产品要求多功能且外型尚须轻薄短小的需求之下，各项电子产品所对应的半导体晶片，不仅其尺寸微缩化，其中的布线密度亦随之提升，因此后续在制造半导体晶片封装体的挑战亦渐趋严峻。其中，晶圆级晶片封装是半导体晶片封装方式的一种，是指晶圆上所有晶片生产完成后，直接对整片晶圆上所有晶片进行封装制程及测试，完成之后才切割制成单颗晶片封装体的晶片封装方式。在半导体晶片尺寸微缩化、布线密度提高的情形之下，晶片封装体在结构设计以及其制造方法上亦渐趋复杂。因此，不仅对各项在晶片封装体制造过程中所涉及制程要求提高，导致成本增加，尚具有良率降低的风险。据此，一种更可靠、更适于量产的晶片封装体及其制造方法，是当今晶片封装工艺重要的研发方向之一。
发明内容
本发明提供一种晶片封装体及其制造方法，晶片封装体的沟槽内具有凸起，而凸起设置于相邻各自需独立信号的重布局金属线路之间。因此凸起可确保相邻各自需独立信号重布局金属线路彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象。据此，能有效提升各自需独立信号重布局金属线路制作时，微影蚀刻制程的制程边际，更能提高晶片封装体的制程良率，有效降低生产成本。此外，凸起实质上与沟槽同时制作完成，而无须增加额外光罩及其微影蚀刻制程，因此更能具有制作简便且能有效降低生产成本的特殊功效。
本发明提出一种晶片封装体，包含半导体晶片、至少一沟槽、多条第一重布局金属线路、以及至少一凸起。半导体晶片具有设置于该半导体晶片的上表面的多个导电垫。沟槽自上表面朝半导体晶片的下表面延伸，沟槽配置于半导体晶片的侧边。多条第一重布局金属线路设置于上表面，所述第一重布局金属线路分别与导电垫电性连接，且所述第一重布局金属线路分别延伸至沟槽内。凸起设置于沟槽内且位于相邻第一重布局金属线路之间。
在本发明的一实施方式中，晶片封装体进一步包含设置于上表面的多条第二重布局金属线路，半导体晶片具有设置于该上表面的多个接地垫，第二重布局金属线路分别与接地垫电性连接，且第二重布局金属线路分别延伸至沟槽内。
在本发明的一实施方式中，上述第二重布局金属线路于沟槽内彼此电性连接。
在本发明的一实施方式中，晶片封装体进一步包含设置于上表面的多条第三重布局金属线路，第三重布局金属线路分别延伸至沟槽内且于沟槽内彼此电性连接。
在本发明的一实施方式中，晶片封装体进一步包含设置于沟槽内的多个焊球，焊球分别位于第一重布局金属线路上。
在本发明的一实施方式中，上述焊球包含锡。
在本发明的一实施方式中，上述凸起包含硅、锗、氧化硅、氮化硅或前述的组合。
在本发明的一实施方式中，上述凸起的高度不高于上表面。
本发明另提出一种晶圆级晶片封装体的制造方法，包含：提供具有至少二半导体晶片相邻排列的半导体晶圆，半导体晶片具有上表面及下表面，且具有设置于上表面的多个导电垫；形成至少一沟槽以及多个凸起，沟槽位于半导体晶片之间，凸起位于沟槽内；全面形成金属层以覆盖上表面、沟槽以及凸起；微影蚀刻金属层以形成多条第一重布局金属线路，第一重布局金属线路分别与导电垫电性连接，且第一重布局金属线路分别延伸至沟槽内，使沟槽内的凸起将第一重布局金属线路分别隔离开来。
在本发明的一实施方式中，上述形成沟槽以及凸起的步骤由同一步骤的微影蚀刻所形成。
附图说明
本发明的上述和其他态样、特征及其他优点参照说明书内容并配合附加图式得到更清楚的了解，其中：
图1是根据本发明一实施方式晶片封装体的局部俯视示意图。
图2是沿图1中剖线2的侧视示意图。
图3是根据本发明另一实施方式晶片封装体的局部俯视示意图。
图4是沿图3中剖线4的侧视示意图。
图5是根据本发明另一实施方式晶片封装体的局部俯视示意图。
图6是根据本发明一些实施方式晶片封装体针对沟槽的局部侧视示意图。
其中，附图中符号的简单说明如下：
100：晶片封装体  130：第一重布局金属线路
110：半导体晶片  140：凸起
111：上表面      150：第二重布局金属线路
112：导电垫      160：第二重布局金属线路
113：下表面      170：焊球
114：接地垫      180：焊线
120：沟槽。
具体实施方式
为了使本揭示内容的叙述更加详尽与完备，下文针对了本发明的实施态样与具体实施例提出了说明性的描述；但这并非实施或运用本发明具体实施例的唯一形式。以下所揭露的各实施例，在有益的情形下可相互组合或取代，也可在一实施例中附加其他的实施例，而无须进一步的记载或说明。在以下描述中，将详细叙述许多特定细节以使读者能够充分理解以下的实施例。然而，可在无此等特定细节的情况下实践本发明的实施例。
图1是根据本发明一实施方式晶片封装体100的局部俯视示意图。请参照图1，晶片封装体100包含半导体晶片110、至少一沟槽120、多条第一重布局金属线路130以及至少一凸起140。半导体晶片110具有多个导电垫112设置于半导体晶片的上表面111。半导体晶片110例如可以是在硅(silicon)、锗(germanium)或其它III-V族元素半导体晶圆基材上所制作的半导体晶片110。半导体晶片110例如可以具有电子元件(图未绘示)位于半导体晶片110的内部，电子元件与配置于半导体晶片110的上表面111的各导电垫112之间具有电性连接。电性连接的方式例如可以是通过位于半导体晶片110内部之内连线结构(图未绘示)电性连接于电子元件。据此，导电垫112即作为晶片封装体100中电子元件信号控制的输入(input)/输出(output)端，导电垫112的材质例如可以是铝(aluminum)、铜(copper)或镍(nickel)或其他合适的导电材料。在本发明中电子元件例如可以是有源元件(active element)或无源元件(passiveelements)、数字电路或模拟电路等集成电路的电子元件(electroniccomponents)、微机电系统(Micro Electro Mechanical Systems,MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)，但不以此为限。
图2是沿图1中剖线2的侧视示意图。请参照图2搭配图1。沟槽120自上表面111朝半导体晶片110的下表面113延伸。沟槽120配置于半导体晶片110的一侧。换言之，沟槽120配置于半导体晶片110的边缘。如图1所示，在本发明的一些实施方式中，晶片封装体100包含一个沟槽120配置半导体晶片110是一侧。但本发明并不以此为限，在本发明的一些实施方式中，晶片封装体100尚可包含两个以上的沟槽120均配置半导体晶片110的同一侧，或是包含两个以上的沟槽120分别配置半导体晶片110的不同侧的情形。沟槽120制作的方式可以是由半导体晶片110的上表面111朝半导体晶片110的下表面113，以微影蚀刻的方式所形成。沟槽120可作为晶片封装体100对外以焊球或焊线电性连接时，焊球或焊线的打接处。
请继续参照图1搭配图2，多条第一重布局金属线路130设置于上表面111，第一重布局金属线路130分别与导电垫112电性连接，且第一重布局金属线路130分别延伸至沟槽120内。如图1所示，各第一重布局金属线路130分别电性连接各导电垫112，因此各第一重布局金属线路130可视为彼此独立的信号线路，分别控制半导体晶片110中不同导电垫112的信号输入或输出。第一重布局金属线路130所使用的材料可以是铝、铜或其它合适的导电材料。第一重布局金属线路130制作的方式可以是先以溅镀(sputtering)或蒸镀(evaporation)制程先沉积导电薄膜，再将导电薄膜以微影蚀刻的方式形成具有预定重布局线路图案的第一重布局金属线路130。此外，本发明的晶片封装体100尚可进一步包含绝缘层(图未绘示)夹设于半导体晶片110的上表面111与第一重布局金属线路130之间，绝缘层所使用的材料可以是氧化硅、氮化硅、氮氧化硅或其它合适的绝缘材料，以化学气相沉积法(chemical vapordeposition)顺应地(conformally)沿着半导体晶片110的上表面111、沟槽120的侧壁以及底部形成绝缘薄膜，再以微影蚀刻的方式对应导电垫112的位置形成开口以暴露出导电垫112，使接下来制作的第一重布局金属线路130可通过绝缘层的开口，电性连接于导电垫112。值得注意的是，如图2所示，凸起140设置于沟槽120内且位于相邻第一重布局金属线路130之间。凸起140可确保相邻第一重布局金属线路130彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象。综合上述，本发明各实施方式的晶片封装体的制造方法包含提供半导体晶圆具有至少二半导体晶片110相邻排列，半导体晶片具有上表面111及下表面113，半导体晶片110具有具有多个导电垫112设置于上表面111。接着，形成至少一沟槽120以及多个凸起140，沟槽120位于半导体晶片110之间，凸起140于沟槽120内。接着全面形成金属层覆盖上表面111、沟槽120以及凸起140。接着微影蚀刻金属层以形成多条第一重布局金属线路130，第一重布局金属线路130分别与导电垫112电性连接，且第一重布局金属线路130分别延伸至沟槽120内，使沟槽120内的凸起140将第一重布局金属线路130分别隔离开来。由此可知，第一重布局金属线路130的形成是在沟槽120以及凸起140制作完毕后，沟槽120内的凸起140可确保相邻第一重布局金属线路130彼此之间能够确实被隔离。据此，能有效提升第一重布局金属线路130制作时，微影蚀刻制程的制程边际(process margin)，更能提高晶片封装体100的制程良率，有效降低生产成本。在本发明的一些实施方式中，凸起140包含硅(silicon)、锗(germanium)、氧化硅(silicon oxide)、氮化硅(siliconnitride)或所述的组合。凸起140的制作方式例如可以是与前述沟槽120于同一微影蚀刻步骤中同时形成。在本发明的一些实施方式中，形成沟槽以及凸起的步骤由同一步骤的微影蚀刻所形成。举例来说，半导体晶片110可以是由硅基材上所制作，如前所述，沟槽120制作的方式可以是由半导体晶片110的上表面111朝半导体晶片110的下表面113，以微影蚀刻的方式所形成，微影制程所使用的光罩除了具有对应沟槽120形成位置的图案之外，尚具有对应凸起140形成位置的图案，因此沟槽120与凸起140实质上在同一张光罩下完成曝光，而于后续显影以及蚀刻后同时形成。换言之，凸起140实质上与沟槽120同时制作完成，而无须增加额外的微影蚀刻，因此更能具有制作简便且能有效降低生产成本的特殊功效。此外如图2所示，在本发明的一些实施方式中，凸起140的高度H不高于上表面111。据此，凸起140除具有前述确保相邻第一重布局金属线路130彼此之间被隔离，不会产生电性连接而短路的现象之外，亦不会妨碍后续焊球或焊线的制作。
再参照图1，在本发明的一些实施方式中，晶片封装体100进一步包含多条第二重布局金属线路150设置于上表面111，半导体晶片110具有多个接地垫114设置于上表面111，第二重布局金属线路150分别与接地垫114电性连接，且第二重布局金属线路150分别延伸至沟槽120内。如图1所示，接地垫114设置于上表面111，可通过内连线结构电性连接于半导体晶片110内部电子元件的部分部件或是接地贯孔(ground via)，使其电性接地(grounding)。接地垫114例如可以是和导电垫112完全相同的材质并于相同步骤中制作，因此接地垫114材质例如可以是铝、铜或镍或其他合适的导电材料。如图1所示，接地垫114可作为半导体晶片110内部电子元件的检测端或是其他需要电性接地的情况，通过与接地垫114电性连接的第二重布局金属线路150，将电性接地的导电路径延伸至沟槽120内。此外，随着各式电子元件及携带式电子元件愈来愈普及与轻巧化，使得晶片封装体的尺寸也日益微缩化，来响应各类集成电路制程的微小化以及多功能性整合晶片的趋势发展。使半导体晶片封装体内部各元件彼此连结的密度愈来愈高，走线之间越来越紧密，彼此的耦合现象也越趋严重，使得信号在传输时经常会有电磁干扰的问题。因此，接地垫114以及第二重布局金属线路150也具有通过电性接地来改善上述耦合现象的特殊功效。如图1以及图2所示，在本发明的一些实施方式中，第二重布局金属线路150于该沟槽120内彼此电性连接。换言之，各第二重布局金属线路150可在延伸至沟槽120内后汇流，而非如第一重布局金属线路130之间由凸起140相互隔开，据此可简化电性接地的连接方式。
此外，又如图1以及图2所示，在本发明的一些实施方式中，晶片封装体100进一步包含多条第三重布局金属线路160设置于上表面111，第三重布局金属线路160分别延伸至沟槽120内且于沟槽160内彼此电性连接。如图1所示，各第三重布局金属线路160亦分别对应电性连接于各导电垫112，第三重布局金属线路160与第一重布局金属线路130的不同点在于：各第一重布局金属线路130可视为彼此独立的信号线路，分别控制半导体晶片110中不同导电垫112的信号输入或输出，因此凸起140设置于沟槽120内且位于相邻第一重布局金属线路130之间，以确保相邻第一重布局金属线路130彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象；而第三重布局金属线路160可以是相同输入或输出信号于不同导电垫112的线路，因此不须凸起140设置于相邻第三重布局金属线路160之间，换言之，各第三重布局金属线路160可于沟槽120内汇流，据此便将需要相同信号导电垫112整合在一起，可进一步简化信号输入或输出。
图3是根据本发明另一实施方式晶片封装体200的局部俯视示意图。图4是沿图3中剖线4的侧视示意图。请参照图3搭配图4，晶片封装体200包含半导体晶片110、沟槽120、多条第一重布局金属线路130以及凸起140。其中有关半导体晶片110、沟槽120、第一重布局金属线路130以及凸起140的制作方式、材料以及各元件之间的相对位置与连接关系大致与前述实施方式晶片封装体100相同，在此即不重复赘述。晶片封装体200与前述实施方式晶片封装体100不同之处在于，晶片封装体200具有二沟槽120配置于半导体晶片110的同一侧。如图3所示，一部分的第一重布局金属线路130延伸至左侧的沟槽120内；而另一部分的第一重布局金属线路130延伸至右侧的沟槽120内。据此，第一重布局金属线路130的图案可针对半导体晶片110的上表面111不同导电垫112位置作适当的弹性调整，更可简化第一重布局金属线路130图案在设计以及制作上的难度。如图4所示，凸起140设置于沟槽120内且位于相邻第一重布局金属线路130之间。凸起140可确保相邻第一重布局金属线路130彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象。据此，能有效提升第一重布局金属线路130制作时，微影蚀刻制程的制程边际，更能提高晶片封装体200的制程良率，有效降低生产成本。此外，沟槽120制作的方式可以是由半导体晶片110的上表面111朝半导体晶片110的下表面113，以微影蚀刻的方式所形成，微影制程所使用的光罩除了具有对应沟槽120形成位置的图案之外，尚具有对应凸起140形成位置的图案，因此沟槽120与凸起140实质上在同一张光罩下完成曝光，而于后续显影以及蚀刻后同时形成。换言之，凸起140实质上与沟槽120同时制作完成，而无须增加额外的微影蚀刻，因此更能具有制作简便且能有效降低生产成本的特殊功效。
图5是根据本发明另一实施方式晶片封装体300的局部俯视示意图。请参照图5，晶片封装体300包含半导体晶片110、沟槽120、多条第一重布局金属线路130以及凸起140。其中有关半导体晶片110、沟槽120、第一重布局金属线路130以及凸起140的制作方式、材料以及各元件之间的相对位置与连接关系大致与前述实施方式晶片封装体100相同，在此即不重复赘述。晶片封装体300与前述实施方式晶片封装体100不同之处在于，晶片封装体200具有二沟槽120配置于半导体晶片110的不同侧。如图5所示，一部分的第一重布局金属线路130延伸至下侧的沟槽120内；而另一部分的第一重布局金属线路130延伸至右侧的沟槽120内。与前述实施方式晶片封装体200相似的是，第一重布局金属线路130的图案亦可针对半导体晶片110的上表面111不同导电垫112位置作适当的弹性调整，更可简化第一重布局金属线路130图案在设计以及制作上的难度。此外，凸起140亦设置于沟槽120内且位于相邻第一重布局金属线路130之间。凸起140可确保相邻第一重布局金属线路130彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象。据此，能有效提升第一重布局金属线路130制作时，微影蚀刻制程的制程边际，更能提高晶片封装体200的制程良率，有效降低生产成本。此外，沟槽120制作的方式可以是由半导体晶片110的上表面111朝半导体晶片110的下表面113，以微影蚀刻的方式所形成，微影制程所使用的光罩除了具有对应沟槽120形成位置的图案之外，尚具有对应凸起140形成位置的图案，因此沟槽120与凸起140实质上在同一张光罩下完成曝光，而于后续显影以及蚀刻后同时形成。换言之，凸起140实质上与沟槽120同时制作完成，而无须增加额外的微影蚀刻，因此更能具有制作简便且能有效降低生产成本的特殊功效。
图6是根据本发明一些实施方式晶片封装体针对沟槽120的局部侧视示意图。在本发明的一些实施方式中，晶片封装体进一步包含多个焊球170设置于沟槽120内且焊球170分别位于第一重布局金属线路130上。因此，焊球170与第一重布局金属线路130电性连接。焊球170的材料例如可以是锡或其他适合于焊接的金属或合金。在本发明的一些实施方式中，其中焊球170包含锡。焊球170作为晶片封装体外接于印刷电路板或其他中介片(interposer)的连接桥梁，据此由印刷电路板或其他中介片的输入/输出的电流信号即可通过焊球170、第一重布局金属线路130以及导电垫112，对晶片封装体内的电子元件进行信号输入/输出控制。然而本发明并不以此为限。在本发明另一些实施方式中，晶片封装体亦可进一步包含焊球170以及连接于焊球170的焊线180，如此焊球170以及焊线180即作为晶片封装体外接于印刷电路板或其他中介片的连接桥梁，据此由印刷电路板或其他中介片的输入/输出的电流信号即可通过焊球170、焊线180、第一重布局金属线路130以及导电垫112，对晶片封装体内的电子元件进行信号输入/输出控制。此外，本发明的晶片封装体尚可包含封装层覆盖半导体晶片110的上表面111、第一重布局金属线路130、沟槽120以及凸起140。封装层所使用的材料可以是绿漆(solder mask)或其它合适的封装材料，顺应地沿着半导体晶片110的上表面111、第一重布局金属线路130、沟槽120以及凸起140以涂布方式形成。
最后要强调的是，本发明所提供的晶片封装体，于晶片封装体的沟槽内具有凸起，而凸起设置于相邻各自需独立信号的重布局金属线路之间。据此，凸起可确保相邻各自需独立信号重布局金属线路彼此之间能够确实被隔离，而不会产生彼此电性连接而短路的现象。据此，能有效提升各自需独立信号重布局金属线路制作时，微影蚀刻制程的制程边际，更能提高晶片封装体的制程良率，有效降低生产成本。此外，本发明所提供的晶片封装体的制造方法，凸起实质上与沟槽同时制作完成，而无须增加额外的微影蚀刻，因此更能具有制作简便且能有效降低生产成本的特殊功效。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (10)

1.一种晶片封装体，其特征在于，包含：
一半导体晶片，具有设置于该半导体晶片的一上表面的多个导电垫；
至少一沟槽，自该上表面朝该半导体晶片的一下表面延伸，该沟槽配置于该半导体晶片的一侧边；
多条第一重布局金属线路，设置于该上表面，所述第一重布局金属线路分别与所述导电垫电性连接，且所述第一重布局金属线路分别延伸至该沟槽内；以及
至少一凸起，设置于该沟槽内且位于相邻的第一重布局金属线路之间。
2.根据权利要求1所述的晶片封装体，其特征在于，进一步包含设置于该上表面的多条第二重布局金属线路，该半导体晶片具有设置于该上表面的多个接地垫，所述第二重布局金属线路分别与所述接地垫电性连接，且所述第二重布局金属线路分别延伸至该沟槽内。
3.根据权利要求2所述的晶片封装体，其特征在于，所述第二重布局金属线路于该沟槽内彼此电性连接。
4.根据权利要求1所述的晶片封装体，其特征在于，进一步包含设置于该上表面的多条第三重布局金属线路，所述第三重布局金属线路分别延伸至该沟槽内且于该沟槽内彼此电性连接。
5.根据权利要求1所述的晶片封装体，其特征在于，进一步包含设置于该沟槽内的多个焊球，所述焊球分别位于所述第一重布局金属线路上。
6.根据权利要求5所述的晶片封装体，其特征在于，该焊球包含锡。
7.根据权利要求1所述的晶片封装体，其特征在于，该凸起包含硅、锗、氧化硅、氮化硅或前述的组合。
8.根据权利要求1所述的晶片封装体，其特征在于，该凸起的高度不高于该上表面。
9.一种晶片封装体的制造方法，其特征在于，包含：
提供具有至少二半导体晶片相邻排列的一半导体晶圆，该半导体晶片具有一上表面及一下表面，且具有设置于该上表面的多个导电垫；
形成至少一沟槽以及多个凸起，该沟槽位于该至少二半导体晶片之间，所述凸起位于该沟槽内；
全面形成一金属层以覆盖该上表面、该沟槽以及所述凸起；以及
微影蚀刻该金属层以形成多条第一重布局金属线路，所述第一重布局金属线路分别与所述导电垫电性连接，且所述第一重布局金属线路分别延伸至该沟槽内，使该沟槽内的所述凸起将所述第一重布局金属线路分别隔离开来。
10.根据权利要求9所述的晶片封装体的制造方法，其特征在于，形成该沟槽以及所述凸起的步骤由同一步骤的微影蚀刻所形成。
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