TWI674649B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI674649B
TWI674649B TW104138318A TW104138318A TWI674649B TW I674649 B TWI674649 B TW I674649B TW 104138318 A TW104138318 A TW 104138318A TW 104138318 A TW104138318 A TW 104138318A TW I674649 B TWI674649 B TW I674649B
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Taiwan
Prior art keywords
layer
conductive
redistribution
insulating layer
chip package
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TW104138318A
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English (en)
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TW201719805A (zh
Inventor
何彥仕
林佳昇
李柏漢
孫唯倫
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精材科技股份有限公司
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Priority to TW104138318A priority Critical patent/TWI674649B/zh
Priority to US15/351,309 priority patent/US20170148752A1/en
Publication of TW201719805A publication Critical patent/TW201719805A/zh
Application granted granted Critical
Publication of TWI674649B publication Critical patent/TWI674649B/zh

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Abstract

一種晶片封裝體包含基板、絕緣層、重佈線層、阻隔層、第一導電層、第二導電層與導電結構。絕緣層位於基板上。重佈線層位於絕緣層上。阻隔層位於絕緣層與重佈線層上。阻隔層具有開口、圍繞開口的壁面與背對絕緣層的表面。部分的重佈線層由開口裸露。第一導電層位於開口中的重佈線層上，且延伸至阻隔層的壁面與表面。第二導電層覆蓋第一導電層。導電結構位於第二導電層上且凸出阻隔層。

Description

晶片封裝體及其製造方法
本案是有關於一種晶片封裝體及一種晶片封裝體的製造方法。
一般而言，晶片封裝體的底面具有接點，用以電性連接電路板。舉例來說，導電凸塊(bump)或球閘陣列(Ball Grid Array；BGA)的錫球(solder ball)均可作為晶片封裝體的接點。
在製作習知的晶片封裝體時，可在矽基板的底面依序形成絕緣層、重佈線層(Redistribution Layer；RDL)、化鍍鎳金層(Electroless Nickel/Immersion Gold；ENIG)、防焊層(solder mask)與錫球(solder ball)。在後續的檢驗中，會對晶片封裝體的錫球作可靠度測試(Ball Level Reliability Test；BLRT)。此測試是以熱衝擊(thermal shock)的方式將晶片封裝體置於-40℃至85℃的環境中，測試錫球在重佈線層上的穩固性。
錫球位於防焊層經圖案化後的開口中，並電性連接開口中的化鍍鎳金層與重佈線層。這樣的設計，錫球與化鍍 鎳金層的接觸面積難以提升，使錫球容易經熱衝擊而從化鍍鎳金層脫落。此外，重佈線層與化鍍鎳金層的厚度薄，因此錫球與絕緣層之間的距離近，使錫球容易經熱衝擊而與絕緣層直接接觸。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式，一種晶片封裝體包含基板、絕緣層、重佈線層、阻隔層、第一導電層、第二導電層與導電結構。絕緣層位於基板上。重佈線層位於絕緣層上。阻隔層位於絕緣層與重佈線層上。阻隔層具有開口、圍繞開口的壁面與背對絕緣層的表面。部分的重佈線層由開口裸露。第一導電層位於開口中的重佈線層上，且延伸至阻隔層的壁面與表面。第二導電層覆蓋第一導電層。導電結構位於第二導電層上且凸出阻隔層。
本發明之另一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式，一種晶片封裝體的製造方法包含下列步驟。形成絕緣層於基板上。形成重佈線層於絕緣層上。形成圖案化的阻隔層於絕緣層與重佈線層上，使部分的重佈線層由阻隔層的開口裸露。形成第一導電層於開口中的重佈線層上、阻隔層圍繞開口的壁面上與阻隔層背對絕緣層的表面上。形成第二導電層以覆蓋第一導電層。形成導電結構於第二導電層上。
在本發明上述實施方式中，由於第一導電層位於阻隔層開口中的重佈線層上，且第一導電層延伸至阻隔層圍繞開口的壁面與阻隔層背對絕緣層的表面，因此待第二導電層覆蓋第一導電層後，第二導電層也會沿阻隔層開口中的第一導電層、阻隔層壁面上的第一導電層與阻隔層表面上的第一導電層設置。如此一來，導電結構可設置在第二導電層上，使得導電結構與第二導電層的接觸面積得以提升，導電結構不易經熱衝擊而從第二導電層脫落。
本發明之又一技術態樣為一種晶片封裝體。
根據本發明一實施方式，一種晶片封裝體包含基板、絕緣層、支撐層、重佈線層、導電層、阻隔層與導電結構。絕緣層位於基板上，且絕緣層具有背對基板的表面。支撐層位於絕緣層的表面上。支撐層具有背對絕緣層的頂面與圍繞頂面的側面。重佈線層覆蓋支撐層之頂面與側面，且重佈線層延伸至絕緣層的表面。導電層覆蓋重佈線層。阻隔層位於絕緣層與導電層上。阻隔層具有開口與背對絕緣層的表面。部分的導電層由阻隔層的開口裸露。導電結構位於開口中的導電層上且凸出阻隔層。
本發明之再一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式，一種晶片封裝體的製造方法包含下列步驟。形成絕緣層於基板上。形成支撐層於絕緣層上。形成重佈線層以覆蓋支撐層背對絕緣層的頂面與圍繞頂面的側面，且重佈線層延伸至絕緣層背對基板的表面。形成導 電層以覆蓋重佈線層。形成圖案化的阻隔層於絕緣層與導電層上，使部分的導電層由阻隔層的開口裸露。形成導電結構於開口中的導電層上。
在本發明上述實施方式中，由於支撐層位於絕緣層的表面上，且重佈線層覆蓋支撐層之頂面與側面且延伸至絕緣層的表面，因此待導電層覆蓋重佈線層後，導電層也會沿支撐層頂面與側面上的重佈線層與絕緣層表面上的重佈線層設置。如此一來，導電結構可設置在開口中的導電層上。藉由支撐層的設計，導電結構與絕緣層之間的距離增加，使導電結構不易經熱衝擊而與絕緣層直接接觸。
100、100a‧‧‧晶片封裝體
110‧‧‧基板
112‧‧‧表面
120‧‧‧絕緣層
122‧‧‧表面
130、130a‧‧‧重佈線層
140‧‧‧阻隔層
142‧‧‧開口
144、144a‧‧‧壁面
146‧‧‧表面
150、150a‧‧‧第一導電層
160、160a‧‧‧第二導電層
165、165a‧‧‧導電層
170‧‧‧導電結構
180‧‧‧支撐層
182‧‧‧頂面
184、184a‧‧‧側面
200、200a‧‧‧晶片封裝體
S1~S6‧‧‧步驟
S1a~S6a‧‧‧步驟
第1圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第2圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第3圖繪示根據本發明一實施方式之基板形成絕緣層後的剖面圖。
第4圖繪示第3圖之絕緣層形成重佈線層後的剖面圖。
第5圖繪示第4圖之絕緣層與重佈線層形成阻隔層後的剖面圖。
第6圖繪示第5圖之重佈線層與阻隔層形成第一導電層後的剖面圖。
第7圖繪示第6圖之第一導電層形成第二導電層後的剖面圖。
第8圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第9圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第10圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第11圖繪示根據本發明一實施方式之絕緣層形成支撐層後的剖面圖。
第12圖繪示第11圖之支撐層與絕緣層依序形成重佈線層與導電層後的剖面圖。
第13圖繪示第12圖之絕緣層與導電層形成阻隔層後的剖面圖。
第14圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的剖面圖。如圖所示，晶片封裝體100包含基板110、絕緣層120、重佈線層130、阻隔層140、第一導電層150、第二導電層160與導電結構170。其中，絕緣層120位於基板110上。重佈線層130位於絕緣層120上。阻隔層140位於絕緣層120與重佈線層130上。阻隔層140具有開口142、圍繞開口142的壁面144與背對絕緣層120的表面146。部分的重佈線層130可由阻隔層140的開口142裸露。第一導電層150位於開口142中的重佈線層130上，且第一導電層150還延伸至阻隔層140的壁面144與表面146。第二導電層160覆蓋第一導電層150。導電結構170位於第二導電層160上且凸出阻隔層140。
在本實施方式中，基板110的材質可以包含矽，例如半導體晶片。重佈線層130的材質可以包含鋁。阻隔層140的材質可以包含環氧樹脂(epoxy)，例如防焊綠漆。第一導電層150的材質可以包含鋁或鈦鎢合金(TiW)，且厚度可介於2μm至4μm，例如3μm。此外，第二導電層160的材質可以包含鎳金合金。第一導電層150可作為球下冶金層(Under Bump Metallurgy；UBM)，而第二導電層160可作為擴散阻障層。導電結構170可以為球閘陣列的錫球或導電凸塊，其形狀與材質並不用以限制本發明。
由於第一導電層150位於阻隔層140開口142中的重佈線層130上，且第一導電層150延伸至阻隔層140的壁面144與表面146，因此待第二導電層160覆蓋第一導電層150後，第二導電層160也會沿阻隔層140開口142中的第一導電層 150及阻隔層140壁面144與表面146上的第一導電層150設置。如此一來，導電結構170便可設置在第二導電層160上，使得導電結構170與第二導電層160的接觸面積得以提升。因此，本發明之晶片封裝體100的導電結構170不易經熱衝擊而從第二導電層160脫落。
應瞭解到，已敘述過的元件材料與元件連接關係將不再重複贅述，合先敘明。在以下敘述中，將說明第1圖晶片封裝體100的製造方法。
第2圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。首先在步驟S1中，形成絕緣層於基板上。接著在步驟S2中，形成重佈線層於絕緣層上。之後在步驟S3中，形成圖案化的阻隔層於絕緣層與重佈線層上，使部分的重佈線層由阻隔層的開口裸露。接著在步驟S4中，形成第一導電層於開口中的重佈線層上、阻隔層圍繞開口的壁面上與阻隔層背對絕緣層的表面上。之後在步驟S5中，形成第二導電層以覆蓋第一導電層。最後在步驟S6中，形成導電結構於第二導電層上。在以下敘述中，將詳細說明上述各步驟。
第3圖繪示根據本發明一實施方式之基板110形成絕緣層120後的剖面圖。第4圖繪示第3圖之絕緣層120形成重佈線層130後的剖面圖。同時參閱第3圖與第4圖，絕緣層120可利用化學氣相沉積法(Chemical Vapor Deposition；CVD)形成於基板110的表面112上。其中，表面112為基板110的背面。絕緣層120的材質可以包含二氧化矽，但並不用以限制本 發明。待絕緣層120形成後，可在絕緣層120背對基板110的表面122上形成圖案化的重佈線層130。重佈線層130可由物理氣相沉積法(Physical Vapor Deposition；PVD)形成在絕緣層120上，例如濺鍍(sputtering)。
第5圖繪示第4圖之絕緣層120與重佈線層130形成阻隔層140後的剖面圖。同時參閱第4圖與第5圖，待重佈線層130形成後，可在絕緣層120與重佈線層130上形成圖案化的阻隔層140，使阻隔層140具有開口142，且部分的重佈線層130由阻隔層140的開口142裸露。
第6圖繪示第5圖之重佈線層130與阻隔層140形成第一導電層150後的剖面圖。第7圖繪示第6圖之第一導電層150形成第二導電層160後的剖面圖。同時參閱第6圖與第7圖，待圖案化的阻隔層140形成後，可於阻隔層140開口142中的重佈線層130上、阻隔層140的壁面144上與表面146上形成第一導電層150。接著，可形成第二導電層160以覆蓋第一導電層150。在本實施方式中，第二導電層160可採用化鍍的方式形成，例如化鍍鎳金(Electroless Nickel/Immersion Gold；ENIG)。
同時參閱第1圖與第7圖，待第二導電層160形成後，便可於第二導電層160上形成導電結構170，而得到晶片封裝體100。
第8圖繪示根據本發明一實施方式之晶片封裝體100a的剖面圖。晶片封裝體100a包含基板110、絕緣層120、重佈線層130、阻隔層140、第一導電層150a、第二導電層160a 與導電結構170。與第1圖實施方式不同的地方在於：晶片封裝體100a之阻隔層140的壁面144a為斜面，且此斜面與重佈線層130夾鈍角。這樣的設計，可避免第一導電層150a與第二導電層160a在阻隔層140與重佈線層130上因轉折而斷裂。
在以下敘述中，將說明其他型式的晶片封裝體。
第9圖繪示根據本發明一實施方式之晶片封裝體200的剖面圖。晶片封裝體200包含基板110、絕緣層120、支撐層180、重佈線層130、導電層165、阻隔層140與導電結構170。其中，絕緣層120位於基板110上，且絕緣層120具有背對基板110的表面122。支撐層180位於絕緣層120的表面122上。支撐層180具有背對絕緣層120的頂面182與圍繞頂面182的側面184。在本實施方式中，支撐層180的材質可以包含聚合物(polymer)，但並不用以限制本發明。重佈線層130覆蓋支撐層180之頂面182與側面184，且重佈線層130延伸至絕緣層120的表面122。導電層165覆蓋重佈線層130。阻隔層140位於絕緣層120與導電層165上。阻隔層140具有開口142與背對絕緣層120的表面146。部分的導電層165由阻隔層140的開口142裸露。導電結構170位於開口142中的導電層165上且凸出阻隔層140。
由於支撐層180位於絕緣層120的表面122上，且重佈線層130覆蓋支撐層180之頂面182與側面184且延伸至絕緣層120的表面122，因此待導電層165覆蓋重佈線層130後，導電層165也會沿支撐層180頂面182與側面184上的重佈線層130與絕緣層120表面122上的重佈線層130設置。如此一來， 導電結構170便可設置在開口142中的導電層165上。藉由支撐層180的設計，導電結構170與絕緣層120之間的距離增加，使得導電結構170不易經熱衝擊而與絕緣層120直接接觸。
在以下敘述中，將說明第9圖晶片封裝體200的製造方法。
第10圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。首先在步驟S1a中，形成絕緣層於基板上。接著在步驟S2a中，形成支撐層於絕緣層上。之後在步驟S3a中，形成重佈線層以覆蓋支撐層背對絕緣層的頂面與圍繞頂面的側面，且重佈線層延伸至絕緣層背對基板的表面。接著在步驟S4a中，形成導電層以覆蓋重佈線層。之後在步驟S5a中，形成圖案化的阻隔層於絕緣層與導電層上，使部分的導電層由阻隔層的開口裸露。最後在步驟S6a中，形成導電結構於開口中的導電層上。在以下敘述中，將詳細說明上述各步驟。
第11圖繪示根據本發明一實施方式之絕緣層120形成支撐層180後的剖面圖。第12圖繪示第11圖之支撐層180與絕緣層120依序形成重佈線層130與導電層165後的剖面圖。同時參閱第11圖與第12圖，待絕緣層120形成於基板110的表面112上後，可於絕緣層120的表面122上形成支撐層180。接著，可形成重佈線層130以覆蓋支撐層180的頂面182與側面184，且重佈線層130延伸至絕緣層120的表面122。待重佈線層130形成後，可採用化鍍的方式形成導電層165以覆蓋重佈線層130。
第13圖繪示第12圖之絕緣層120與導電層165形成阻隔層140後的剖面圖。同時參閱第12圖與第13圖，待導電層165形成後，可於絕緣層120與導電層165上形成圖案化的阻隔層140，使部分的導電層165可由阻隔層140的開口142裸露。接著，便可在開口142中的導電層165上形成導電結構170(見第9圖)，而得到第9圖的晶片封裝體200。
第14圖繪示根據本發明一實施方式之晶片封裝體200a的剖面圖。晶片封裝體200a包含基板110、絕緣層120、支撐層180、重佈線層130a、導電層165a、阻隔層140與導電結構170。與第9圖實施方式不同的地方在於：晶片封裝體200a之支撐層180的側面184a為斜面，且此斜面與絕緣層120夾鈍角。這樣的設計，可避免重佈線層130a與導電層165a在支撐層180與絕緣層120上因轉折而斷裂。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (8)

  1. 一種晶片封裝體，包含：一基板；一絕緣層，位於該基板上，且具有背對該基板的一表面；一支撐層，位於該絕緣層的該表面上，該支撐層具有背對該絕緣層的一頂面與圍繞該頂面的一側面；一重佈線層，覆蓋該支撐層之該頂面與該側面，該重佈線層具有一延伸部，該延伸部沿該絕緣層的該表面延伸而垂直該支撐層的該側面；一導電層，覆蓋該重佈線層；一阻隔層，位於該絕緣層與該導電層上，該阻隔層具有一開口與背對該絕緣層的一表面，其中部分的該導電層由該開口裸露；一導電結構，位於該開口中的該導電層上且凸出該阻隔層，且該導電結構至少部分位於該阻隔層的該開口中。
  2. 如請求項1所述的晶片封裝體，其中該支撐層的材質包含聚合物。
  3. 如請求項1所述的晶片封裝體，其中該重佈線層的材質包含鋁。
  4. 如請求項1所述的晶片封裝體，其中該導電層的材質包含鎳金合金。
  5. 如請求項1所述的晶片封裝體，其中該導電結構為錫球或導電凸塊。
  6. 如請求項1所述的晶片封裝體，其中該支撐層的該側面為一斜面，且該斜面與該絕緣層夾一鈍角。
  7. 一種晶片封裝體的製造方法，包含：形成一絕緣層於一基板上；形成一支撐層於該絕緣層上；形成一重佈線層以覆蓋該支撐層背對該絕緣層的一頂面與圍繞該頂面的一側面，且該重佈線層延伸至該絕緣層背對該基板的一表面，該重佈線層具有一延伸部，該延伸部沿該絕緣層的該表面延伸而垂直該支撐層的該側面；形成一導電層以覆蓋該重佈線層；形成圖案化的一阻隔層於該絕緣層與該導電層上，使部分的該導電層由該阻隔層的一開口裸露；以及形成一導電結構於該開口中的該導電層上，其中該導電結構至少部分位於該阻隔層的該開口中。
  8. 如請求項7所述的晶片封裝體的製造方法，其中該導電層係以化鍍的方式形成。
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US20060160267A1 (en) * 2005-01-14 2006-07-20 Stats Chippac Ltd. Under bump metallurgy in integrated circuits
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