TWI464849B - 半導體結構及形成元件的方法 - Google Patents

半導體結構及形成元件的方法 Download PDF

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Publication number
TWI464849B
TWI464849B TW099137918A TW99137918A TWI464849B TW I464849 B TWI464849 B TW I464849B TW 099137918 A TW099137918 A TW 099137918A TW 99137918 A TW99137918 A TW 99137918A TW I464849 B TWI464849 B TW I464849B
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Taiwan
Prior art keywords
substrate
dummy
pillar
width
pillars
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TW099137918A
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English (en)
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TW201203481A (en
Inventor
Cheng Hung Shen
Tin Hao Kuo
Chen Cheng Kuo
Chen Shien Chen
Yao Chun Chuang
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201203481A publication Critical patent/TW201203481A/zh
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Publication of TWI464849B publication Critical patent/TWI464849B/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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Description

半導體結構及形成元件的方法
本發明係有關於半導體元件，特別有關於將兩個或多個基底接合在一起所使用的支撐架。
在過去數十年中，電子與半導體的封裝技術上有許多轉變，其影響整個半導體工業。表面黏著技術(surface mount technology；SMT)與球閘陣列(ball grid array；BGA)封裝通常是各種積體電路(IC)元件的高量產組件(high-throughput assembly)的重要步驟，同時可允許印刷電路板上的墊片間距(pad pitch)降低。傳統上封裝的積體電路結構基本上是藉由在晶片上的金屬墊與散佈在模塑樹脂封裝體的電極之間的細微金導線進行內連線，雙列直插式封裝(dual inline package；DIP)或四方扁平封裝(quad flat package；QFP)是目前積體電路封裝的基礎結構。然而，增加周邊引腳數目的設計以及圍繞封裝體的排列方式通常會造成導線(lead wire)的間距(pitch)過短，其會使得封裝晶片的搭載基板(board mounting)受到限制。
晶片級(chip-scale)或晶片尺寸封裝(chip-size packaging；CSP)以及球閘陣列(BGA)封裝只是一些能夠加密電極排列，而不會大幅地增加封裝尺寸的解決方法。一些晶片尺寸封裝(CSP)技術可提供額外的好處，其允許晶片尺寸的晶圓級封裝，晶片尺寸封裝(CSP)通常是在晶片尺寸的1.2倍以內的封裝，其大幅地降低以CSP材料所製造的元件之可能尺寸。
一些晶片尺寸封裝(CSP)或球閘陣列(BGA)封裝依靠焊錫凸塊，提供在晶片上的接點與基底，例如封裝基底、印刷電路板(printed circuit board；PCB)、另一晶片或晶圓，或其他類似的基底上的接點之間的電性連接。其他CSP或BGA封裝則使用放置在凸塊電極或支柱上的錫球或焊錫凸塊，這些封裝結構的完整性係依靠焊錫接合，藉由將一片晶片上的接點對準另一晶片上的接點，施加壓力並且進行回焊(solder reflow)製程，而將基底接合在一起。
然而，基底之間的距離往往會改變，例如相較於基底的邊緣，接近基底中央的基底之間的距離常常會比較大，這可能是因為翹曲、施加壓力不同、抵抗力的量不同或類似的原因所造成。由於基底之間的距離改變，可能會發生沿著支柱結構側邊的焊錫潤濕(solder wetting)現象，特別是沿著基底的邊緣，在此處的基底之間的距離通常小於中央區域。
本發明之一實施例提供用於半導體結構的支撐架(stand-offs)，形成具有主動支柱與偽支柱的基底，主動支柱具有第一寬度與第一高度，偽支柱具有第二寬度與第二高度，其中第二寬度小於第一寬度，並且第二高度大於第一高度。
在一實施例中，支撐架藉由將基底之上的遮罩圖案化而形成，其中圖案化遮罩具有偽支柱開口與主動支柱開口，偽支柱開口的寬度小於主動支柱開口的寬度，偽支柱與主動支柱在各自的開口中形成，然後將圖案化遮罩移除。在此實施例中，偽支柱的寬度小於主動支柱的寬度，並且偽支柱的高度大於主動支柱的高度。
其他實施例揭示如下。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
在此所揭示的實施例之製造與使用詳述如下，然而，可以理解的是，這些實施例提供許多可應用的發明概念，其可以在各種特定背景中實施，在此所討論的特定實施例僅用於說明這些實施例之製造與使用的特定方式，並非用於限定揭露的範圍。
第1至5圖顯示依據一實施例，具有偽支柱的半導體元件之形成方法的各中間階段。首先參閱第1圖，依據一實施例，基底102的一部份具有電性電路104形成於其上，基底102可包括例如巨塊矽(bulk silicon)、摻雜或未摻雜的基底、或者為半導體覆蓋絕緣層(semiconductor-on-insulator；SOI)基底的主動層。一般而言，SOI基底包括一層半導體材料，例如矽，形成於絕緣層上。絕緣層可以是埋藏氧化層(buried oxide；BOX)或氧化矽層，在基底上提供絕緣層，基底通常為矽或玻璃基底，其他基底例如多層或梯度漸變的基底也可以使用。
形成於基底102上的電性電路104可以是適用於特定應用之任何種類的電路，在一實施例中，電性電路104包含形成於基底102上的電性元件，一個或多個介電層覆蓋於電性元件上，可在介電層之間形成金屬層，藉此在電性元件之間按規定路線發送電性訊號，另外電性元件也可在一層或多層介電層內形成。
舉例來說，電性電路104可包含各種N型金氧半導體(N-typed metal-oxide semiconductor；NMOS)以及/或P型金氧半導體(PMOS)元件，例如為電晶體、電容器、電阻器、二極體、光二極體(photo-diode)、熔線以及類似的元件，這些元件互相連接，以執行一種或多種功能。這些功能可包含記憶體結構、處理器結構、感應器、放大器、電源分配器、輸入/輸出電路或類似的功能，在此技術領域中具有通常知識者當可瞭解，上述提供的例子僅用於說明並進一步解釋一些圖式實施例的應用，並非將此揭露限定在任何方式，其他電路也可適用於特定應用而使用。
第1圖中也顯示層間介電層(inter-layer dielectric；ILD)108，層間介電層108可以由例如低介電常數介電材料形成，其例如為磷矽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、摻氟矽玻璃(fluorinated silicate glass；FSG)、SiOx Cy 、旋轉塗佈玻璃(spin-on-glass)、旋轉塗佈高分子(spin-on-polymers)、碳化矽材料、前述之化合物、前述之複合物、前述之組合或類似的材料，可藉由任何習知的合適方法，例如旋轉塗佈、化學氣相沈積(chemical vapor deposition；CVD)，以及電漿增強型化學氣相沈積(plasma-enhanced CVD；PECVD)的方式形成，層間介電層108可包括複數層介電層。
接點例如為接點110，其係貫穿ILD層108而形成，提供至電性電路104的電性接觸。接點110可藉由例如微影技術，在ILD層108上沈積光阻材料並將其圖案化，暴露出ILD層108的一部份，使用蝕刻製程，例如非等向性的乾蝕刻製程，在ILD層108內產生開口，這些開口可以使用擴散阻障層以及/或黏著層(未繪出)作為內襯，並且填充導電材料，藉此形成接點110。在一實施例中，擴散阻障層包括一層或多層的TaN、Ta、TiN、Ti、CoW或類似的材料，並且導電材料包括銅、鎢、鋁、銀以及前述之組合，或類似的材料，藉此形成如第1圖所示之接點110。
在ILD層108之上形成一層或多層的金屬層間介電層(inter-metal dielectric；IMD)112以及相關聯的金屬化層(未繪出)，一般而言，這一層或多層的IMD層112以及相關聯的金屬化層是用於將電性電路104互相連接，以及提供外部的電性連接。IMD層112可由低介電常數介電材料形成，其例如為藉由電漿增強型化學氣相沈積(PECVD)技術或高密度電漿化學氣相沈積(HDPCVD)形成的摻氟矽玻璃(FSG)或類似的材料，並且可包含中間的蝕刻停止層，在最上層的IMD層內形成接點114，藉此提供外部的電性連接。
一層或多層的蝕刻停止層(未繪出)可以設置在相鄰的介電層之間，例如ILD層108與IMD層112之間。一般而言，當形成導孔以及/或接點時，蝕刻停止層提供停止蝕刻製程的機制。蝕刻停止層由介電材料形成，其蝕刻選擇比與相鄰的層不同，例如與其底下的基底102、其上方ILD層108以及上方的IMD層112之蝕刻選擇比不同。在一實施例中，蝕刻停止層可由SiN、SiCN、SiCO、CN、前述之組合或類似的材料，藉由CVD或PECVD技術沈積而成。
第一鈍化層(passivation layer)116例如為介電材料，其可在最上層IMD層112的表面之上形成並圖案化，以形成接點114之上的開口，並且保護其下方的各層，避免受到各種環境污染物的侵害。之後，在第一鈍化層116之上形成導電墊118並將其圖案化，導電墊118提供電性連接，在其之上可形成接觸凸塊，做為外部連接用。導電墊118也可作為重佈路線層(redistribution layer；RDL)，以提供引腳或焊球所需的佈局。導電墊118可由任何合適的導電材料形成，例如銅、鎢、鋁、銀以及前述之組合，或類似的材料。
第二鈍化層120例如為介電層，其在導電墊118之上形成並圖案化，如第1圖所示。第二鈍化層120可由任何合適的方法形成，例如化學氣相沈積(CVD)、物理氣相沈積(physical vapor deposition；PVD)或類似的方法。
第1圖更顯示在第二鈍化層120之上形成保護層122，並且將其圖案化以暴露出至少一部份的導電墊118。保護層122可由例如高分子，如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxasole)或類似的材料，藉由任何合適的製程，例如微影塗佈(lithography coater)製程或類似的製程形成，並且進一步避免元件受到環境的損害，例如濕氣、氧化或類似的現象。
上述所討論的結構可使用任何合適的製程形成，在此不再詳細討論，在此技術領域中具有通常知識者當可瞭解，以上描述係提供實施例特徵的一般描述，而且還可存在許多其他特徵，例如其他電路、襯層、阻障層、凸塊下金屬化配置，以及類似的元件。以上描述僅用於提供在此所討論的實施例之概念，並非用於將此揭示或任何申請專利範圍限定在這些特定實施例中。
第2圖顯示在保護層122的表面之上沈積晶種層(seed layer)210，晶種層210為一層薄的導電材料，其在後續製程步驟期間有助於形成較厚的層。在一實施例中，晶種層210可藉由沈積一層或多層薄的導電層而形成，例如使用CVD或PVD技術，形成一層或多層薄的Cu、Ti、Ta、TiN、TaN、前述之組合或類似的材料層。在一實施例中，可藉由PVD製程沈積一層Ti層，以形成擴散阻障薄膜，並藉由PVD製程沈積一層Cu層，以形成銅晶種層。
之後，如第3圖所示，依據一實施例，在晶種層210之上形成圖案化的遮罩310，圖案化遮罩310的圖案化提供主動支柱(active pillar)開口312以及偽支柱(dummy pillar)開口314，並且圖案化遮罩310定義出後續形成的導電支柱與偽支柱的橫向邊界，其詳細討論如下。圖案化遮罩310可以是圖案化的光阻遮罩、硬遮罩、前述之組合或類似的遮罩。在一實施例中，圖案化遮罩310的厚度約為30μm至約200μm。
將偽支柱開口314放置在導電墊118與接點114之上僅用於說明之用，在後續製程中，當偽支柱形成於偽支柱開口314中時，其並不會作為基底102與連接至基底102的另一基底之間的主動電性連接，偽支柱開口314可在鈍化層以及/或聚亞醯胺層的可用區域之上形成。
第4圖顯示依據一實施例，形成主動支柱410與偽支柱412。主動支柱410與偽支柱412可由任何合適的導電材料形成，包含Cu、Ni、Pt、Al、前述之組合或類似的材料，並且可經由任何數量的合適技術形成，包含PVD、CVD、電化學沈積(electrochemical deposition；ECD)、分子束磊晶(molecular beam epitaxy；MBE)、原子層沈積(atomic layer deposition ALD)、電鍍以及類似的技術。
主動支柱410與偽支柱412可藉由例如電鍍製程形成，將晶圓浸入或泡在電鍍液中，晶圓表面電性連接至外部直流(DC)電源供應的負端，使得晶圓在電鍍製程中作為陰極。固態的導電陽極，例如為銅陽極也浸泡在電鍍液中，並且附著至電源供應的正端。來自陽極的原子解離至電鍍液中，因此陰極例如晶圓可得到此原子，藉此將晶圓暴露出來的導電區域電鍍，例如圖案化遮罩310的主動支柱開口312與偽支柱開口314(參閱第3圖)中，晶種層210暴露出來的部分。然而，也可以使用其他製程形成主動支柱410與偽支柱412。
如上所述，偽支柱開口314的寬度較主動支柱開口312小，由於其寬度較小，偽支柱412在垂直方向的生長速度比主動支柱410快，使得偽支柱412的高度大於主動支柱410，這種方式可以讓主動支柱410與偽支柱412在其他物體之中同時形成，而不需要額外的製程步驟去分別地形成主動支柱410與偽支柱41。
之後，如第5圖所示，可將圖案化遮罩310移除。在圖案化遮罩310由光阻材料形成的實施例中，光阻可藉由例如化學溶液剝除，化學溶液例如為乳酸乙酯(ethyl lactate)、苯甲醚(anisole)、甲基丁基乙酸酯(methyl butyl acetate)、乙酸戊酯(amyl acetate)、甲基酚醛環氧樹脂(cresol novolak resin)以及重氮系光活性化合物(diazo photoactive compound；稱為SPR9)之混合物，或者使用另一種剝離製程。可進行清潔製程，例如浸泡在具有1%的氫氟酸(HF)之磷酸(H3 PO4 )與過氧化氫(H2 O2 )的化學溶液(稱為DPP)中，或者使用另一種清潔製程，除去晶種層210暴露出來的部分以及任何來自保護層122表面的污染物。
在一實施例中，主動支柱410的高度HA 介於約30μm到約150μm之間，並且其寬度WA 介於約40μm到約120μm之間，而偽支柱412的高度HD 介於約40μm到約120μm之間，並且其寬度WD 介於約30μm到約150μm之間。在一實施例中，偽支柱412的寬度與主動支柱410的寬度之比值等於或大於約0.2，並且等於或小於約0.9。
偽支柱412在平面圖中的剖面可以是任何形狀，例如偽支柱412可以是圓形、三角形、方形、矩形、六角形、八角形、多邊形或類似的形狀。另外，偽支柱412可包含多重延伸部分，每個延伸部分具有在不同方向延伸的長軸，例如為L形、T形、星形或類似的形狀，並且這些不同形狀的偽支柱可以被包含在單一晶片上。
第6及7圖顯示依據一實施例，將第一基底602附著至第二基底604，第一基底602可參照與上述第1至5圖相似的方式形成，第二基底604可包括積體電路晶片、封裝基底、中介層(interposer)、高密度內連線、陶瓷基底、有機基底或類似的基底，第二基底604本身可包括各種接觸墊、金屬化層、重分佈路線、貫穿基底的導孔以及/或類似的元件。第二基底604的上表面可包括鈍化層或聚亞醯胺層，以保護第二基底604避免其受到環境污染物污染。第二基底604具有阻焊膜(solder resist mask)606形成於其上，以及焊錫凸塊/錫球608形成於阻焊膜606的開口中。在一實施例中，焊錫凸塊/錫球608包括SnPb、高鉛材料、Sn基焊錫、無鉛焊錫或其他合適的導電材料。
如第6圖所示，在阻焊膜606中的開口對應至主動支柱410與偽支柱412的位置，因此，當如第7圖所示將第一基底602與第二基底604接合在一起時，偽支柱412延伸至開口內，直接支撐在第二基底604的上表面上。在回焊製程之後，焊錫凸塊/錫球608形成與主動支柱410及偽支柱412的電性連接，當偽支柱412不是用於傳送電性元件之間的電性訊號時，焊錫凸塊/錫球608有助於在第一基底602與第二基底604之間提供更強的物理接合。
第8及9圖顯示在另一實施例中，將第一基底802附著至第二基底804，其中第一基底802可以是上述第1至5圖所揭示的基底，並且第二基底804可以是上述第6及7圖所述之第二基底604，其中相似的標號對應至相似的元件。相較於第6及7圖所示之實施例，第8及9圖中的阻焊膜606沒有對應至偽支柱412的開口，如第9圖所示，當第一基底802與第二基底804接合在一起時，偽支柱412支撐在阻焊膜606的表面上。在此實施例中，偽支柱412不需要像第6及7圖那麼高。
第10A至10F圖顯示偽支柱412的各種設置方式以及/或形狀，例如第10A至10C圖分別顯示圓形、三角形以及L形的偽支柱412，其放置在晶片的角落。第10D圖顯示一實施例，其中偽支柱412除了排列在四個角落之外，沿著每一邊緣的中間區域也有偽支柱412存在，並且在晶片的中央區也有偽支柱412。第10E圖顯示另一實施例，其中偽支柱412沿著晶片的周邊排列，第10F圖顯示在第10E圖的實施例中還具有X形的偽支柱412連接對角線的角落。第10E圖與第10F圖中顯示實心的線去表示偽支柱的位置，在這些實施例中，偽支柱在實心的線內排列，偽支柱可以用規則或不規則的間隔放置。在其他實施例中，也可以使用其他的型態排列的偽支柱。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，在此技術領域中具有通常知識者當可瞭解，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
102‧‧‧基底
104‧‧‧電性電路
108‧‧‧層間介電層
110、114‧‧‧接點
112‧‧‧金屬層間介電層
116‧‧‧第一鈍化層
118‧‧‧導電墊
120‧‧‧第二鈍化層
122‧‧‧保護層
210‧‧‧晶種層
310‧‧‧圖案化遮罩
312‧‧‧主動支柱開口
314‧‧‧偽支柱開口
410‧‧‧主動支柱
412‧‧‧偽支柱
602、802‧‧‧第一基底
604、804‧‧‧第二基底
606‧‧‧阻焊膜
608‧‧‧焊錫凸塊/錫球
第1至5圖係顯示依據一實施例，具有偽支柱的半導體元件之形成方法的各中間階段。
第6及7圖係顯示依據一實施例，將兩片基板接合在一起。
第8及9圖係顯示依據另一實施例，將兩片基板接合在一起。
第10A至10F圖係顯示依據一些實施例，可使用的偽支柱圖案。
102．．．基底
104．．．電性電路
108．．．層間介電層
110、114．．．接點
112．．．金屬層間介電層
116．．．第一鈍化層
118．．．導電墊
120．．．第二鈍化層
122．．．保護層
210．．．晶種層
410．．．主動支柱
412．．．偽支柱
602．．．第一基底
604．．．第二基底
606．．．阻焊膜
608．．．焊錫凸塊/錫球

Claims (10)

  1. 一種半導體結構，包括：一第一基底；一主動支柱，設置在該第一基底上，該主動支柱具有一第一寬度與一第一高度；以及一偽支柱，設置在該第一基底上，該偽支柱具有一第二寬度與一第二高度，其中該第二寬度小於該第一寬度，該第二高度大於該第一高度，且該偽支柱由一導電材料形成。
  2. 如申請專利範圍第1項所述之半導體結構，其中該第二寬度與該第一寬度的比值大於或等於0.2，且小於或等於0.9。
  3. 如申請專利範圍第1項所述之半導體結構，其中沿著平行於該第一基底的一平面，該偽支柱的一剖面為圓形。
  4. 如申請專利範圍第1項所述之半導體結構，其中沿著平行於該第一基底的一平面，該偽支柱的一剖面具有複數個直線邊緣。
  5. 如申請專利範圍第1項所述之半導體結構，其中沿著平行於該第一基底的一平面，該偽支柱的一剖面包括一第一部份，具有一第一縱軸，以及一第二部分，具有一第二縱軸，其中該第一縱軸與該第二縱軸相交。
  6. 如申請專利範圍第1項所述之半導體結構，更包括一第二基底附著至該第一基底，該第二基底具有一阻焊膜，且該偽支柱延伸至該阻焊膜的一開口中。
  7. 如申請專利範圍第1項所述之半導體結構，更包括一第二基底附著至該第一基底，該第二基底具有一阻焊膜，且該偽支柱接觸該阻焊膜的一上表面。
  8. 一種形成元件的方法，包括：提供一第一基底，具有一個或多個電性接點；形成一圖案化遮罩在該第一基底之上，該圖案化遮罩具有複數個偽支柱開口與複數個主動支柱開口；在該些偽支柱開口內形成複數個偽支柱，並且在該些主動支柱開口內形成複數個主動支柱，該些偽支柱的一寬度小於該些主動支柱的一寬度，且該些偽支柱不傳送電性訊號；以及移除該圖案化遮罩。
  9. 如申請專利範圍第8項所述之形成元件的方法，其中至少一些偽支柱設置在該第一基底的角落，或沿著該第一基底的相鄰角落之間的邊緣設置。
  10. 如申請專利範圍第8項所述之形成元件的方法，更包括將該第一基底附著至一第二基底，其中該第二基底具有一阻焊膜形成於其上，且該些偽支柱接觸該阻焊膜的一上表面或延伸至該阻焊膜內的個別開口中。
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TW201014000A (en) * 2008-09-10 2010-04-01 Taiwan Semiconductor Mfg Method of forming a light-emitting diode device
TW201023331A (en) * 2008-12-10 2010-06-16 Taiwan Semiconductor Mfg Semiconductor device and method for forming the same

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