JP2005285997A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005285997A JP2005285997A JP2004095965A JP2004095965A JP2005285997A JP 2005285997 A JP2005285997 A JP 2005285997A JP 2004095965 A JP2004095965 A JP 2004095965A JP 2004095965 A JP2004095965 A JP 2004095965A JP 2005285997 A JP2005285997 A JP 2005285997A
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- semiconductor chip
- semiconductor
- semiconductor device
- electrode pad
- chip
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Abstract
【解決手段】下側の半導体チップ104と、上側の半導体チップ106と、下側の半導体チップ104および上側の半導体チップ106の間に設けられ、上側の半導体チップ106の外周縁よりも外方向へ張り出した張出部分を有するシリコンスペーサー108と、を備え、シリコンスペーサー108は、貫通電極190a、190bと、再配線128a、128bと、を有する半導体装置100を提供する。
【選択図】図1
Description
図1は、実施形態1の多段チップ積層構造を示す断面図である。
図4は、実施形態2の多段チップ積層構造を示す断面図である。
図5は、実施形態3の多段チップ積層構造を示す断面図である。
図6は、実施形態4の多段チップ積層構造を示す断面図である。
図7は、実施形態5の多段チップ積層構造を示す断面図である。
102 基板
104 半導体チップ
106 半導体チップ
108 シリコンスペーサー
112 電極パッド
114 電極パッド
116 電極パッド
118 電極パッド
120 ワイヤー
128 再配線
130 補強材
132 封止樹脂層
134 アンダーフィル樹脂層
136 電極パッド
138 半田ボール
142 再配線層
190 貫通電極
192 電極パッド
194 ダミーバンプ
196 ダミーバンプ
200 半導体装置
300 半導体装置
400 半導体装置
411 第一の半導体チップ
412 第一の半導体チップの表面
413 第一の半導体チップのバンプ
414 絶縁フィルム
415 フィルム
416 配線パターン
417 第二の半導体チップ
418 第二の半導体チップの表面
419 第二の半導体チップのバンプ
420 配線パターン
423 接続部
424 接続部
425 接続部
426 接続部
427 接続部
500 半導体装置
1001 半導体装置
1002 第一の半導体チップ
1002a 主面
1003 第二の半導体チップ
1003b 側方領域
1004 ダイパッド
1005 樹脂パッケージ
1006 接着剤
1007 異方性導電樹脂
1020 第一の端子部
1020a 第一の端子パッド
1020b バンプ
1030 第二の端子部
1030a 第二の端子パッド
1030b バンプ
1031 信号用の端子部
1031a 信号用の端子パッド
1031b バンプ
1032 第二の端子部
1032a 第二の端子パッド
1032b バンプ
1033 配線部
1040 外部接続用端子
1041 内部リード
1042 外部リード
1070 樹脂成分
1071 導電ボール
W ワイヤ
1100 半導体装置
1102 基板
1104 半導体チップ
1106 半導体チップ
1108 シリコンスペーサー
1112 電極パッド
1116 電極パッド
1120 ワイヤー
1128 導電部材
1132 レジスト膜
1138 導電部材
Claims (12)
- 第一の半導体素子と、
第二の半導体素子と、
前記第一の半導体素子と前記第二の半導体素子との間に設けられ、前記第二の半導体素子の外周縁よりも外方向へ張り出した張出部分を有する板状体と、
を備え、
前記第一の半導体素子は、前記板状体側の面に第一の電極パッドを有し、
前記第二の半導体素子は、前記板状体側の面に第二の電極パッドおよび第三の電極パッドを有し、
前記板状体は、
前記第一の電極パッドと前記第二の電極パッドとを接続する貫通電極と、
前記張出部分における前記第二の半導体素子側の面に設けられた第四の電極パッドと、
前記第三の電極パッドと前記第四の電極パッドとを接続する配線と、
を有することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記貫通電極は、前記第一の電極パッドおよび前記第二の電極パッドと、それぞれバンプ接合していることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記板状体は、板状スペーサーであることを特徴とする半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記板状体は、シリコンスペーサーであることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第一の半導体素子および前記第二の半導体素子は、シリコン系半導体素子であることを特徴とする半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記第四の電極パッドは、前記第一の半導体素子の外周縁よりも外側に設けられていることを特徴とする半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記第四の電極パッドは、ワイヤーボンディングにより接続されていることを特徴とする半導体装置。 - 請求項1乃至7いずれかに記載の半導体装置において、
基板をさらに備え、
前記第一の半導体素子は、前記基板の上部に設けられており、
前記第二の半導体素子は、前記第一の半導体素子の上部に設けられていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記基板上に、前記板状体を前記張出部分において支持する補強材をさらに備えることを特徴とする半導体装置。 - 請求項8または9に記載の半導体装置において、
前記第一の半導体素子上に、前記板状体を前記張出部分において支持する補強材をさらに備えることを特徴とする半導体装置。 - 請求項8乃至10いずれかに記載の半導体装置において、
前記基板の上面に第五の電極パッドが設けられており、
前記第四の電極パッドは、前記第五の電極パッドにワイヤーボンディングにより接続していることを特徴とする半導体装置。 - 請求項1乃至11いずれかに記載の半導体装置において、
前記第一の半導体素子は、メモリ素子であり、
前記第二の半導体素子は、ロジック素子であることを特徴とする半導体装置。
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KR100914985B1 (ko) * | 2008-01-28 | 2009-09-02 | 주식회사 하이닉스반도체 | 반도체 패키지 |
JP2010062292A (ja) * | 2008-09-03 | 2010-03-18 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
KR101202452B1 (ko) | 2011-07-13 | 2012-11-16 | 에스티에스반도체통신 주식회사 | 반도체 패키지 및 이의 제조 방법 |
US9024452B2 (en) | 2011-07-13 | 2015-05-05 | Sts Semiconductor & Telecommunications Co., Ltd. | Semiconductor package comprising an interposer and method of manufacturing the same |
US10756060B2 (en) | 2018-07-12 | 2020-08-25 | Toshiba Memory Corporation | Semiconductor device |
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US8143716B2 (en) | 2012-03-27 |
JP4580671B2 (ja) | 2010-11-17 |
US20050212114A1 (en) | 2005-09-29 |
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