WO2020232610A1 - 芯片封装结构及芯片封装方法 - Google Patents

芯片封装结构及芯片封装方法 Download PDF

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WO2020232610A1
WO2020232610A1 PCT/CN2019/087659 CN2019087659W WO2020232610A1 WO 2020232610 A1 WO2020232610 A1 WO 2020232610A1 CN 2019087659 W CN2019087659 W CN 2019087659W WO 2020232610 A1 WO2020232610 A1 WO 2020232610A1
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Prior art keywords
chip
conductor post
layer
away
packaging structure
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PCT/CN2019/087659
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English (en)
French (fr)
Inventor
张童龙
张晓东
官勇
李珩
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980096458.2A priority Critical patent/CN113826200A/zh
Priority to PCT/CN2019/087659 priority patent/WO2020232610A1/zh
Priority to EP19930096.3A priority patent/EP3958307A4/en
Publication of WO2020232610A1 publication Critical patent/WO2020232610A1/zh
Priority to US17/531,133 priority patent/US20220077123A1/en

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • This application relates to the technical field of chip packaging, and in particular to a chip packaging structure and a chip packaging method.
  • chips such as Application Processor (AP)
  • AP Application Processor
  • functional modules such as storage modules
  • the proportion of the area occupied by the memory module is increasing, resulting in an increase in the area of the application processing chip.
  • the industry has gradually reached a consensus to separate some functional modules (such as memory modules) within the application processing chip to form a separate chip, and then interconnect with the application processing chip to form a package.
  • some functional modules such as memory modules
  • it can reduce the memory module’s application processing
  • the occupancy ratio in the chip prevents the application processing chip from being too large; on the other hand, the size of the separated memory module is no longer limited by the application processing chip, and the size can become larger to meet the needs of high-storage, high-speed electronic equipment demand. Therefore, there is an urgent need for a multi-chip packaging technology.
  • the present invention provides a chip packaging structure and a chip packaging method, which overcomes the technical problems that the signal transmission between the two chips needs to go through a long line and the signal transmission efficiency is low.
  • an embodiment of the present application provides a chip packaging structure, including: at least one first chip, a second chip, and a carrier, wherein the first chip is disposed between the second chip and the carrier, and the first chip
  • the active layer of is opposite to the active layer of the second chip
  • a first interconnection structure is provided between the first chip and the second chip for connecting the active layer of the first chip and the active layer of the second chip
  • the inside of the first chip is provided with a first conductor post, one end of the first conductor post is connected with the active layer of the first chip, and the other end of the first conductor post passes through the first chip to communicate with the circuit in the carrier board.
  • the carrier board in the embodiment of the present application may be a rewiring layer (for example, the second rewiring layer in the embodiment of the present application), a printed circuit board (Printed Circuit Board, PCB), a circuit board, a chip or a chip packaging structure, etc. ,
  • a rewiring layer for example, the second rewiring layer in the embodiment of the present application
  • PCB printed circuit board
  • circuit board a chip or a chip packaging structure, etc.
  • the embodiment of this application is not limited.
  • the above-mentioned chip packaging structure communicates with the internal circuit of the first chip and the circuit in the carrier through the first conductor post arranged inside the first chip, and connects the internal circuit of the second chip through the second conductor post arranged on the active layer of the second chip
  • the circuit in the carrier board by connecting the active layers of the two chips (ie the first chip and the second chip) face to face, the signal transmission line between the two chips is shortened, and the signal transmission efficiency between the two chips is improved .
  • the chip packaging structure further includes a second conductor post, one end of the second conductor post is in communication with the active layer of the second chip, and the other One end is connected with the circuit in the carrier board.
  • a dielectric layer is provided on the surface of the first chip away from the second chip (that is, the back surface of the first chip), and the first conductor post passes through the dielectric layer and is electrically connected to the carrier board.
  • the backside of the first chip is also the surface of the active layer on the first chip facing away from the first chip.
  • the above-mentioned dielectric layer can prevent the semiconductor material of the first conductive post and the first chip from being polished simultaneously during the grinding process, thus can prevent the conductive particles in the first conductive post from polluting the semiconductor material of the first chip and improve the electrical performance of the chip.
  • the chip packaging structure further includes: a plastic encapsulation layer disposed between the carrier board and the second chip, wherein the first conductor post passes through the plastic encapsulation layer, and the second conductor post passes through Over the plastic layer.
  • the above-mentioned plastic encapsulation layer can prevent the back surface of the first chip from being ground during the chip packaging process, can reduce the process of chip packaging, and thereby reduce the cost of chip packaging.
  • the end face of the first conductor post facing away from the second chip and the end face of the second conductor post facing away from the second chip are flush, so that a flattened load can be obtained during the chip packaging process. board.
  • the first interconnect structure may include at least one solder ball, at least one metal bump, or at least one metal pillar, or the like.
  • the chip packaging structure may further include: a first redistribution layer, a second interconnection structure, a third chip, and a third conductor post, where the first redistribution layer is disposed at The second chip is on the surface facing away from the first chip (also called the back of the second chip), the third chip is arranged on the surface of the first redistribution layer facing away from the first chip, and the third chip is connected to the first chip through the second interconnect structure.
  • the wiring layer is interconnected; the third conductor post is used to electrically connect the circuit in the carrier board and the circuit in the first redistribution layer.
  • the aforementioned third chip may also be replaced with a chip packaging structure in the prior art or any chip packaging structure described in the first aspect of the embodiments of the present application.
  • the end surface of the first conductor post away from the second chip, the end surface of the second conductor post away from the second chip, and the end surface of the third conductor post away from the first redistribution layer are flush.
  • the first rewiring layer is provided on the non-active layer of the second chip to realize the stacking of multi-layer chips, thereby reducing the size of the chip packaging structure and improving the integration of the chip.
  • the chip packaging structure further includes a third interconnection structure disposed on the surface of the carrier board away from the first chip, and the third interconnection structure is used to communicate with the carrier board The circuit in the circuit and the circuit on the printed circuit board.
  • the embodiments of the present application also provide an integrated circuit, which includes a printed circuit board and any one of the chip packaging structures described in the first aspect, wherein the circuits in the carrier of the chip packaging structure pass The third interconnection structure communicates with the circuit on the printed circuit board.
  • embodiments of the present application also provide an integrated circuit device, which includes: the integrated circuit shown in the second aspect.
  • an embodiment of the present application also provides a chip packaging method, which includes:
  • a carrier, at least one first chip, and a second chip are provided, wherein a first conductor post is arranged inside the first chip, and at least one second conductor post is arranged on the active layer of the second chip;
  • the carrier sheet is removed to obtain a chip packaging structure.
  • the chip package structure prepared by the above method is electrically connected to the internal circuit of the first chip and the circuit in the carrier through the first conductor post arranged inside the first chip, and is electrically connected through the second conductor post arranged on the active layer of the second chip.
  • the internal circuit of the second chip is connected to the circuit on the carrier board.
  • the carrier board in the embodiment of the present application may be a rewiring layer (for example, the second rewiring layer in the embodiment of the present application), a printed circuit board (Printed Circuit Board, PCB), a circuit board, a chip, or a chip packaging structure Etc., the embodiment of the present application does not limit it.
  • a rewiring layer for example, the second rewiring layer in the embodiment of the present application
  • PCB printed circuit board
  • Etc chip packaging structure
  • the surface of the active layer of the second chip is provided with a second conductor post; the method further includes:
  • the carrier board and the end surface of the second conductor post away from the second chip are connected with the carrier board.
  • the carrier board is a second redistribution layer
  • the carrier board and the end surface of the first conductor post facing away from the first chip are connected to the carrier board, and the carrier board and the second conductor post are away from each other.
  • the end face of the second chip is connected with the carrier board, which specifically includes:
  • the second rewiring layer is formed on the remaining plastic encapsulation layer, and the first conductor post and the second conductor post are respectively connected with the second rewiring layer.
  • an implementation manner of connecting the active layer of the first chip with the active layer of the second chip through the first interconnection structure may be: At least one of pressure bonding, eutectic bonding, buried bump interconnection, metal-to-metal direct bonding, and hybrid bonding connects the active layer of the first chip with the second chip.
  • the source layer is connected through the first interconnect structure.
  • a part of the plastic encapsulation layer is removed to expose the end surface of the first conductive pillar away from the second chip and the second conductive pillar away from the second chip
  • the end face of can include but is not limited to the following three implementations:
  • the first conductor post is wrapped in the first chip, and one end of the first conductor post is electrically connected to the internal circuit of the first chip.
  • the implementation manner may include the following steps:
  • the part of the plastic encapsulation layer provided on the back surface of the first chip is removed to expose the back surface of the first chip, and the back surface of the first chip is on the first chip facing away from the first chip
  • the surface of the active layer
  • a part of the plastic encapsulation layer and a part of the dielectric layer are removed to expose the end surface of the first conductor post facing away from the second chip and the end surface of the second conductor post facing away from the second chip.
  • forming a dielectric layer can prevent the first conductive pillar and the semiconductor material of the first chip from being ground at the same time, thereby avoiding contamination of the semiconductor material of the first chip by conductive particles in the first conductive pillar , Improve the electrical performance of the chip.
  • the first conductor post is wrapped in the first chip, one end of the first conductor post is connected to the internal circuit of the first chip, and is formed on the carrier, the second chip and the first chip.
  • a first photoresist layer covering the carrier, the second chip and the first chip may be formed; the first photoresist layer may be patterned to expose the Back; using the patterned first photoresist layer as a mask to remove part of the material on the back of the first chip to expose the first conductor post of a predetermined length; removing the patterned first A photoresist.
  • a plastic encapsulation layer covering the carrier, the second chip and the first chip may be formed; part of the plastic encapsulation layer is removed to expose the end surface of the first conductor post facing away from the second chip And the second conductor post is away from the end surface of the second chip.
  • Implementation of the second implementation manner described above does not require the formation of a dielectric layer, and the plastic encapsulation layer is used to protect the back surface of the first chip from being ground, which can reduce the process of chip packaging and further reduce the cost of chip packaging.
  • one end of the first conductor post is connected to the internal circuit of the first chip, and the other end is exposed outside the back surface of the first chip.
  • a first via hole may be opened in the position of the plastic encapsulation layer relative to the first conductor post to expose The first conductor post is away from the end surface of the second chip; and, a second via hole is respectively opened at a position of the plastic encapsulation layer opposite to the second conductor post to expose the second conductor post away from the The end face of the second chip.
  • one end of the first conductor post in the first chip that needs to be prepared and formed is exposed on the back of the first chip.
  • the packaging material does not need to be polished, which can further reduce the chip packaging process. Reduce the cost of chip packaging.
  • the method before bonding the back surface of the second chip on the carrier sheet, the method further includes: sequentially forming a first rewiring layer and a second rewiring layer on the carrier sheet.
  • a three-conductor post wherein a third conductor post is arranged on the surface of the first redistribution layer facing away from the carrier, and one end of the third conductor post is connected to the first redistribution; at this time:
  • An implementation of bonding the back surface of the second chip to the carrier sheet may be: bonding the back surface of the second chip to the surface of the first redistribution layer facing away from the carrier sheet;
  • the method further includes: opening a third via hole at a position of the plastic encapsulation layer relative to the third conductor post to reveal that the third conductor post is away from the first conductor post.
  • the end face of the redistribution layer is not limited to:
  • the other end of the third conductor post is in communication with the carrier board.
  • the method may further include: connecting the third chip with the first rewiring layer through a second interconnect structure.
  • the aforementioned third chip may also be replaced with a chip packaging structure in the prior art or any chip packaging structure described in the first aspect of the embodiments of the present application.
  • the first rewiring layer is provided on the back of the second chip to realize the stacking of multiple layers of chips, thereby reducing the size of the chip packaging structure and improving the integration of the chip.
  • FIG. 1 is a schematic structural diagram of a chip packaging structure provided by the prior art
  • FIG. 2 is a schematic cross-sectional view of the first chip packaging structure provided by an embodiment of the application.
  • FIG. 3 is a schematic cross-sectional view of a second chip packaging structure provided by an embodiment of the application.
  • FIG. 4 is a schematic cross-sectional view of a third chip packaging structure provided by an embodiment of the application.
  • FIG. 5 is a schematic cross-sectional view of a fourth chip packaging structure provided by an embodiment of the application.
  • FIG. 6 is a schematic cross-sectional view of a fifth chip packaging structure provided by an embodiment of the application.
  • FIG. 7 is a schematic cross-sectional view of a sixth chip packaging structure provided by an embodiment of the application.
  • FIG. 8 is a schematic flowchart of a chip packaging method provided by an embodiment of the application.
  • 9A-FIG. 90 are cross-sectional schematic diagrams of structures obtained by each process of a chip packaging method provided by an embodiment of the application;
  • FIG. 10 is a schematic structural diagram of an integrated circuit provided by an embodiment of this application.
  • FIG. 11 is a schematic structural diagram of an integrated circuit device provided by an embodiment of the application.
  • PCB Printed Circuit Board
  • SMT board-level surface mount technology
  • Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer. Various circuit element structures can be processed on silicon wafers to become IC products with specific electrical functions.
  • a die refers to a small piece cut from a wafer, which is a chip. Before the wafer is packaged, the chips on the wafer or the chips obtained by cutting the wafer are called bare chips.
  • Through silicon via is a through hole formed in a chip manufacturing process or a chip packaging process through the silicon layer, and the through hole is filled with conductive material. It should be understood that, in each embodiment of the present application, the through silicon via in the first chip is the first conductor post.
  • a through-dielectric-via is formed in a chip packaging process or a chip packaging process through a through hole including a dielectric material, and the through hole is filled with a conductive material.
  • a through molding via is a through hole that passes through the plastic encapsulation layer formed in the chip packaging process, and the through hole is filled with conductive material. It should be understood that, in each embodiment of the present application, the second conductor post and the third conductor post passing through the plastic encapsulation layer can be called plastic encapsulation through holes.
  • first chip in the embodiments of the present application refer to general terms, and are intended to limit the relative positions and connection modes between the respective chips. It should be understood that in the chip packaging structure, the "first chips” in different positions may be chips with the same function and manufacturing process, or chips with different functions and manufacturing processes.
  • Chips such as the first chip, the second chip, and the third chip in the embodiments of the present application may be bare chips, or may be formed by bare chips and other chips or components (active devices or passive devices, etc.) through simple packaging.
  • the chip may also be a chip packaging structure formed after packaging, which is not limited here. In specific application scenarios, it can be memory (Memory), application processing chip (Application Processor, AP), Micro-Electro-Mechanical System (MEMS), microwave radio frequency chip, Application Specific Integrated Circuit (Application Specific Integrated Circuit), Referred to as ASIC) and other chips.
  • the aforementioned application processing chip or application specific integrated circuit may be a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, for example, a neural network processor in a specific application. (Network Processing Unit, NPU), etc.
  • the memory can be a cache, a random access memory (Random Access Memory, RAM), a read only memory (Read Only Memory, ROM), or other memories. It should be understood that the chips listed here are only exemplary descriptions, which are not limited in this application.
  • FIG. 2 is a schematic cross-sectional view of the first chip packaging structure provided by an embodiment of the application.
  • the chip packaging structure 200 can be obtained by fan-out wafer-level packaging (Fan-out wafer-level package, FOWLP).
  • the packaging structure 200 may include at least one first chip 10, a second chip 20, a carrier board 30, and a plastic encapsulation layer 40 wrapping at least one surface of the first chip 10 and the second chip 20.
  • the active layer 101 of the first chip 10 is opposite to the active layer 201 of the second chip 20, and the active layer 101 and the active layer 201 are directly connected through the first interconnection structure 102;
  • the first conductor post 103 is inside the first chip 10 and communicates with the active layer 101 for connecting the circuit in the active layer 101 with the circuit in the carrier 30.
  • the carrier board in the embodiment of the present application may be a rewiring layer (for example, the second rewiring layer in the embodiment of the present application), a printed circuit board (Printed Circuit Board, PCB), a circuit board, a chip or a chip packaging structure, etc. ,
  • the embodiment of this application is not limited.
  • the embodiment of the present application takes the carrier board 30 as the rewiring layer as an example for description.
  • first conductive pillar 103 inside the first chip 10 may also be called a through silicon via when the first chip 10 is a bare chip or in other cases.
  • the second conductor post 202 there is at least one second conductor post 202 between the second chip 20 and the carrier board 30.
  • One end of the second conductive pillar 202 is electrically connected to the circuit in the active layer 201 of the second chip 20, and the other end of the second conductive pillar 202 is electrically connected to the circuit in the carrier 30.
  • the second conductor post 202 bypasses the first chip 10 and is used to connect the internal circuit of the second chip 20 and the circuit in the carrier 30.
  • the second conductor post 202 passes through the plastic encapsulation layer 40 and communicates with the carrier board 30. At this time, the second conductor post 202 may become a plastic through hole.
  • one end of the first conductor post 103 is electrically connected to the internal circuit of the first chip 10, and the other end passes through the first chip 10 and is electrically connected to the circuit of the carrier board 30, thereby realizing the first chip 10
  • the internal circuit is connected to the carrier board 30.
  • One end of the second conductor post 202 is electrically connected to the internal circuit of the second chip 20, and the other end is electrically connected to the carrier board 30 through the plastic encapsulation layer 40, thereby realizing the internal circuit of the second chip 20 and the carrier board 30 Of connectivity.
  • the active layer 101 of the first chip 10 and the active layer 201 of the second chip 20 are connected face-to-face to shorten the signal transmission distance between the first chip 10 and the second chip 20, and realize the first Part of the I/O terminals of the two chips 20 are connected to the part of the I/O terminals of the first chip 10 at a close distance, so that the first chip 10 and the second chip 20 can quickly transmit signals.
  • the chip packaging structure 300 includes the surface of the first chip 10 facing away from the second chip 20 (also The back side of the first chip 10 is also provided with a dielectric layer 104, and the first conductor post 103 passes through the dielectric layer 104 and is electrically connected to the carrier board 30.
  • first conductor post 103 is electrically connected to the active layer 101 of the first chip 10, and the other end passes through the first chip 10 and the dielectric layer 104 and is electrically connected to the circuit on the carrier board 30.
  • the first conductor post 103 is actually a through-dielectric-via (TDV).
  • the above-mentioned dielectric layer 104 can prevent the semiconductor material of the first conductive pillar 103 and the first chip 10 from being ground at the same time during the grinding process. Therefore, it can prevent the conductive particles in the first conductive pillar 103 from polluting the semiconductor material of the first chip 10 and improve The electrical performance of the chip.
  • the plastic encapsulation layer 40 faces away from the surface of the second chip 20
  • the dielectric layer 104 faces away from the surface of the first chip 10
  • the first conductor post 103 faces away from the end face of the second chip 20 and the second chip 20.
  • the end surface of the conductor post 202 away from the second chip 20 is flush, so that the prepared carrier board 30 is flatter, and the electrical performance of the chip packaging structure is improved.
  • the chip packaging structure 400 may include the components shown in FIG. 2 above. Wherein, the first conductor post 103 passes through the plastic encapsulation layer 40 and is electrically connected to the circuit on the carrier board 30. Similarly, the second conductor post 202 passes through the plastic encapsulation layer 40 and is electrically connected to the circuit on the carrier board 30.
  • the plastic encapsulation layer 40 defines a first via hole relative to the first conductor post 103 and a second via hole relative to the second conductor post 202, and the carrier board 30 is electrically connected through the first via hole.
  • the first conductor post 103 and the second conductor post 202 are electrically connected through the second via hole.
  • the plastic encapsulation layer 40 in the chip packaging structure shown in FIG. 4 can prevent the back surface of the first chip from being ground during the chip packaging process, which can reduce the process of chip packaging, thereby reducing the cost of chip packaging.
  • the first chip 10 in the aforementioned chip packaging structures 200, 300, and 400 may specifically be a cache memory or a random access memory, and the second chip 20 may be an application processing chip.
  • the first chip 10 in the aforementioned chip packaging structures 200, 300, and 400 may specifically be a GPU or an NPU, and the second chip 20 may be an application processing chip.
  • the first chip 10 in the aforementioned chip packaging structures 200, 300, and 400 may specifically be an application processing chip, and the second chip 20 may be a cache memory or a random access memory.
  • the chip packaging structure may include a first rewiring layer in addition to the components in the chip packaging structure 200 shown in FIG. 2, FIG. 3, or FIG. , The third conductor post, the second interconnection structure and the third chip.
  • the chip packaging structure shown in FIG. 2 is taken as an example.
  • the second chip 20 can be bonded to the first redistribution layer 601 through an adhesive material 503.
  • the surface, that is, the first redistribution layer 601 is bonded to the surface of the second chip 20 away from the first chip 10 (also referred to as the non-active layer of the second chip 20 in this application), and the third chip 80 is set on the first redistribution
  • the layer 601 is away from the surface of the first chip 10, the third chip 80 is electrically connected to the first redistribution layer 601 through the second interconnect structure 70; the third conductor post 602 is used to electrically connect the circuit in the carrier 30 and the first redistribution Circuits in the wiring layer 601.
  • One end of the third conductor post 602 is electrically connected to the circuit on the carrier board 30, the other end is electrically connected to the circuit on the first redistribution layer 601, and the internal circuit of the third chip 80 is electrically connected to the first redistribution.
  • the circuit on the layer 601 further realizes the electrical connection between the internal circuit of the third chip 80 and the carrier board 30.
  • the active layer of the third chip 80 may face the first redistribution layer 601.
  • the first redistribution layer 601 may be electrically connected to the active layer of the third chip 80 through the second interconnect structure 70, and further, realize signal transmission between the third chip 80 and the first chip 10, the second chip 20, the PCB, and the like, respectively.
  • the active layer of the third chip 80 can be away from the first redistribution layer 601.
  • the third chip 80 can be It includes a fourth conductor post passing through the third chip 80, one end of the fourth conductor post is electrically connected to the internal circuit of the third chip 80, and the other end is electrically connected to the first redistribution via the second interconnect structure 70 Layer 601, so that the third chip 80 can be electrically connected to the first redistribution layer 601 through the fourth conductor post, the second interconnection structure 70, etc., so as to realize the third chip 80 and the first chip 10 respectively.
  • the first chip 10 in the chip packaging structure 500 may specifically be a cache memory
  • the second chip 20 may be an application processing chip
  • the third chip 80 may be a random access memory.
  • the first chip 10 in the above chip packaging structure 500 may specifically be a random access memory
  • the second chip 20 may be an application processing chip
  • the third chip 80 may be a GPU or an NPU.
  • the aforementioned chip packaging structure 200, 300, 400, and 500 may further include a third interconnection structure 50 for connecting the PCB to couple the chip packaging structure with the PCB.
  • the third interconnect structure 50 may also be connected to other chip packaging structures, which will not be repeated here.
  • the chip packaging structures 200, 300, 400, and 500 shown in FIGS. 2 to 5 above are only described by taking the chip packaging structure including a first chip 10 as an example. It should be understood that the larger the chip size, the lower the yield rate. The higher the cost, the greater the risk of warpage and stress. Optionally, some large chips can be separated into multiple smaller chips and interconnected with the second chip 20 to improve the yield rate of the chips.
  • the chip packaging structure may include a plurality of first chips 10, and the plurality of first chips 10 may be the same or different chips, as shown in FIG. 6 is a schematic cross-sectional view of the fifth chip packaging structure.
  • the chip package structure shown in FIG. 6 includes two first chips 10, A chip and B chip, respectively.
  • the A chip and the B chip are arranged in parallel on the active layer 201 of the second chip 20, and are electrically connected to the second chip 20 through the interconnection structure 1021 and the interconnection structure 1022.
  • the A chip and the B chip are away from the second chip.
  • the surface of the chip 20 is provided with dielectric layers 1041 and 1042 respectively, and the A chip and the B chip are respectively provided with first conductor posts 1031 and 1032 for transmitting signals between the second chip 20 and the carrier 30.
  • the cache memory can include multiple levels, and generally can be composed of a level 1 cache (L1), a level 2 cache (L2), and a level 3 cache (L3).
  • L represents a level or a level (level).
  • the second chip 20 may be an application processing chip
  • the application processing chip includes L1 and L2
  • the chip A may be L3
  • the chip B may be a GPU
  • the third chip 80 may be a RAM.
  • the second chip 20 may be an application processing chip
  • the chip A may be a GPU
  • the chip B may be an NPU
  • the third chip 80 may be a RAM.
  • the second chip 20 may be an application processing chip
  • chip A may be a RAM
  • chip B may be an NPU
  • the third chip 80 may be a GPU.
  • the third chip 80 can also be a memory (memory), a semiconductor die (silicon die), a flip chip package (flip chip package), a passive device (passive device), a microelectromechanical system chip (Micro- electro-mechanical Systems, MEMS) etc.
  • the embodiment of the present application also provides a chip packaging structure group.
  • the chip packaging structure group may include one or more chip packaging structures as shown in FIG. 2 to FIG. 6, wherein two adjacent chip packaging structures are The electrical connection is achieved through the third interconnect structure 50 and the first rewiring layer 601.
  • chip packaging structure group 800 shown in FIG. 7 is illustrated by taking the chip packaging structure shown in FIG. 5 and FIG. 2 as an example. It should be understood that the chip packaging structure group may also include more chip packaging structures, among which, Any one or more chip packaging structures in the chip packaging structure group may also be a chip packaging structure in the prior art, which is not limited in the embodiment of the present application.
  • first chip 10 in different chip packaging structures in the chip packaging structure group may be a chip with the same function and manufacturing process, or may be a chip with different functions and manufacturing processes; similarly, in different chip packaging structures
  • the second chip 20 may be a chip with the same function and manufacturing process, or a chip with a different function and manufacturing process.
  • the chip packaging structure group shown in FIG. 7 can be realized as a multi-layer chip packaging structure, which can compress the volume of the chip packaging structure and realize the production of small-sized electronic devices.
  • the present application also provides a chip packaging method, which adopts fan-out wafer-level packaging technology. Through this method, a chip package with stable performance and high yield can be easily manufactured. . Please refer to the schematic flow diagram of the chip packaging method shown in FIG. 8 and the cross-sectional schematic diagrams of the structure obtained by the various steps shown in FIGS. 9A-90.
  • the chip packaging method may include, but is not limited to, some or all of the following steps:
  • S02 Provide a carrier 600, at least one first chip 10 and a second chip 20, wherein at least one first conductor post 103 is provided inside the first chip 10.
  • At least one second conductor post 202 is provided on the surface of the active layer 201 of the second conductor 20.
  • the first chips 11, 12 and the second chip 20 are shown in FIG. 9A.
  • the method may further include:
  • a temporary bonding adhesive layer 603 can be formed on the carrier sheet 600, and then a first rewiring layer 601 is prepared on the temporary bonding adhesive layer 603, and further, on the first rewiring layer 601 At least one third conductor post 602 is prepared above, and one end of the third conductor post 602 is electrically connected to the circuit on the first redistribution layer 601.
  • the temporary bonding adhesive layer 603 may be hot melt adhesive or optical adhesive, so as to facilitate the subsequent separation of the carrier sheet 600 from the second rewiring 601 layer by heating or light.
  • the carrier 600 may not include the first redistribution layer 601 and the third conductor post 602
  • the first surface of the second chip 20 may be temporarily keyed to the carrier 600 by hot melt glue or optical glue.
  • the above-mentioned carrier 600 may be a silicon wafer, a glass wafer, etc., and the silicon wafer or glass wafer may be a wafer-level or board-level size.
  • the first conductive pillar may be formed inside the first chip and the first interconnection may be formed on the surface of the active layer of the first chip. structure.
  • the first chip formed after the chip manufacturing process includes a thicker substrate, such as a silicon substrate. Based on whether the first conductor post 103 penetrates the substrate of the first chip, the first chip can be divided into two types of chips. . As shown in FIG. 9A, in the first chip 11 of the first type, the first conductive pillar 103 may pass through the first chip 11, and the end surface of the first conductive pillar 103 away from the active layer 101 is exposed between the first chip 11.
  • the first conductor post 103 is disposed inside the first chip 12, and then the substrate of the first chip 12 is polished to make the first conductor post 103 away from the end surface of the active layer 101 Naked.
  • the embodiment of the present application takes the second type of the first chip 12 as an example for illustration, where the first conductive pillar 103 is formed of a conductive material, for example, a metal or metal alloy such as copper, silver, or palladium.
  • the second chip 20 may include at least one second conductor post 202, as shown in FIG. 9A. It should be understood that, in the manufacturing process of the second chip 20, before the wafer is cut to obtain the second chip 20, at least one second conductor post 202 is formed on the active layer 201 of the second chip 20; For example, before S04, a plurality of second conductive pillars 202 are formed on the surface of the active layer 201 of the second chip 20 by photolithography, thin film deposition, electroplating, and other methods. The second conductive pillar 202 may also be formed by other processes, which is not limited in the embodiment of the present application.
  • the first interconnect structure 102 may also be formed on the surface of the active layer 201 of the second chip 20; or, partly formed on the active layer 101 of the first chip 11/12, and partly formed on the active layer of the second chip 20 201, for example, solder balls are provided on the active layer 101 of the first chip 11/12, and pads are provided on the active layer 201 of the second chip 20, which is not limited in the embodiment of the present application.
  • the first conductor post 103 and the first interconnect structure 102 can also be completed in the chip packaging process, for example, before S04, can be on the surface of the active layer 101 of the first chip 11/12 or the second chip
  • the surface of the active layer 201 of 20 forms a first interconnect structure 102, which is not limited in the embodiment of the present application.
  • S04 Adhere the back surface of the second chip 20 to the carrier sheet 600.
  • the back surface of the second chip 20 is the surface of the second chip 20 that faces away from the active layer 201 of the second chip 20.
  • the back surface of the second chip 20 can be bonded to the surface of the first redistribution layer 601 away from the carrier sheet 600 through the adhesive material 604, as shown in FIG. 9B.
  • the carrier 600 may not include the first rewiring layer 601 and the third conductor post 602, and the back surface of the second chip 20 may be directly bonded to the carrier 600.
  • the first chip 12 or the second chip 20 includes a first interconnect structure 102.
  • the first interconnect structure 102 may be solder balls, pads, metal bumps, metal pillars, etc.
  • the interconnection methods include but not Limited to thermal compression bonding (thermal compression bonding), eutectic bonding (eutectic bonding), embedded bump interconnection (embedded bump bonding), metal-metal direct bonding (metal-metal direct bonding), hybrid bonding (hybrid bonding) etc.
  • part of the I/O terminals of the second chip 20 can be electrically connected to part of the I/O terminals of the first chip 10 through the first interconnect structure 102, and the active layer 101 of the first chip 12 and the second
  • the active layer 201 of the chip 20 is directly connected face-to-face to shorten the distance between the active layers of the two chips, so that the first chip 12 and the second chip 20 can quickly transmit signals.
  • S6 can be executed at any time after S2 and before S8, which is not limited in the embodiment of the present application.
  • a plastic encapsulation layer 40 is formed on the carrier 600, the second chip 20 and the first chip 11/12, and a part of the plastic encapsulation layer 40 is removed to expose the end surface of the first conductor post 103 away from the second chip 20.
  • step S8 can include but is not limited to the following three implementation modes:
  • the first chip 10 is the second type of first chip 12 described above, that is, the first conductor post 103 is wrapped in the first chip 10, and one end of the first conductor post 103 is electrically connected
  • the internal circuit of the first chip 10 specifically, the implementation manner may include the following steps:
  • the plastic encapsulation layer may be ground through grinding and polishing processes until the back surface of the first chip 12 is exposed, and the structure shown in FIG. 9D is obtained.
  • a part of the plastic encapsulation layer 40 provided on the back surface of the first chip 12 may be removed by a photolithography process, and the back surface of the first chip 12 is exposed.
  • the silicon material on the back side of the first chip 12 can be etched through a dry etching process, instead of the first conductive pillar 103.
  • the etching finally reveals the first conductor post 103 with a predetermined length.
  • the predetermined length can be 0.1-2 micrometers, such as 0.2 micrometers, 0.5 micrometers, 1 micrometer, 1.2 micrometers, and so on. It should be understood that what is removed by the etching is a part of the silicon substrate on the back of the first chip 12, and the preset length is less than the total length of the first conductive pillar 103. It should also be understood that for different semiconductor materials, a suitable process can be selected to achieve the task of partially removing the material on the back side of the first chip 12.
  • S814 Form the dielectric layer 104 covering the first chip 12 and the first conductive pillar 103 to obtain a structure as shown in FIG. 9F.
  • S816 Remove part of the plastic encapsulation layer 40 and part of the dielectric layer 104 to expose the end surface of the first conductive pillar 103 away from the second chip 20. It should be understood that when the surface of the active layer 201 of the second chip 20 is provided with the second conductor post 202, the end surface of the second conductor post 202 away from the second chip 20 needs to be exposed to obtain the structure as shown in FIG. 9G.
  • the carrier 600 includes the first redistribution layer 601 and the third conductor post 602, the structure formed by removing part of the plastic encapsulation layer 40 also needs to expose the end surface of the third conductor post 602 facing away from the first redistribution layer 601.
  • the plastic encapsulation layer 40 and the dielectric layer 104 can be ground and/or polished until the end surface of the first conductor post 103 facing away from the second chip 20, the end surface of the second conductor post 202 facing away from the second chip 20 and The third conductor post 602 faces away from the end surface of the first redistribution layer 601. It should also be understood that the heights of the first conductor post 103, the second conductor post 202, and the third conductor post 602 may be different. At this time, the higher conductor post needs to be ground to obtain a planarized structure layer, that is, the plastic encapsulation layer 40.
  • the surface away from the carrier 600, the back surface of the first chip 12, the end surface of the first conductor post 103 away from the second chip 20, the end surface of the second conductor post 202 away from the second chip 20, and the third conductor post 602 away from the first rewiring The end faces of layer 601 are flush.
  • forming a dielectric layer can prevent the first conductive pillar 103 and the semiconductor material of the first chip 12 from being ground at the same time, thereby preventing the conductive particles in the first conductive pillar 103 from affecting the first chip 12 Pollution of semiconductor materials improves the electrical performance of the chip.
  • the first chip is the second type of first chip 12, that is, the first conductive pillar 103 is wrapped in the first chip 12, and one end of the first conductive pillar 103 is electrically connected to The internal circuit of the first chip 12, wherein, before the plastic encapsulation layer 40 is formed on the carrier 600 and the second chip 20, the method further includes steps S71-S74, which are specifically as follows:
  • S71 Form a first photoresist layer 901 covering the carrier 600, the second chip 20 and the first chip 12 to obtain a structure as shown in FIG. 9H.
  • a dielectric layer may be formed on the surface of the first photoresist 901 facing away from the second chip 20 and the back surface of the first chip 12.
  • the dielectric layer provided on the surface of the first photoresist 901 falls off, and only the dielectric layer provided on the back surface of the first chip 12 remains.
  • the second implementation of S8 may specifically include the following steps:
  • part of the molding layer 40 may be removed by grinding and/or polishing processes. If the carrier 600 includes the first redistribution layer 601 and the third conductor post 602, the plastic encapsulation layer 40 is polished, and the end surface of the third conductor post 602 facing away from the first redistribution layer 601 needs to be exposed.
  • Implementation of the second implementation manner described above does not require the formation of a dielectric layer, and the plastic encapsulation layer is used to protect the back surface of the first chip from being ground, which can reduce the process of chip packaging and further reduce the cost of chip packaging.
  • the first chip is the aforementioned first chip 11 of the first type, that is, one end of the first conductor post 103 is electrically connected to the internal circuit of the first chip 11, and the other end is exposed on the first chip 11.
  • the implementation may include the following steps:
  • the formed molding layer 40 may be a planarization layer.
  • S832 Open a first via 904 at a position of the plastic encapsulation layer 40 relative to the first conductor post 103 to expose the end surface of the first conductor post 103 away from the second chip 20, and open a position of the plastic encapsulation layer 40 relative to the second conductor post 202 And the second via 903 to expose the end surface of the second conductor post 202 away from the second chip 20 to obtain the structure as shown in FIG. 90.
  • a third via 901 needs to be respectively opened at the position of the plastic encapsulation layer 40 relative to the third conductor post 602 to expose the third conductor.
  • the pillar 602 faces away from the end surface of the first redistribution layer 601.
  • one end of the first conductor post in the first chip 11/12 that needs to be prepared and formed is exposed outside the back surface of the first chip 11/12.
  • the packaging material does not need to be polished, and further The process of chip packaging is reduced, thereby reducing the cost of chip packaging.
  • the carrier 30 is the second redistribution layer.
  • a specific implementation of S10 may be: forming a second redistribution layer on the remaining plastic encapsulation layer, and the first conductor post 103 and the second conductor post 202 are connected to each other respectively. The second redistribution layer is connected.
  • the carrier 600 includes the first redistribution layer 601 and the third conductor post 602, the third conductor post 602 is electrically connected to the carrier 30 to realize the coupling of the carrier 30 and the first redistribution layer 601 .
  • the method may further include:
  • the second interconnect structure 70 may include at least one solder ball, pad, metal bump, metal pillar, etc., which is not limited in the embodiment of the present application.
  • the chip packaging structure shown in FIG. 3 can be obtained through the first implementation of S8, S10 and S12.
  • the chip packaging structure shown in FIG. 2 can be obtained after the second implementation of S8, S10 and S12.
  • the chip packaging structure shown in FIG. 4 can be obtained through the third implementation of S8, S10 and S12.
  • the chip packaging structure as shown in FIG. 5 or FIG. 6 can be obtained through the first implementation of S8, S10, S12 and S14.
  • chip packages with other structures can be obtained through any one of the S8 implementation modes, S10, S12, and S14. The structure is not repeated here.
  • the patterning process may include, but is not limited to, photolithography, 3D printing, silk screen, etc.
  • the photolithography process includes forming a photoresist layer, partially exposing the photoresist layer through a photomask, and using a developer
  • the developed photoresist layer to be patterned is subjected to steps such as etching using the patterned photoresist layer as a mask and the material provided under the photoresist layer.
  • the etching process includes dry etching process, wet etching process, reactive etching process and so on. It should be understood that an appropriate etching process can be selected for the material to be etched and the environment in which the material is located.
  • CMP chemical mechanical planarization
  • the first interconnection structure 102, the second interconnection structure 70, the third interconnection structure 50 and other interconnection structures may include at least one solder ball, at least one metal bump, or at least one metal pillar.
  • Methods of interconnection include but are not limited to thermal compression bonding, eutectic bonding, embedded bump bonding, and metal-metal direct bonding (metal-metal bonding). direct bonding, hybrid bonding, etc.
  • the material of the dielectric layer includes but is not limited to polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy molding compound (EMC) Such as polymer insulating materials, or inorganic insulating materials such as silicon nitride, silicon oxide, and silicon carbide.
  • PI polyimide
  • PBO polybenzoxazole
  • BCB benzocyclobutene
  • EMC epoxy molding compound
  • polymer insulating materials or inorganic insulating materials such as silicon nitride, silicon oxide, and silicon carbide.
  • the first conductor post 103, the second conductor post 202, the third conductor post 602, etc. can be metal posts formed of metal materials, such as copper posts, aluminum posts, silver posts, palladium posts, etc., or they can be The columnar bodies formed of other conductive materials are not limited in the embodiment of the present application.
  • the conductor post is usually prepared by coating, and its height can be precisely controlled.
  • the material of the plastic sealing layer 40 may be one or a combination of epoxy (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane, and the like.
  • the molding process of the plastic encapsulation layer 40 can be as follows: the low-viscosity plastic encapsulation layer 40 is dripped onto the surface of the carrier sheet 600 and the second chip 20, and the low-viscosity plastic encapsulation layer 40 fills the gap between the chip and the carrier sheet 600 and wraps the first For the chips 11/12 and the second chip 20, when the thickness of the low-viscosity molding layer 40 reaches a preset thickness, the low-viscosity molding layer 40 is heated and cured to form the molding layer 40.
  • Spin coating is a thin film forming process, which can be used to form the molding layer 40, the photoresist layer, and the like.
  • the spin coating process usually includes three steps of compounding, high-speed rotation, and volatilization to form a film.
  • the thickness of the film is controlled by controlling the time, rotation speed, amount of dripping, and the concentration and viscosity of the solution used.
  • the dielectric layer 104 may be an organic insulating material, for example, epoxy resin, polyethylene, etc., or an inorganic insulating material, such as silicon nitride, silicon carbide, etc.
  • the preparation process of the dielectric layer 104 includes, but is not limited to, physical vapor deposition. For thin film preparation processes such as chemical vapor deposition, a suitable preparation process can be selected through the material of the dielectric layer 104, and the details are not repeated here.
  • the second redistribution layer, the first redistribution layer 601, and other redistribution layers may include at least one layer of patterned conductive material and an insulating material that isolates the patterned conductive material.
  • the conductive material may be a metal, such as copper. (Cu), silver (Ag), aluminum (Al) or other metals or metal alloys, etc.
  • the conductive material may also be indium tin oxide (ITO), graphite, graphene, etc., which are not limited in the embodiments of the present application.
  • the insulating material may be an inorganic insulating material or an organic insulating material, etc., which is not limited in the embodiment of the present application.
  • the chip packaging structure or the chip packaging structure formed by the chip packaging method can further be applied to integrated circuits.
  • the integrated circuit includes a printed circuit board and a chip packaging structure, wherein the carrier board and the printed circuit board are coupled in the chip packaging structure.
  • the chip packaging structure is any chip packaging structure in the foregoing embodiments.
  • FIG. 10 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • FIG. 10 takes the chip packaging structure 500 shown in FIG. 5 as an example for illustration.
  • the carrier board 30 is connected to each other through a third interconnection structure 50
  • the printed circuit boards 1001 are interconnected, so as to realize that the printed circuit board 1001 supplies power to the chips in the chip packaging structure 500 and the circuits on the printed circuit board 1001 are connected with the circuits of the chip packaging structure 500.
  • the chip packaging structure please refer to the related descriptions in Figure 2 to Figure 7 above, and will not be repeated in this application embodiment.
  • the integrated circuit may be integrated with a central processing unit (CPU), memory, etc.
  • CPU central processing unit
  • memory etc.
  • FIG. 11 is a schematic structural diagram of an integrated circuit device provided by an embodiment of the present application.
  • the integrated circuit device includes an integrated circuit 1101.
  • the integrated circuit 1101 may be the integrated circuit shown in FIG.
  • Related descriptions in the integrated circuit described in 10 are not repeated in the embodiment of this application.
  • the integrated circuit 1101 may be integrated with a CPU, a memory, and the like.
  • the integrated circuit device may further include a power management module 1102 for supplying power to the integrated circuit 1101.
  • the integrated circuit device may further include a communication module 1103, an input module 1104, and/or an output module 1105.
  • the communication module 1103 is used to realize the communication connection between the integrated circuit device and other devices or the Internet;
  • the input module 1104 is used to realize the user inputting information into the integrated circuit device, which may include a touch panel, a keyboard, a camera, etc.;
  • an output module 1105 Used to realize the output of information from the integrated circuit device to the user, which may include a display panel, etc.
  • the power management module 1102, the communication module 1103, the input module 1104, and/or the output module 1105 are not necessary components of the integrated circuit device; the power management module 1102, the communication module 1103, the input module 1104 and/or the output module 1105 may also It is integrated in the integrated circuit 1101, or is separately provided, and is coupled to the integrated circuit 1101, which is not limited in the embodiment of the present application.
  • the integrated circuit device in the embodiment of the present application may be an electronic device including the integrated circuit 1101, such as a smart phone, a tablet computer, a personal digital assistant, an e-book, a computer, a server, a smart bracelet, a virtual reality (Virtual Reality, VR) device, and an enhanced Augmented Reality (AR) equipment, digital TV, set-top box, etc.
  • the electronic devices listed here are only exemplary descriptions, which are not limited in this application.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • chip packaging method can be executed by robots or numerical control processing, and the device software or process used to execute the chip packaging method can be executed by executing the computer program code stored in the memory. Chip packaging method.

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Abstract

一种芯片封装结构及芯片封装方法，该芯片封装结构包括至少一个第一芯片(10)、第二芯片(20)和载板(30)，其中，第一芯片(10)设置于第二芯片(20)和载板(30)之间，第一芯片(10)的有源层(101)和第二芯片(20)的有源层(201)相对，第一芯片(10)和第二芯片(20)之间设置有第一互连结构(102)，用于连通第一芯片(10)的有源层(101)和第二芯片(20)的有源层(201)，第一芯片(10)的内部设有第一导体柱(103)，该第一导体柱(103)的一端与第一芯片(10)的有源层(101)连通，第一导体柱(103)的另一端穿过第一芯片(10)与载板(30)中的电路连通。通过将两个芯片的有源层进行面对面连接，缩短两个芯片之间信号传输的线路，提高两个芯片之间的信号传输效率。

Description

芯片封装结构及芯片封装方法 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构及芯片封装方法。
背景技术
随着人们对多功能、高存储、高速率电子设备的需求越来越多，芯片，如应用处理芯片(Application Processor,AP)集成度越来越高，尺寸越来越大。然而，芯片尺寸越大，应力和翘曲风险越大，成本也越高，良率越低。通常，应用处理芯片内部集成了很多的功能模块，例如存储模块。且随着用户对芯片带宽和存储需求的提高，存储模块占用的面积比例越来越大，导致应用处理芯片的面积变大。
目前产业界逐渐达成共识，将应用处理芯片内部部分功能模块(如存储模块)分离出来，形成单独的芯片，再与应用处理芯片互连形成封装体，一方面，可以减小存储模块在应用处理芯片中的占用比例，避免应用处理芯片尺寸过大；另一方面，分离出来的存储模块，其尺寸不再受限于应用处理芯片，尺寸可以变得更大，满足高存储、高速率电子设备需求。因此，亟需一种多芯片封装的技术。
在现有的芯片封装的技术方案中，如图1所示，通常两个芯片(芯片1和芯片2)分别通过铜柱电连接至重布线层，进而，通过铜柱和重布线层实现两个芯片之间信号的传输。然而，两个芯片之间的信号传输需要经过较长的线路，信号传输效率低。
发明内容
本发明提供一种芯片封装结构和芯片封装方法，克服了上述两个芯片之间的信号传输需要经过较长的线路，信号传输效率低技术问题。
第一方面，本申请实施例提供了一种芯片封装结构，包括：至少一个第一芯片、第二芯片和载板，其中，第一芯片设置于第二芯片和载板之间，第一芯片的有源层和第二芯片的有源层相对，第一芯片和第二芯片之间设置有第一互连结构，用于连通第一芯片的有源层和第二芯片的有源层，第一芯片的内部设有第一导体柱，第一导体柱的一端与第一芯片的有源层连通，第一导体柱的另一端穿过第一芯片与所述载板中的电路连通。
应理解，本申请实施例中载板可以是重布线层(例如本申请实施例中第二重布线层)、印制电路板(Printed Circuit Board，PCB)、电路板、芯片或芯片封装结构等，本申请实施例不作限定。
上述芯片封装结构通过设置于第一芯片内部的第一导体柱连通第一芯片的内部电路与载板中电路，通过设于第二芯片有源层的第二导体柱连通第二芯片的内部电路和载板中电路，通过将两个芯片(即第一芯片和第二芯片)的有源层进行面对面连接，缩短两个芯片之间信号传输的线路，提高两个芯片之间的信号传输效率。
在本申请实施例的一种可能的实现中，芯片封装结构还包括第二导体柱，该第二导体柱的一端与所述第二芯片的有源层连通，所述第二导体柱的另一端与载板中的电路连通。
在本申请实施例的一种可能的实现中，第一芯片背离第二芯片的表面(即第一芯片的背面)上设有介质层，第一导体柱穿过介质层与载板电连接。
应理解，第一芯片的背面也就是第一芯片上背对第一芯片的有源层的表面。
上述介质层可以避免研磨工艺中第一导体柱和第一芯片的半导体材料同时被研磨，因此可以避免第一导体柱中的导电粒子对第一芯片的半导体材料的污染，提高芯片的电学性能。
在本申请实施例的一种可能的实现中，该芯片封装结构还包括：设于载板和第二芯片之间的塑封层，其中，第一导体柱穿过塑封层，第二导体柱穿过塑封层。
上述塑封层可以避免芯片封装工艺中第一芯片的背面被研磨，可减少芯片封装的工序，进而减少芯片封装的成本。
在本申请实施例的一种可能的实现中，第一导体柱背离第二芯片的端面和第二导体柱背离第二芯片的端面齐平，以使在芯片封装过程中可以得到平坦化的载板。
可选地，第一互连结构可以包括至少一个焊球、至少一个金属凸点或至少一个金属柱等。
在本申请实施例的一种可能的实现中，芯片封装结构还可以包括：第一重布线层、第二互连结构、第三芯片和第三导体柱，其中，第一重布线层设于第二芯片背离第一芯片的表面(也称第二芯片的背面)上，第三芯片设于第一重布线层背离第一芯片的表面，第三芯片通过第二互连结构与第一重布线层互连；第三导体柱用于电性连接载板中的电路和第一重布线层中的电路。
可选地，上述第三芯片还可以替换为现有技术中芯片封装结构或本申请实施例第一方面所述的任意一种芯片封装结构。
进一步地，第一导体柱背离第二芯片的端面、第二导体柱背离第二芯片的端面和第三导体柱背离第一重布线层的端面齐平。
上述芯片封装结构，通过在第二芯片的非有源层设置第一重布线层，实现了多层芯片的层叠，进而减少芯片封装结构的尺寸，提高芯片的集成度。
在本申请实施例的一种可能的实现中，芯片封装结构还包括第三互连结构，该第三互连结构设置于载板背离第一芯片表面，第三互连结构用于连通载板中的电路和印制电路板上的电路。
第二方面，本申请实施例还提供了一种集成电路，该集成电路包括印制电路板和第一方面所述的任意一种芯片封装结构，其中，芯片封装结构的载板中的电路通过第三互连结构与印制电路板上的电路连通。
第三方面，本申请实施例还提供了一种集成电路设备，该集成电路设备包括：如第二方面所示的集成电路。
第四方面，本申请实施例还提供了一种芯片封装方法，该方法包括：
提供一载片、至少一个第一芯片、第二芯片，其中，所述第一芯片的内部设有第一导体柱，所述第二芯片的有源层设有至少一个第二导体柱；
将所述第二芯片的背面粘结在所述载片上，所述第二芯片的背面为所述第二芯片上背离所述第二芯片的有源层的表面；
通过第一互连结构将所述第一芯片的有源层与所述第二芯片的有源层连通；
在所述载片、所述第二芯片和所述第一芯片上形成塑封层；
去除部分的所述塑封层，以裸露所述第一导体柱背离所述第二芯片的端面；
将载板与所述第一导体柱背离所述第一芯片的端面与载板连通；
去除所述载片，得到芯片封装结构。
上述方法制备得到的芯片封装结构通过设置于第一芯片内部的第一导体柱电性连接第一芯片的内部电路与载板中电路，通过设于第二芯片有源层的第二导体柱电性连接第二芯片的内部电路和载板中电路，通过将两个芯片的有源层进行面对面连接，缩短两个芯片之间信号传输的线路，提高两个芯片之间的信号传输效率。
可选地，本申请实施例中载板可以是重布线层(例如本申请实施例中第二重布线层)、印制电路板(Printed Circuit Board，PCB)、电路板、芯片或芯片封装结构等，本申请实施例不作限定。
在本申请实施例的一种可能的实现中，所述第二芯片的有源层的表面设有第二导体柱；所述方法还包括：
去除部分的所述塑封层，以显露所述第二导体柱背离所述第二芯片的端面；
将载板与所述第二导体柱背离所述第二芯片的端面与载板连通。
可选地，载板为第二重布线层，所述将载板与所述第一导体柱背离所述第一芯片的端面与载板连通，将载板与所述第二导体柱背离所述第二芯片的端面与载板连通，具体包括：
在剩余的塑封层上形成所述第二重布线层，所述第一导体柱和所述第二导体柱分别与所述第二重布线层连通。
在本申请实施例的一种可能的实现中，通过第一互连结构将所述第一芯片的有源层与所述第二芯片的有源层连通的一种实现方式可以是：通过热压键合、共晶键合、埋入型凸点互连、金属-金属直接键合、混合键合中的至少一种将所述第一芯片的有源层与所述第二芯片的有源层通过第一互连结构连通。
在本申请实施例的一种可能的实现中，去除部分的所述塑封层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面可以包括但不限于如下三种实现方式：
在实现方式一中，第一导体柱被包裹在第一芯片之内，第一导体柱的一端电性连接第一芯片的内部电路，具体的，该实现方式可以包括如下步骤：
去除设于所述第一芯片的背面上的部分的所述塑封层，以裸露所述第一芯片的背面，所述第一芯片的背面为所述第一芯片上背对所述第一芯片的有源层的表面；
去除部分的所述第一芯片的背面的材料，以裸露预设长度的所述第一导体柱；
形成覆盖所述第一芯片和所述第一导体柱的介质层；
去除部分的所述塑封层和部分的所述介质层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面。
实施上述实现方式一，在研磨之前，形成介质层，可以避免第一导体柱和第一芯片的半导体材料同时被研磨，进而避免第一导体柱中的导电粒子对第一芯片的半导体材料的污染，提高芯片的电学性能。
在实现方式二中，第一导体柱被包裹在第一芯片之内，第一导体柱的一端连通第一芯片的内部电路，在所述载片、所述第二芯片和第一芯片上形成塑封层之前，可以形成覆盖所述载片、所述第二芯片和所述第一芯片的第一光刻胶层；图案化所述第一光刻胶层，以裸露所述第一芯片的背面；以所述图案化的第一光刻胶层为掩膜，去除部分所述第一芯片的背面的材料，以裸露预设长度的所述第一导体柱；去除所述图案化的第一光刻胶。
此时，可以形成覆盖所述载片、所述第二芯片和所述第一芯片的塑封层；去除部分的所述塑封层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面。
实施上述实现方式二，不需要形成介质层，通过塑封层来保护第一芯片的背面不被研磨，可减少芯片封装的工序，进而减少芯片封装的成本。
在实现方式三中，第一导体柱的一端连通第一芯片的内部电路，另一端裸露在第一芯片的背面外。此时，在形成覆盖所述载片、所述第二芯片和所述第一芯片的塑封层之后，可以在所述塑封层相对所述第一导体柱的位置开设第一过孔，以裸露所述第一导体柱背离所述第二芯片的端面；以及，在在所述塑封层相对所述第二导体柱的位置分别开设第二过孔，以裸露所述第二导体柱背离所述第二芯片的端面。
实施上述实现方式三，需要制备形成的第一芯片中的第一导体柱的一端裸露于第一芯片的背面，此时，不需要对封装材料进行研磨，可进一步地减少芯片封装的工序，进而减少芯片封装的成本。
在本申请实施例的一种可能的实现中，将所述第二芯片的背面粘结在所述载片上之前，所述方法还包括：在所述载片上依次形成第一重布线层、第三导体柱，其中，第三导体柱设置于第一重布线层背离所述载片的表面，所述第三导体柱的一端与所述第一重布线连通；此时：
所述将所述第二芯片的背面粘结在所述载片上的一种实现可以是：将所述第二芯片的背面粘结在第一重布线层背离所述载片的表面；
在所述塑封层上形成载板之前，所述方法还包括：在所述塑封层相对所述第三导体柱的位置开设第三过孔，以显露所述第三导体柱背离所述第一重布线层的端面；
在所述塑封层上形成载板之后，所述第三导体柱的另一端与所述载板连通。
可选地，在去除所述载片后，该方法还可以包括：通过第二互连结构将第三芯片与所述第一重布线层连通。
可选地，上述第三芯片还可以替换为现有技术中芯片封装结构或本申请实施例第一方面所述的任意一种芯片封装结构。
上述芯片封装结构，通过在第二芯片的背面设置第一重布线层，实现了多层芯片的层叠，进而减少芯片封装结构的尺寸，提高芯片的集成度。
附图说明
图1为现有技术提供的一种芯片封装结构的结构示意图；
图2为本申请实施例提供的第一种芯片封装结构的剖面示意图；
图3为本申请实施例提供的第二种芯片封装结构的剖面示意图；
图4为本申请实施例提供的第三种芯片封装结构的剖面示意图；
图5为本申请实施例提供的第四种芯片封装结构的剖面示意图；
图6为本申请实施例提供的第五种芯片封装结构的剖面示意图；
图7为本申请实施例提供的第六种芯片封装结构的剖面示意图；
图8为本申请实施例提供的一种芯片封装方法的流程示意图；
图9A-图9O为本申请实施例提供的一种芯片封装方法的各流程得到结构的剖面示意图；
图10为本申请实施例提供的一种集成电路的结构示意图；
图11为本申请实施例提供的一种集成电路设备的结构示意图。
具体实施方式
为便于理解，首先对一些概念和背景进行简单介绍。
印制电路板(Printed Circuit Board，PCB)，是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的载体。由于它是采用电子印刷术制作的，故被称为“印刷”电路板。通过板级表面组装技术(surface mount technology，SMT)实现芯片的I/O端与PCB的电气连接。
晶圆(wafer)，指硅半导体集成电路制作所用的硅晶圆，由于其形状为圆形，故称为晶圆。在硅晶圆上可加工制作成各种电路元件结构，而成为有特定电性功能的IC产品。
晶片(die)，指晶圆切割下来的一个小块，为一个芯片。在晶圆未封装前，晶圆上的芯片或晶圆切割得到的芯片称为裸芯片。
硅通孔(through silicon via，TSV)，在芯片制造工艺或者芯片封装工艺中形成的穿过硅层的通孔，该通孔内填充导电材料。应理解，本申请各个实施例中，第一芯片内的硅通孔即为第一导体柱。
介质通孔(through-dielectric-via，TDV)在芯片封装工艺或者芯片封装工艺中形成的穿过包括介电材料的通孔，该通孔内填充导电材料。
塑封通孔(through molding via，TMV)，在芯片封装工艺中形成的穿过塑封层的通孔，该通孔内填充导电材料。应理解，本申请各个实施例中，穿过塑封层的第二导体柱、第三导体柱都可以称为塑封通孔。
需要说明的是，本申请实施例中“第一芯片”、“第二芯片”、“第三芯片”为泛指，旨在限定各个芯片之间的相对位置和连接方式。应理解，在芯片封装结构中，不同位置的“第一芯片”可以是功能、制程等相同的芯片或功能、制程等不同的芯片。
本申请中一个部件与另一个部件的电气连接，也称为“电连接”、“连通”、“耦合”、“互连”、“直连”等。
本申请实施例中第一芯片、第二芯片和第三芯片等芯片可以是裸芯片，也可以是裸芯片与其他芯片或部件(有源器件或无源器件等)形成的通过简单封装后形成的芯片，还可以是经过封装之后形成的芯片封装结构，此处不作限定。在具体的应用场景中可以是存储器(Memory)、应用处理芯片(Application Processor,AP)、微机电系统(Micro-Electro-Mechanical System，MEMS)、微波射频芯片、专用集成电路(Application  Specific Integrated Circuit，简称ASIC)等芯片。应理解，上述应用处理芯片或专用集成电路在具体应用中可以是中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)、人工智能处理器，例如，神经网络处理器(Network Processing Unit，NPU)等。存储器可以是高速缓冲存储器(cache)、随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)或其他存储器。应理解，这里所列举的芯片仅为示例性说明，本申请对此不作限定。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述。
图2所示为本申请实施例提供的第一种芯片封装结构的剖面示意图，该芯片封装结构200可以通过扇出型晶圆级封装(Fan-out wafer-level package,FOWLP)得到，该芯片封装结构200可以包括至少一个第一芯片10、第二芯片20、载板30以及包裹第一芯片10和第二芯片20的至少一个表面的塑封层40。其中，第一芯片10的有源层101与第二芯片20的有源层201相对，且有源层101和有源层201通过第一互连结构102直连；第一芯片10的内部设有至少一个第一导体柱103。第一导体柱103在第一芯片10的内部，连通有源层101，用于将有源层101中的电路与载板30中的电路连通。
应理解，本申请实施例中载板可以是重布线层(例如本申请实施例中第二重布线层)、印制电路板(Printed Circuit Board，PCB)、电路板、芯片或芯片封装结构等，本申请实施例不作限定。本申请实施例以载板30为重布线层为例来说明。
需要说明的是，第一芯片10内部的第一导体柱103在第一芯片10为裸芯片的情况下或者其他情况下，也可以称为硅通孔。
可选地，第二芯片20和所述载板30之间有至少一个第二导体柱202。第二导体柱202的一端被电连接至第二芯片20的有源层201内的电路，第二导体柱202的另一端被电连接至载板30内的电路。第二导体柱202绕过第一芯片10，用于连通第二芯片20的内部电路和载板30中的电路。
需要说明的是，第二导体柱202穿过塑封层40与载板30连通，此时的第二导体柱202可以成为塑封通孔。
如图2所示第一导体柱103的一端被电连接至第一芯片10的内部电路，另一端穿过第一芯片10被电连接至载板30的电路，进而实现了第一芯片10的内部电路与载板30的连通。
第二导体柱202的一端被电性连接至第二芯片20的内部电路，另一端穿过塑封层40被电性连接至载板30，进而实现了第二芯片20的内部电路与载板30的连通。
上述芯片封装结构中，第一芯片10的有源层101和第二芯片20的有源层201通过面对面的连接，缩短了第一芯片10与第二芯片20之间信号传输距离，实现了第二芯片20的部分I/O端与第一芯片10的部分I/O端的近距离连接，使得第一芯片10和第二芯片20快速传输信号。
图3是本申请实施例提供的第二种芯片封装结构的剖面示意图，该芯片封装结构300除包括上述图2所示的各个部件外，在第一芯片10背离第二芯片20的表面(也称第一芯片10的背面)还设有介质层104，第一导体柱103穿过介质层104与载板30电连接。
需要说明的是，第一导体柱103的一端被电连接至第一芯片10的有源层101，另一端 穿过第一芯片10和介质层104与载板30上的电路电连接，此时，第一导体柱103的实际上是介质通孔(through-dielectric-via，TDV)。
上述介质层104可以避免研磨工艺中第一导体柱103和第一芯片10的半导体材料同时被研磨，因此可以避免第一导体柱103中的导电粒子对第一芯片10的半导体材料的污染，提高芯片的电学性能。
可选地，上述芯片封装结构200、300中，塑封层40背离第二芯片20的表面、介质层104背离第一芯片10的表面、第一导体柱103背离第二芯片20的端面和第二导体柱202背离第二芯片20的端面齐平，使得制备得到的载板30更加平坦，提高芯片封装结构的电学性能。
图4是本申请实施例提供的第三种芯片封装结构的剖面示意图，该芯片封装结构400可以包括上述图2所示的各个部件。其中，第一导体柱103穿过塑封层40与载板30上的电路电连接，同理，第二导体柱202穿过塑封层40与载板30上的电路电连接。
在本申请实施例的另一种实现中，该塑封层40相对第一导体柱103开设第一过孔以及相对第二导体柱202开设第二过孔，载板30通过第一过孔电连接第一导体柱103以及通过第二过孔电连接第二导体柱202。
上述图4所示的芯片封装结构中塑封层40可以避免芯片封装工艺中第一芯片的背面被研磨，可减少芯片封装的工序，进而减少芯片封装的成本。
在本申请实施例的第一应用场景中，上述芯片封装结构200、300和400中第一芯片10具体可以是高速缓冲存储器或者随机存储器，第二芯片20可以是应用处理芯片。
在本申请实施例的第二应用场景中，上述芯片封装结构200、300和400中第一芯片10具体可以是GPU或NPU，第二芯片20可以是应用处理芯片。
在本申请实施例的第三应用场景中，上述芯片封装结构200、300和400中第一芯片10具体可以是应用处理芯片，第二芯片20可以是高速缓冲存储器或者随机存储器。
应理解，不限于上述应用场景，本申请实施例还可以应用于其他应用场景中，对此，本申请实施例不作限定。
在本申请实施例的一种可能的实现中，该芯片封装结构除包括如上述图2、图3或图4所示的芯片封装结构200中各个部件之外，还可以包括第一重布线层、第三导体柱、第二互连结构和第三芯片。本申请实施例中以图2所示的芯片封装结构为例来说明，如图5所示，在芯片封装结构500中第二芯片20可以通过粘性材料503粘结在第一重布线层601的表面，即第一重布线层601与第二芯片20背离第一芯片10的表面(本申请中也称第二芯片20的非有源层)粘结，第三芯片80设于第一重布线层601背离第一芯片10的表面，第三芯片80通过第二互连结构70与第一重布线层601电连接；第三导体柱602用于电连接载板30中的电路和第一重布线层601中的电路。
第三导体柱602的一端被电连接至载板30上的电路，另一端被电连接至第一重布线层601上的电路，而第三芯片80的内部电路被电连接至第一重布线层601上的电路，进而实现了第三芯片80的内部电路与载板30的电连接。
在第三芯片80的内部电路与第一重布线层601的第一种电连接方式中，第三芯片80的有源层可以面对第一重布线层601，此时，第一重布线层601可以通过第二互连结构70 与第三芯片80的有源层电连接，进而，实现第三芯片80分别与第一芯片10、第二芯片20、PCB等之间的信号传输。
在第三芯片80的内部电路与第一重布线层601的第二种电连接方式中，第三芯片80的有源层可以背离第一重布线层601，此时，第三芯片80内可以包括穿过该第三芯片80的第四导体柱，该第四导体柱的一端被电连接至第三芯片80的内部电路，另一端通过第二互连结构70被电连接至第一重布线层601，进而，使得第三芯片80可以通过其内的第四导体柱、第二互连结构70等与第一重布线层601进行电连接，以实现第三芯片80分别与第一芯片10、第二芯片20、PCB等之间的信号传输。
在本申请实施例的第四应用场景中，上述芯片封装结构500中第一芯片10具体可以是高速缓冲存储器，第二芯片20可以是应用处理芯片，第三芯片80具体可以是随机存储器。
在本申请实施例的第五应用场景中，上述芯片封装结构500中第一芯片10具体可以是随机存储器，第二芯片20可以是应用处理芯片，第三芯片80具体可以是GPU或NPU。
应理解，不限于上述应用场景，本申请实施例还可以应用于其他应用场景中，对此，本申请实施例不作限定。
在本申请实施例的另一种实现中，上述芯片封装结构200、300、400和500还可以包括第三互连结构50，用于连接PCB，以使芯片封装结构与PCB耦合。在本申请实施例的另一种实现中，第三互连结构50还可以连接其他的芯片封装结构，此处不再赘述。
上述图2-图5所示的芯片封装结构200、300、400和500,仅仅以芯片封装结构包括一个第一芯片10为例来说明，应理解，芯片的尺寸越大，良率越低，成本越高，翘曲和应力风险也越大。可选地，可以将一些大的芯片分离成多个较小的芯片，并与第二芯片20互连，提高芯片的良品率。芯片封装结构可以包括多个第一芯片10，该多个第一芯片10可以是相同或不同的芯片，如图6所示的第五种芯片封装结构的剖面示意图。图6所示的芯片封装结构包括两个第一芯片10分别是A芯片和B芯片。A芯片和B芯片并列设于第二芯片20的有源层201上，分别通过互连结构1021和互连结构1022与第二芯片20电连接，可选地，A芯片和B芯片背离第二芯片20的表面分别设置有介质层1041、1042，A芯片和B芯片内分别设有第一导体柱1031、1032，用于传输第二芯片20与载板30之间的信号。
一般来说，高速缓存存储器可以包括多个层次，一般可以由一级缓存(L1)、二级缓存(L2)、三级缓存(L3)，L表示级别或层级(level)。在本申请实施例第五实现场景中，第二芯片20可以是应用处理芯片，该应用处理芯片包括L1、L2，芯片A可以是L3、芯片B可以是GPU，第三芯片80可以是RAM。
在本申请实施例的第六实现场景中，第二芯片20可以是应用处理芯片、芯片A可以是GPU、芯片B可以是NPU，第三芯片80可以是RAM。
在本申请实施例的第七实现场景中，第二芯片20可以是应用处理芯片、芯片A可以是RAM、芯片B可以是NPU，第三芯片80可以是GPU，
应理解，不限于上述应用场景，本申请实施例还可以应用于其他应用场景中，对此，本申请实施例不作限定。
上述各个应用场景中，第三芯片80还可以是存储器(memory)，半导体管芯(silicon die)，倒装芯片封装(flip chip package)，被动元件(passive device)、微机电系统芯片 (Micro-electro-mechanical Systems，MEMS)等。
本申请实施例还提供了一种芯片封装结构组，该芯片封装结构组可以包括一个或多个如图2-图6所示的芯片封装结构，其中，相邻的两个芯片封装结构之间通过第三互连结构50、第一重布线层601实现电性连接。
应理解，图7所示的芯片封装结构组800是以图5和图2所示的芯片封装结构为例来说明，应理解，芯片封装结构组还可以包括更多的芯片封装结构，其中，芯片封装结构组中任意一个或多个芯片封装结构还可以是现有技术中的芯片封装结构，本申请实施例不作限定。
还应理解，芯片封装结构组内不同的芯片封装结构中的第一芯片10可以是功能、制程等相同的芯片，也可以是功能、制程等不同的芯片；同理，不同的芯片封装结构中第二芯片20可以是功能、制程等相同的芯片，也可以是功能、制程等不同的芯片。
上述图7所示的芯片封装结构组可实现为多层的芯片封装结构，可以压缩芯片封装结构的体积，实现小尺寸电子设备的生产。
为制备上述芯片封装体，本申请还提供一种芯片封装方法，该方法采用了扇出型晶圆级封装技术，通过该方法能够较便捷的制得性能稳定，良率较高的芯片封装体。请参阅图8所示的芯片封装方法的流程示意图，以及图9A-图9O所示的各个步骤得到结构的剖面示意图，该芯片的封装方法可以包括但不限于如下部分或全部步骤：
S02：提供一载片600、至少一个第一芯片10和第二芯片20，其中，第一芯片10的内部设有至少一个第一导体柱103。
可选地，第二导体20的的有源层201的表面上设有至少一个第二导体柱202。如图9A中所示的第一芯片11、12和第二芯片20。
在本申请实施例的实现一(例如形成如图5或图6所示的芯片封装结构的实现)中，在步骤S4之前，该方法还可以包括：
S03：在载片600上依次制备第一重布线层601、与第一重布线层601电连接的第三导体柱602，得到线路载片60，如图9A所示的线路载片60的剖面示意图。
在S03的一种具体的实现中，可以在载片600上形成临时键合胶层603，再在临时键合胶层603上制备第一重布线层601，进而，在第一重布线层601上制备至少一个第三导体柱602，该第三导体柱602的一端被电连接第一重布线层601上的电路。其中，临时键合胶层603可以是热熔胶或光学胶，以便于后续通过加热或光照将载片600与第二重布线601层分离。
在本申请实施例的实现二(例如形成如图2、图3或图4所示的芯片封装结构的实现)中，载片600上可以不包括第一重布线层601和第三导体柱602，第二芯片20的第一表面可以通过热熔胶或光学胶临时键固定在载片600上。
上述载片600可以是硅片、玻璃片等，硅片或玻璃片可以是晶圆级或板级的尺寸。
应理解，在第一芯片的制造工艺中，对晶圆进行切割得到第一芯片之前，可以在第一芯片内部形成第一导体柱以及在第一芯片的有源层的表面形成第一互连结构。其中，通常芯片制造工艺后形成的第一芯片包括较厚的衬底，比如硅衬底，基于第一导体柱103是否 穿透第一芯片的衬底，可以将第一芯片分为两类芯片。如图9A所示，其中，在第一类第一芯片11中，第一导体柱103可以穿过第一芯片11，第一导体柱103背离有源层101的端面裸露与第一芯片11之外；在第二类第一芯片12中，第一导体柱103设置于第一芯片12的内部，后续通过研磨第一芯片12的衬底，使得第一导体柱103背离有源层101的端面裸露出来。本申请实施例以第二类第一芯片12为例来说明，其中，第一导体柱103由导电材料，比如，铜、银或者钯等金属或金属的合金形成。
第二芯片20可以包括至少一个第二导体柱202，如图9A所示。应理解，在第二芯片20的制造工艺中，对晶圆进行切割得到第二芯片20之前，在第二芯片20的有源层201形成至少一个第二导体柱202；也可以在芯片封装工艺中完成，例如，在S04之前，通过光刻、薄膜沉积、电镀等方法在第二芯片20的有源层201的表面形成多个第二导体柱202。还可以通过其他工艺形成第二导体柱202，本申请实施例不作限定。
第一互连结构102也可以形成在第二芯片20的有源层201的表面；或，部分形成在第一芯片11/12的有源层101，部分形成在第二芯片20的有源层201，例如，在第一芯片11/12的有源层101设有焊球，在第二芯片20的有源层201设有焊盘，对此，本申请实施例不作限定。
可选地，第一导体柱103和第一互连结构102也可以在芯片封装工艺中完成，例如，在S04之前，可以在第一芯片11/12的有源层101的表面或第二芯片20的有源层201的表面形成第一互连结构102，本申请实施例不作限定。
S04：将第二芯片20的背面粘结在载片600上，第二芯片20的背面为第二芯片20上背离第二芯片20的有源层201的表面。
对应于上述实现一，第二芯片20的背面可以通过黏性材料604粘结在第一重布线层601背离载片600的表面，如图9B所示。
对应于上述实现二，载片600上可以不包括第一重布线层601和第三导体柱602，第二芯片20的背面可以直接粘结在载片600上。
S06：通过第一互连结构102将第一芯片11/12的有源层101和第二芯片20的有源层201连通，以第二类第一芯片12为例，如图9B所示。
其中，第一芯片12或第二芯片20上包括第一互连结构102，该第一互连结构102可以是焊球、焊盘、金属凸点、金属柱等，互连的方法包括但不限于热压键合(thermal compression bonding)、共晶键合(eutectic bonding)、埋入型凸点互连(embedded bump bonding)、金属-金属直接键合(metal-metal direct bonding)、混合键合(hybrid bonding)等。
进行互连后，第二芯片20的部分I/O端可以通过第一互连结构102与第一芯片10的部分I/O端进行电连接，第一芯片12的有源层101和第二芯片20的有源层201面对面直连可缩短两芯片有源层之间的距离，使得第一芯片12和第二芯片20之间可以快速传输信号。
应理解，S6可以在S2之后，S8之前的任意时刻执行，本申请实施例不做限定。
S08：在载片600、第二芯片20和第一芯片11/12上形成塑封层40，去除部分的塑封层40，以裸露第一导体柱103背离第二芯片20的端面。
应理解，在第二芯片20的有源层201的表面设置有第二导体柱的情况下，去除部分塑 封层40后，还需要裸露出第二导体柱202背离第二芯片20的端面。
该塑封层40具有绝缘、防止芯片被氧化、支撑芯片封装结构的作用。其中，步骤S8的可以包括但不限于如下3种实现方式：
实现方式一：
在实现方式一中，在步骤S8之前第一芯片10为上述第二类第一芯片12，即第一导体柱103被包裹在第一芯片10之内，第一导体柱103的一端被电连接第一芯片10的内部电路，具体的，该实现方式可以包括如下步骤：
S811：形成覆盖载片600、第二芯片20和第一芯片12的塑封层40，得到如图9C所示的结构。
S812：去除设于第一芯片12的背面上的部分塑封层，以裸露第一芯片12的背面。
在S812的一种实现中，可以通过研磨和抛光工艺对塑封层进行研磨，直到显露出第一芯片12的背面，得到如图9D所示的结构。
在S812的另一种实现中，可以通过光刻工艺去除设于第一芯片12的背面的部分塑封层40，裸露第一芯片12的背面。
S813：去除部分的第一芯片12的背面的材料，以裸露预设长度的第一导体柱103，得到如图9E所示的结构。
在一种具体实现中，可以通过干刻工艺，只对第一芯片12的背面(即第一芯片12背离第二芯片20的表面)的硅材料进行刻蚀，而不对第一导体柱103进行刻蚀，最终显露预设长度的第一导体柱103。该预设长度可以是0.1-2微米，例如0.2微米、0.5微米、1微米、1.2微米等。应理解，刻蚀所去除的是第一芯片12的背面的部分硅衬底，预设长度小于第一导体柱103的总长度。还应理解，对于不同的半导体材料，可以选择合适的工艺以实现部分去除第一芯片12的背面的材料的任务。
应理解，可以根据塑封层40是否已经形成、塑封层40的材质、第一导电体103的材质选择合适的工艺，在不损伤或几乎不损伤第一导电体103的情况下，去除第一芯片12的背面的材料，对此，本申请实施例不再赘述。
S814：形成覆盖第一芯片12和第一导体柱103的介质层104，得到如图9F所示的结构。
S816：去除部分的塑封层40和部分的介质层104，以裸露第一导体柱103背离第二芯片20的端面。应理解，第二芯片20的有源层201的表面设有第二导体柱202的情况下，还需要裸露第二导体柱202背离第二芯片20的端面，得到如图9G所示的结构。
应理解，若载片600上包括第一重布线层601和第三导体柱602，则去除部分塑封层40形成的结构还需要裸露第三导体柱602背对第一重布线层601的端面。
在一种具体的实现中，可以研磨和/或抛光塑封层40和介质层104,直到显露第一导体柱103背离第二芯片20的端面、第二导体柱202背离第二芯片20的端面以及第三导体柱602背离第一重布线层601的端面。还应理解，第一导体柱103、第二导体柱202和第三导体柱602的高度可能不同，此时，还需要研磨高出的导体柱，以得到平坦化的结构层，即塑封层40背离载片600的表面、第一芯片12的背面、第一导体柱103背离第二芯片20的端面、第二导体柱202背离第二芯片20的端面以及第三导体柱602背离第一重布线层601 的端面齐平。
实施上述实现方式一，在研磨之前，形成介质层，可以避免第一导体柱103和第一芯片12的半导体材料同时被研磨，进而避免第一导体柱103中的导电粒子对第一芯片12的半导体材料的污染，提高芯片的电学性能。
实现方式二：
在实现方式二中，在步骤S8之前第一芯片为上述第二类第一芯片12，即第一导体柱103被包裹在第一芯片12之内，第一导体柱103的一端被电连接至第一芯片12的内部电路，其中，在载片600和第二芯片20上形成塑封层40之前，该方法还包括步骤S71-S74，具体如下：
S71：形成覆盖载片600、第二芯片20和第一芯片12的第一光刻胶层901，得到如图9H所示的结构。
S72：图案化第一光刻胶层901，裸露第一芯片12的背面，得到如图9I所示的结构。
S73：以图案化的第一光刻胶层901为掩膜，去除部分第一芯片12的背面的材料，以裸露预设长度的第一导体柱103，得到如图9J所示的结构。
S74：去除图案化的第一光刻胶901，得到如图9K所示的结构。
在本申请实施例的另一种实现中，在S73之后,S74之前，可以在第一光刻胶901的背离第二芯片20的表面和第一芯片12的背面上形成介质层。在S74中，去除第一光刻胶901层时，设于第一光刻胶901的表面的介质层脱落，进而仅仅保留设于第一芯片12的背面上形成介质层。
此时，S8的实现方式二具体可以包括如下步骤：
S821：形成覆盖载片600、第二芯片20和第一芯片12的塑封层40，得到如图9L所示的结构。
S822：去除部分的塑封层40，以裸露第一导体柱103背离第二芯片20的端面以及第二导体柱202背离第二芯片20的端面，得到如图9M所示的结构。
应理解，可以通过研磨和/或抛光工艺去除部分的塑封层40。若载片600上包括第一重布线层601和第三导体柱602，则研磨塑封层40，还需要裸露第三导体柱602背对第一重布线层601的端面。
实施上述实现方式二，不需要形成介质层，通过塑封层来保护第一芯片的背面不被研磨，可减少芯片封装的工序，进而减少芯片封装的成本。
实现方式三：
在实现方式三中，在步骤S8之前第一芯片为上述第一类第一芯片11，即，第一导体柱103的一端电连接第一芯片11的内部电路，另一端裸露在第一芯片11的背面。具体的，该实现方式可以包括如下步骤：
S831：形成覆盖载片600、第二芯片20和第一芯片11的塑封层40，得到如图9N所示的结构。
其中，形成的塑封层40可以是为平坦化层。
S832：在塑封层40相对第一导体柱103的位置开设第一过孔904，以裸露第一导体柱103背离第二芯片20的端面，以及在塑封层40相对第二导体柱202的位置开设和第二过 孔903，以裸露第二导体柱202背离第二芯片20的端面，得到如图9O所示的结构。
应理解，若载片600上包括第一重布线层601和第三导体柱602，则还需要在塑封层40相对第三导体柱602的位置分别开设第三过孔901，以裸露第三导体柱602背离第一重布线层601的端面。
实施上述实现方式三，需要制备形成的第一芯片11/12中的第一导体柱的一端裸露于第一芯片11/12的背面外，此时，不需要对封装材料进行研磨，可进一步地减少芯片封装的工序，进而减少芯片封装的成本。
S10：将载板30与第一导体柱103背离第一芯片11/12的端面连通。应理解，第二芯片20的有源层201的表面设有第二导体柱202的情况下，还需要将载板30与第二导体柱202背离第二芯片20的端面连通。
可选地，载板30为第二重布线层，S10的一种具体实现方式可以是：在剩余的塑封层上形成第二重布线层，第一导体柱103和第二导体柱202分别与第二重布线层连通。
应理解，若载片600上包括第一重布线层601和第三导体柱602，则第三导体柱602被电连接至载板30，以实现载板30和第一重布线层601的耦合。
S12：去除载片600，得到芯片封装结构。
可选地，S12之后，对于线路载片60来说，该方法还可以包括：
S14：通过第二互连结构70将第三芯片80与第一重布线层601进行互连。
其中，互连的具体实现方式同S06中互连的具体实现，可以参见上述S06中相关描述，本申请实施例不再赘述。
应理解，第二互连结构70可以包括至少一个焊球、焊盘、金属凸点、金属柱等，本申请实施例不作限定。
需要说明的是，若第二芯片20直接粘结在载片600上，通过S8的实现方式一、S10和S12之后，可以得到如图3所示的芯片封装结构。
若第二芯片20直接粘结在载片600上，通过S8的实现方式二、S10和S12之后，可以得到如图2所示的芯片封装结构。
若第二芯片20直接粘结在载片600上，通过S8的实现方式三、S10和S12之后，可以得到如图4所示的芯片封装结构。
若第二芯片20粘结在载片600的第一重布线层601上，通过S8的实现方式一、S10、S12和S14之后，可以得到如图5或图6所示的芯片封装结构。
同理，若第二芯片20粘结在载片600的第一重布线层601上，通过S8的实现方式中任意一种实现方式、S10、S12、S14之后，还可以得到其他结构的芯片封装结构，此处不再赘述。
需要说明的是，上述各个层结构的制备方法可以参见现有技术中材料的制备方法，本申请实施例不再赘述。
还需要说明的是，图案化工艺可以包括但不限于光刻工艺、3D打印技术、丝印等，其中，光刻工艺包括形成光刻胶层，通过光罩部分曝光光刻胶层、利用显影液显影得待图案化的光刻胶层，以图案化的光刻胶层为掩膜设于光刻胶层下的材料进行刻蚀等步骤。
刻蚀工艺包括干刻工艺、湿刻工艺、反应刻蚀工艺等。应理解，针对被刻蚀的材料和 该材料所处的环境可以选择适当的刻蚀工艺。
研磨、化学机械抛光(chemical mechanical planarization，CMP)等为平坦化工艺，通过研磨或抛光可以得到平坦化的层结构。
第一互连结构102、第二互连结构70、第三互连结构50等互连结构可以包括至少一个焊球、至少一个金属凸点或至少一个金属柱等，对此，本申请实施例不作限定。互连的方法包括但不限于热压键合(thermal compression bonding)、共晶键合(eutectic bonding)、埋入型凸点互连(embedded bump bonding)、金属-金属直接键合(metal-metal direct bonding)、混合键合(hybrid bonding)等。
介质层的材料包括但不限于是聚酰亚胺(polyimide，PI)、聚苯并唑(ploybenzoxazole，PBO)、苯并环丁烯(BCB)、环氧成型模料(Epoxy Molding Compound,EMC)等高分子绝缘材料，或者氮化硅、氧化硅、碳化硅等无机绝缘材料。
第一导体柱103、第二导体柱202、第三导体柱602等导体柱可以是金属材料形成的金属柱，比如铜柱(copper pillar)、铝柱、银柱、钯柱等，也可以是其他导电材料形成的柱状体，本申请实施例不作限定。导体柱通常采用镀膜的方法制备，其高度可以精确控制。
塑封层40的材质可以环氧树脂(Epoxy Molding Compound，EMC)、聚乙烯、聚丙烯、聚烯烃、聚酰胺、聚亚氨酯等中的一种或多种的组合。塑封层40的成型过程可以是，将低粘度的塑封层40滴灌在载片600和第二芯片20的表面，低粘度的塑封层40填充芯片与载片600之间的空隙，并包裹第一芯片11/12和第二芯片20，当低粘度的塑封层40的厚度达到预设厚度之后，对低粘度的塑封层40进行加热固化，形成塑封层40。
旋涂法(spin coating)为一种薄膜形成工艺，可以用于形成塑封层40、光刻胶层等。旋涂工艺通常包括配料，高速旋转，挥发成膜三个步骤，通过控制匀胶的时间，转速，滴液量以及所用溶液的浓度、粘度来控制成膜的厚度。
介质层104可以是有机绝缘材料例如，可以是环氧树脂、聚乙烯等，也可以是无机绝缘材料，例如氮化硅、碳化硅等，介质层104的制备工艺包括但不限于物理气相沉积法、化学气相沉积法等薄膜制备工艺，可以通过介质层104的材料选择合适的制备工艺，具体不再赘述。
本申请中，第二重布线层、第一重布线层601等重布线层可以包括至少一层图案化的导电材料以及隔离图案化的导电材料的绝缘材料，该导电材料可以是金属，如铜(Cu)、银(Ag)、铝(Al)或其他金属或金属的合金等，该导电材料还可以是氧化铟锡(ITO)、石墨、石墨烯等，本申请实施例不作限定。绝缘材料可以是无机绝缘材料或有机绝缘材料，等，本申请实施例不作限定。
上述芯片封装结构或芯片封装方法制备形成的芯片封装结构，进一步地可以应用于集成电路中。该集成电路包括：印制电路板和芯片封装结构，其中，芯片封装结构中载板与印制电路板耦合。该芯片封装结构为上述实施例中任意一种芯片封装结构。图10是本申请实施例提供的一种集成电路的结构示意图，图10以图5所示的芯片封装结构500为例来说明，芯片封装结构500中载板30通过第三互连结构50与印制电路板1001互连，以实现印制电路板1001向芯片封装结构500中芯片供电、印制电路板1001上的电路与芯片封装结构500的电路的连通。芯片封装结构的具体实现可以参见上述图2-图7中相关描述，本申 请实施例不再赘述。
在一种具体实现中，集成电路可以集成有中央处理器(central processing unit，CPU)、存储器等。
上述芯片封装结构、芯片封装方法制备形成的芯片封装结构或集成电路，进一步地可以应用于集成电路设备中。请参阅图11，图11是本申请实施例提供的一种集成电路设备的结构示意图，该集成电路设备包括集成电路1101，该集成电路1101可以是图10所示的集成电路，具体可参见图10所述的集成电路中相关描述，本申请实施例不再赘述。
在一种具体实现中，集成电路1101可以集成有CPU、存储器等。可选地，该集成电路设备还可以包括电源管理模块1102，用于对集成电路1101进行供电。可选地，该集成电路设备还可以包括通信模块1103、输入模块1104和/或输出模块1105等。其中，通信模块1103用于实现集成电路设备与其他设备或互连网的通信连接；输入模块1104用于实现用户将信息输入到集成电路设备，可以包括，触控面板、键盘、摄像头等；输出模块1105用于实现集成电路设备向用户输出信息，可以包括显示面板等。应理解，电源管理模块1102、通信模块1103、输入模块1104和/或输出模块1105不是集成电路设备必须的组成部件；电源管理模块1102、通信模块1103、输入模块1104和/或输出模块1105也可以集成在集成电路1101中，或单独设置，耦合至集成电路1101，本申请实施例不做限定。
本申请实施例中集成电路设备可以是包括集成电路1101的电子设备，如智能手机、平板电脑、个人数字助理、电子书、计算机、服务器、智能手环、虚拟现实(VirtualReality，VR)设备、增强现实(Augmented Reality，简称AR)设备、数字电视、机顶盒等。应理解，这里所列举的电子设备仅为示例性说明，本申请对此不作限定。
以上不同实施例之间可以交叉引用。例如当一个实施例对某一方面的技术细节做了简略描述，可进一步参考其他实施例的介绍。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，上述列举的芯片封装方法的各实施例，可以通过机器人或者数控加工方式来执行，用于执行芯片封装方法的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述芯片封装方法。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种芯片封装结构，其特征在于，包括：第一芯片、第二芯片和载板，其中，所述第一芯片设置于所述第二芯片和所述载板之间，所述第一芯片的有源层和所述第二芯片的有源层相对，所述第一芯片和所述第二芯片之间设置有第一互连结构，用于连通所述第一芯片的有源层和所述第二芯片的有源层，所述第一芯片的内部设有第一导体柱，所述第一导体柱的一端与所述第一芯片的有源层连通，所述第一导体柱的另一端穿过所述第一芯片与所述载板中的电路连通。
  2. 如权利要求1所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第二导体柱，所述第二导体柱的一端与所述第二芯片的有源层连通，所述第二导体柱的另一端与所述载板中的电路连通。
  3. 如权利要求1或2所述的芯片封装结构，其特征在于，所述第一芯片背离所述第二芯片的表面上设有介质层，所述第一导体柱穿过所述介质层。
  4. 如权利要求1或2所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：设于所述载板和所述第二芯片之间的塑封层，所述第一导体柱穿过所述塑封层，所述第二导体柱穿过所述塑封层。
  5. 如权利要求1-4任一项所述的芯片封装结构，其特征在于，所述第一导体柱背离所述第二芯片的端面和所述第二导体柱背离所述第二芯片的端面齐平。
  6. 如权利要求1-5任一项所述的芯片封装结构，其特征在于，所述第一互连结构包括至少一个焊球、至少一个金属凸点或至少一个金属柱。
  7. 如权利要求1-6任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：第一重布线层、第二互连结构、第三芯片和第三导体柱，其中，所述第一重布线层设于所述第二芯片背离所述第一芯片的表面，所述第三芯片设于所述第一重布线层背离所述第一芯片的表面，所述第三芯片通过第二互连结构与所述第一重布线层连通；所述第三导体柱的一端与所述载板中的电路连通，所述第三导体柱的另一端与所述中的电路连通。
  8. 如权利要求7所述的芯片封装结构，其特征在于，所述第一导体柱背离所述第二芯片的端面、所述第二导体柱背离所述第二芯片的端面和所述第三导体柱背离所述的端面齐平。
  9. 如权利要求1-8任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第三互连结构，所述第三互连结构设置于所述载板背离所述第一芯片表面，所述第三互 连结构用于连通所述载板中的电路和印制电路板上的电路。
  10. 一种集成电路，其特征在于，包括印制电路板以及如权利要求1-7任一项所述的芯片封装结构，其中，所述芯片封装结构中的载板与所述印制电路板连通。
  11. 一种集成电路设备，其特征在于，包括如权利要求8所示的任意一种集成电路。
  12. 一种芯片封装方法，其特征在于，包括：
    提供一载片、至少一个第一芯片、第二芯片，其中，所述第一芯片的内部设有第一导体柱；
    将所述第二芯片的背面粘结在所述载片上，所述第二芯片的背面为所述第二芯片上背离所述第二芯片的有源层的表面；
    通过第一互连结构将所述第一芯片的有源层与所述第二芯片的有源层连通；
    在所述载片、所述第二芯片和所述第一芯片上形成塑封层；
    去除部分的所述塑封层，以显露所述第一导体柱背离所述第二芯片的端面；
    将载板与所述第一导体柱背离所述第一芯片的端面与载板连通；
    去除所述载片，得到芯片封装结构。
  13. 如权利要求12所述的方法，其特征在于，所述第二芯片的有源层的表面设有第二导体柱；所述方法还包括：
    去除部分的所述塑封层，以显露所述第二导体柱背离所述第二芯片的端面；
    将载板与所述第二导体柱背离所述第二芯片的端面连通。
  14. 如权利要求12或13所述的方法，其特征在于，所述通过第一互连结构将所述第一芯片的有源层与所述第二芯片的有源层连通，具体包括：
    通过热压键合、共晶键合、埋入型凸点互连、金属-金属直接键合、混合键合中的至少一种将所述第一芯片的有源层与所述第二芯片的有源层通过第一互连结构连通。
  15. 如权利要求13或14所述的方法，其特征在于，所述去除部分的所述塑封层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面，具体包括：
    去除设于所述第一芯片的背面上的部分的所述塑封层，裸露所述第一芯片的背面，所述第一芯片的背面为所述第一芯片上背对所述第一芯片的有源层的表面；
    去除部分的所述第一芯片的背面的材料，以裸露预设长度的所述第一导体柱；
    形成覆盖所述第一芯片和所述第一导体柱的介质层；
    去除部分的所述塑封层和部分的所述介质层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面。
  16. 如权利要求12-14任一项所述的方法，其特征在于，所述在所述载片、所述第二芯片和所述第一芯片上形成塑封层之前，所述方法还包括：
    形成覆盖所述载片、所述第二芯片和所述第一芯片的第一光刻胶层；
    图案化所述第一光刻胶层，以裸露所述第一芯片的背面，所述第一芯片的背面为所述第一芯片上背对所述第一芯片的有源层的表面；
    以图案化的第一光刻胶层为掩膜，去除所述第一芯片的背面上的部分的材料，以裸露预设长度的所述第一导体柱；
    去除所述图案化的第一光刻胶。
  17. 如权利要求12-14任一项或16所述的方法，其特征在于，所述去除部分的所述塑封层，以裸露所述第一导体柱背离所述第二芯片的端面以及所述第二导体柱背离所述第二芯片的端面，具体包括：
    在所述塑封层相对所述第一导体柱的位置开设第一过孔，以裸露所述第一导体柱背离所述第二芯片的端面；以及，在在所述塑封层相对所述第二导体柱的位置分别开设第二过孔，以裸露所述第二导体柱背离所述第二芯片的端面。
  18. 如权利要求12-17任一项所述的方法，其特征在于，所述将所述第二芯片的背面粘结在所述载片上之前，所述方法还包括：在所述载片上依次形成第一重布线层、第三导体柱，其中，第三导体柱设置于第一重布线层背离所述载片的表面，所述第三导体柱的一端与所述第一重布线层连通；
    所述将所述第二芯片的背面粘结在所述载片上，具体包括：将所述第二芯片的非有源层粘结在第一重布线层背离所述载片的表面；
    所述在所述塑封层上形成载板之前，所述方法还包括：在所述塑封层相对所述第三导体柱的位置开设第三过孔，以显露所述第三导体柱背离所述第一重布线层的端面；
    在所述塑封层上形成载板之后，所述第三导体柱的另一端与所述载板连通。
  19. 如权利要求18所述的方法，其特征在于，所述去除所述载片之后，所述方法还包括：通过第二互连结构将所述第三芯片与所述第一重布线层连通。
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