CN113826200A - 芯片封装结构及芯片封装方法 - Google Patents

芯片封装结构及芯片封装方法 Download PDF

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CN113826200A
CN113826200A CN201980096458.2A CN201980096458A CN113826200A CN 113826200 A CN113826200 A CN 113826200A CN 201980096458 A CN201980096458 A CN 201980096458A CN 113826200 A CN113826200 A CN 113826200A
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chip
layer
conductor
pillar
conductor pillar
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张童龙
张晓东
官勇
李珩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

一种芯片封装结构及芯片封装方法，该芯片封装结构包括至少一个第一芯片(10)、第二芯片(20)和载板(30)，其中，第一芯片(10)设置于第二芯片(20)和载板(30)之间，第一芯片(10)的有源层(101)和第二芯片(20)的有源层(201)相对，第一芯片(10)和第二芯片(20)之间设置有第一互连结构(102)，用于连通第一芯片(10)的有源层(101)和第二芯片(20)的有源层(201)，第一芯片(10)的内部设有第一导体柱(103)，该第一导体柱(103)的一端与第一芯片(10)的有源层(101)连通，第一导体柱(103)的另一端穿过第一芯片(10)与载板(30)中的电路连通。通过将两个芯片的有源层进行面对面连接，缩短两个芯片之间信号传输的线路，提高两个芯片之间的信号传输效率。

Description

PCT国内申请，说明书已公开。

Claims (19)

  1. PCT国内申请，权利要求书已公开。
CN201980096458.2A 2019-05-20 2019-05-20 芯片封装结构及芯片封装方法 Pending CN113826200A (zh)

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