WO2024007407A1 - 半导体封装组件及制备方法 - Google Patents

半导体封装组件及制备方法 Download PDF

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Publication number
WO2024007407A1
WO2024007407A1 PCT/CN2022/110303 CN2022110303W WO2024007407A1 WO 2024007407 A1 WO2024007407 A1 WO 2024007407A1 CN 2022110303 W CN2022110303 W CN 2022110303W WO 2024007407 A1 WO2024007407 A1 WO 2024007407A1
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Prior art keywords
substrate
interposer
solder ball
packaging
interconnection
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PCT/CN2022/110303
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English (en)
French (fr)
Inventor
孙晓飞
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22790428.1A priority Critical patent/EP4325557A1/en
Priority to KR1020227039107A priority patent/KR20240007732A/ko
Priority to US17/952,404 priority patent/US20230014357A1/en
Publication of WO2024007407A1 publication Critical patent/WO2024007407A1/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor packaging component and a preparation method.
  • embodiments of the present disclosure provide a semiconductor packaging component and a manufacturing method.
  • a semiconductor packaging component including:
  • a first chip structure, the first chip structure is located on the substrate and is electrically connected to the first surface of the substrate;
  • the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, and a first solder ball is formed on the first interconnection area, so A first bonding pad is formed on the second interconnection area, and the interposer is electrically connected to the first surface of the substrate through the first bonding pad;
  • the plastic packaging material seals the first chip structure, the interposer layer and the first side of the substrate, wherein the first solder ball has a surface exposed to the plastic packaging material, the first There is a preset height between the exposed surface of the solder ball and the first interconnection surface of the interposer.
  • the first chip structure includes a plurality of first semiconductor chips sequentially stacked in a direction perpendicular to the substrate;
  • the interposer is located on the first chip structure.
  • it also includes:
  • each of the first semiconductor chips is electrically connected to the substrate through the first conductive lines;
  • the second interconnection area is electrically connected to the substrate through the second conductive lines.
  • a plurality of second bonding pads are formed on the first interconnection area, wherein the number of the first bonding pads is greater than the number of the second bonding pads, and the number of the first bonding pads is The area is smaller than the area of the second bonding pad.
  • the first chip structure includes a plurality of first semiconductor chips sequentially arranged in a direction parallel to the substrate;
  • the first chip structure is located on the interposer layer.
  • it also includes:
  • a first conductive block is located between the first semiconductor chip and the interposer, and each first semiconductor chip is electrically connected to the substrate through the first conductive block;
  • a second conductive block is located between the interposer layer and the substrate, and the interposer layer is electrically connected to the substrate through the second conductive block.
  • it also includes:
  • the second packaging structure includes a second solder ball, and the second packaging structure is electrically connected to the first solder ball through the second solder ball.
  • the volume of the first solder ball is greater than the volume of the second solder ball.
  • the plastic compound has a first thickness in a direction perpendicular to the substrate
  • the second packaging structure includes a second plastic compound, and the second plastic compound has a second thickness in a direction perpendicular to the substrate; wherein the first thickness is greater than or equal to the second thickness.
  • a method for manufacturing a semiconductor packaging component including:
  • a first chip structure is formed on the substrate, and the first chip structure is electrically connected to the first surface of the substrate;
  • the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, and a first solder ball is formed on the first interconnection area, A first bonding pad is formed on the second interconnection area, and the interposer is electrically connected to the first surface of the substrate through the first bonding pad;
  • the plastic compound seals the first chip structure, the interposer layer and the first side of the substrate, wherein the first solder ball has a surface exposed to the plastic compound, and the third solder ball has a surface exposed to the plastic compound. There is a preset height between the exposed surface of a solder ball and the first interconnection surface of the interposer.
  • forming the plastic compound includes:
  • the surface of the first packaging mold is parallel to the surface of the substrate, the first packaging mold is located above the first chip structure and the interposer, and is in contact with the first chip There is a distance between the structure and said interposer;
  • Part of the pre-layer of plastic encapsulation material is removed to form a plastic encapsulation material and expose the surface of the first solder ball.
  • forming the first chip structure includes: forming a plurality of first semiconductor chips stacked sequentially in a direction perpendicular to the substrate;
  • An interposer layer is formed on the first chip structure.
  • it also includes:
  • each first semiconductor chip is electrically connected to the substrate through the first conductive line;
  • a second conductive line is formed; the second interconnection area is electrically connected to the substrate through the second conductive line.
  • it also includes:
  • a plurality of second bonding pads are formed on the first interconnection area, wherein the number of the first bonding pads is greater than the number of the second bonding pads, and the area of the first bonding pads is smaller than the area of the second bonding pads. The area of the soldering pad.
  • forming a first chip structure on the interposer forming a first chip structure on the interposer
  • the forming the first chip structure includes: forming a plurality of first semiconductor chips arranged in sequence in a direction parallel to the substrate.
  • it also includes:
  • a second conductive block is formed on the substrate, and an intermediary layer is formed on the second conductive block; the interposer layer is electrically connected to the substrate through the second conductive block;
  • a first conductive block is formed on the interposer, and a first chip structure is formed on the first conductive block; each of the first semiconductor chips is connected to the first conductive block through the first conductive block. electrical connections between substrates.
  • it also includes:
  • a second packaging structure is formed, the second packaging structure includes a second solder ball, and the second packaging structure is electrically connected to the first solder ball through the second solder ball.
  • the volume of the first solder ball is greater than the volume of the second solder ball.
  • the plastic compound has a first thickness in a direction perpendicular to the substrate
  • the second packaging structure includes a second plastic compound, and the second plastic compound has a second thickness in a direction perpendicular to the substrate; wherein the first thickness is greater than or equal to the second thickness.
  • the subsequent second package structure can be connected to the first chip structure and the substrate through the first solder ball on the interposer.
  • first solder ball on the interposer.
  • connections make the combination of different structures more flexible.
  • the first chip structure and the second packaging structure are independently packaged, it is easier to perform testing and failure analysis.
  • there is a preset height between the top surface of the first solder ball and the first interconnection surface which can ensure that the entire package structure has a relatively thin overall thickness and is relatively thinner than the subsequent second package structure. Good bonding power.
  • Figure 1 is a schematic structural diagram of a semiconductor packaging component provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a substrate provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a semiconductor packaging component provided by another embodiment of the present disclosure.
  • Figure 4 is a schematic flowchart of a method for manufacturing a semiconductor packaging component according to an embodiment of the present disclosure
  • 5a to 5h are schematic diagrams of the device structure during the preparation process of the semiconductor package component provided by the embodiment of the present disclosure.
  • 6a to 6f are schematic diagrams of the device structure during the preparation process of a semiconductor package component provided by another embodiment of the present disclosure.
  • 30-interposer 301-first interconnection surface; 31-first interconnection area; 32-second interconnection area; 311-second solder pad; 312-first solder ball; 312'-initial first solder Ball; 321-first bonding pad; 33-intermediate substrate; 34-insulating dielectric layer on the intermediary; 35-insulating dielectric layer under the intermediary; 322-second conductive block;
  • FIG. 1 is a schematic structural diagram of a semiconductor packaging component provided by an embodiment of the present disclosure.
  • the semiconductor packaging component includes:
  • Substrate 10 said substrate having a first surface 101;
  • the first chip structure 20 is located on the substrate 10 and is electrically connected to the first surface 101 of the substrate 10;
  • Interposer layer 30 said interposer layer 30 has a first interconnection surface 301, said first interconnection surface 301 has a first interconnection area 31 and a second interconnection area 32, said first interconnection area 31 is formed There are first solder balls 312 , and a first solder pad 321 is formed on the second interconnection area 32 .
  • the interposer 30 is electrically connected to the first surface 101 of the substrate 10 through the first solder pad 321 . connect;
  • Plastic compound 40 the plastic compound 40 seals the first chip structure 20 , the interposer 30 and the first side 101 of the substrate 10 , wherein the first solder ball 312 has a surface exposed to the plastic compound. 40, there is a preset height h between the exposed surface of the first solder ball 312 and the first interconnection surface 301 of the interposer 30.
  • the subsequent second package structure can be connected to the first chip structure and the substrate through the first solder ball on the interposer.
  • the interposer can be made of non-organic materials, For example, a silicon interposer or a structure composed of any one or more organic materials. Through the setting of the intermediary layer, the interconnection between structures of different types or different specifications can be realized, making the combination of different structures more flexible. At the same time, because the first chip structure and the second packaging structure are independently packaged, it is easier to perform testing and failure analysis.
  • the preset height h is not less than 1/5-1/2 of the thickness of the interposer. In some cases, if the thickness of the interposer is 100-200 ⁇ m, then the preset height h is 50-120 ⁇ m. Through such a setting, the stress problem caused by the mismatch in thermal expansion coefficient between the plastic compound and the interposer can be effectively suppressed. On the basis of ensuring that the entire packaging structure has a relatively thin overall thickness, it also has relatively good bonding force with the subsequent second packaging structure.
  • FIG. 2 is a schematic structural diagram of a substrate provided by an embodiment of the present disclosure.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the first surface 101 of the substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate.
  • the substrate 10 further includes a second surface 102 that is away from the first surface 101 .
  • the second surface 102 is the lower surface of the insulating dielectric layer 13 under the substrate.
  • the substrate 10 also includes an on-substrate connection pad 14 located in the insulating dielectric layer 12 on the substrate, an under-substrate connection pad 15 located in the under-substrate insulating dielectric layer 13 , and a substrate 11 extending through the substrate.
  • the substrate connection through hole 16 connects the upper substrate connection pad 14 and the lower substrate connection pad 15 to each other.
  • connection pad 14 on the substrate and the connection pad 15 under the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate connection via 16 may be a through silicon via (TSV).
  • the substrate 10 further includes substrate connection bumps 17 located on the second surface 102 of the substrate 10 .
  • the substrate connection bump 17 can electrically connect the semiconductor package component to an external device, can receive at least one of a control signal, a power signal and a ground signal for operating the first chip structure from the external device, or can receive from the external device By receiving a data signal to be stored in the first chip structure, the data in the first chip structure may also be provided to an external device.
  • the substrate connection bumps 17 include electrically conductive material.
  • the substrate connection bumps 17 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only used as a reference in the embodiment of the present disclosure. is a lower and feasible specific implementation, and does not constitute a limitation on the present disclosure.
  • the substrate connection bumps can also be of other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.
  • the substrate 10 further includes a first signal transmission area 110 and a second signal transmission area 120 respectively located on opposite sides of the substrate 10 .
  • the first signal transmission area 110 is electrically connected to the first chip structure 20, and the second signal transmission area 120 is electrically connected to the interposer layer 30,
  • the substrate 10 further includes a third signal transmission area 130 located between the first signal transmission area 110 and the second signal transmission area 120 , and the first chip structure 20 is located on the third signal transmission area 130 .
  • the interposer 30 is located above the first chip structure 20
  • the other is as shown in FIG. 3
  • the first chip structure 20 is located above the interposer layer 30 .
  • the first chip structure 20 includes a plurality of first semiconductor chips 21 sequentially stacked in a direction perpendicular to the substrate 10 ; the interposer 30 is located in the first chip structure. 20 on.
  • the horizontal area of the semiconductor package component can be saved.
  • the first semiconductor chip may be a DRAM chip or other types of semiconductor chips.
  • the semiconductor packaging component also includes:
  • First conductive lines 51 each of the first semiconductor chips 21 is electrically connected to the substrate 10 through the first conductive lines 51;
  • Second conductive lines 52 the second interconnection area 32 is electrically connected to the substrate 10 through the second conductive lines 52 .
  • the first semiconductor chip 21 has a first connection terminal 211.
  • the first connection terminal 211 is located on the same side as the first signal transmission area 110.
  • a first conductive wire is drawn from the first connection terminal 211.
  • the wire 51 is connected to the first transmission area 110 to realize the electrical connection between the first semiconductor chip 21 and the substrate 10 .
  • a first bonding pad 321 is formed on the second interconnection area 32 , and a second conductive line 52 is led from the first bonding pad 321 to the second transmission area 120 to realize the connection between the interposer 30 and the substrate 10 electrical connection between them.
  • the wire bonding method for electrical connection between the first chip structure and the substrate includes an overhang method and a film on wire (FOW) method.
  • wire bonding is performed using an overhang method.
  • Two adjacent first semiconductor chips 21 are connected through an adhesive film 60.
  • the adhesive film 60 does not cover the first connection end 211 and the first conductive line 51 on the first semiconductor chip 21 below it.
  • the adhesive film 60 is misaligned with the first semiconductor chip 21 one layer below it.
  • a wire-on-wire coating method is used for wire bonding (not shown).
  • a plurality of first semiconductor chips are aligned in a direction perpendicular to the substrate, and the adhesive film between two adjacent first semiconductor chips covers the first connection end on the first semiconductor chip one layer below and First wire line.
  • leads for electrical connection in the embodiments of the present disclosure is only a lower and feasible implementation method in the embodiments of the present disclosure, and does not constitute a limitation on the present disclosure. Other methods can also be used. Electrical connections, such as hybrid bonding or bump interconnects.
  • the interposer layer 30 includes an interposer substrate 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper surface and the lower surface of the interposer substrate 33 .
  • the interposer substrate 33 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be made of green paint.
  • a plurality of second bonding pads 311 are formed on the first interconnection area 31 of the interposer 30 , wherein the number of the first bonding pads 321 is greater than the number of the second bonding pads 311 .
  • the area of the pad 321 is smaller than the area of the second bonding pad 311 .
  • the layout design is relatively fixed, while the first bonding pad carries the interconnection between the second package structure and the substrate, so the layout design is more flexible.
  • the first bonding pads are designed to be larger in number and smaller in area, which can improve signal transmission efficiency.
  • the material of the first bonding pad 321 and the second bonding pad 311 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the first chip structure 20 includes a plurality of first semiconductor chips 21 sequentially arranged in a direction parallel to the substrate 10 ; the first chip structure 20 is located in the intermediary On level 30.
  • the packaging height of the semiconductor package component can be reduced.
  • the semiconductor package component further includes: a first conductive block 201 located between the first semiconductor chip 21 and the interposer 30 .
  • Each of the first semiconductor chips 21 passes through the first conductive block 201 .
  • the conductive block 201 is electrically connected to the substrate 10; the second conductive block 322 is located between the interposer 30 and the substrate 10, and the interposer 30 is connected to the substrate through the second conductive block 322. 10 electrical connections.
  • the first semiconductor chip is interconnected with the interposer through the first conductive block, and the interposer is interconnected with the substrate. Therefore, the first semiconductor chip is connected with the substrate through the first conductive block and the interposer.
  • the area of the first bonding pad 321 is larger than the area of the second bonding pad 311 .
  • the second interconnection area no longer mainly carries the communication between other packaging structures and the substrate. Therefore, the first bonding pad can use a large area of metal, increasing the heat dissipation area to improve heat dissipation efficiency.
  • the semiconductor packaging component further includes: a second packaging structure 70 , the second packaging structure 70 includes a second solder ball 71 , and the second packaging structure 70 passes through the second solder ball 71 .
  • the solder ball 71 is electrically connected to the first solder ball 312 .
  • the volume of the first solder ball 312 is larger than the volume of the second solder ball 71 .
  • the first solder ball 312 and the second solder ball 71 prevent the lateral flow of solder during the subsequent reflow soldering process, reduce the risk of short circuit between adjacent solder balls, and improve the quality of the first solder ball and the second solder ball. Ball joint strength.
  • the plastic molding compound 40 In a direction perpendicular to the substrate 10 , the plastic molding compound 40 has a first thickness; the second packaging structure 70 includes a second plastic molding compound 73 , and in a direction perpendicular to the substrate 10 , the second molding compound 40 has a first thickness.
  • the plastic molding material 73 has a second thickness; wherein the first thickness is greater than or equal to the second thickness. Since the thickness of the plastic molding material 40 is relatively large, it can fully support the second packaging structure and prevent the first packaging structure from warping toward the second packaging structure.
  • the second packaging structure 70 further includes a second substrate 72.
  • the structure of the second substrate 72 may be the same as or different from the structure of the substrate 10, which will not be described again here.
  • the second packaging structure includes a second chip structure (not shown), and the second chip structure may be a universal flash memory chip (Universal File Store, UFS).
  • UFS Universal File Store
  • the semiconductor packaging component provided by the embodiment of the present disclosure can be applied to a multi-chip package (UFS Multi Chip Package, UMCP) with a package on package (Package on Package, PoP) structure.
  • UFS Multi Chip Package UMCP
  • PoP package on Package
  • the top surface of the plastic packaging material is coplanar with the top surface of the first solder ball. Therefore, when forming the plastic packaging material, a normal packaging mold can be used for packaging without forming a special-shaped packaging mold.
  • the production cost of special-shaped packaging molds is high and the process is more complicated. Therefore, the semiconductor packaging component provided by the embodiment of the present disclosure can reduce the cost and the formation process is simpler.
  • An embodiment of the present disclosure also provides a method for preparing a semiconductor packaging component. Please refer to Figure 4 for details. As shown in the figure, the method includes the following steps:
  • Step 401 Provide a substrate, the substrate having a first side;
  • Step 402 Form a first chip structure on the substrate, and the first chip structure is electrically connected to the first surface of the substrate;
  • Step 403 Form an interposer layer; the interposer layer has a first interconnection surface, the first interconnection surface has a first interconnection area and a second interconnection area, and a first interconnection area is formed on the first interconnection area. Solder ball, a first soldering pad is formed on the second interconnection area, and the interposer is electrically connected to the first surface of the substrate through the first soldering pad;
  • Step 404 Form a plastic compound that seals the first chip structure, the interposer and the first side of the substrate, wherein the first solder ball has a surface exposed to the plastic compound, There is a preset height between the exposed surface of the first solder ball and the first interconnection surface of the interposer.
  • FIGS. 5a to 5h are schematic diagrams of the device structure of a semiconductor package component during the preparation process according to an embodiment of the present disclosure.
  • FIGS. 6a to 6e are schematic diagrams of the device structure of a semiconductor package component during the preparation process according to another embodiment of the present disclosure. It should be explained that in the method of manufacturing the semiconductor package component shown in Figures 5a to 5h, the first chip structure is formed first, and then the interposer is formed, while in the method of manufacturing the semiconductor package component shown in Figures 6a to 6e, The interposer layer is formed first, and then the first chip structure is formed.
  • FIG. 5a to FIG. 5h one embodiment of the method for manufacturing the semiconductor package component will be described in detail.
  • step 401 is performed to provide a substrate 10 having a first side 101 .
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a base substrate 11 and an upper-substrate insulating dielectric layer 12 and a lower-substrate insulating dielectric layer 13 respectively disposed on the upper surface and lower surface of the base substrate 11 .
  • the substrate substrate 11 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be made of green paint.
  • the first surface 101 of the substrate 10 is the upper surface of the insulating dielectric layer 12 on the substrate.
  • the substrate 10 further includes a second surface 102 that is away from the first surface 101 .
  • the second surface 102 is the lower surface of the insulating dielectric layer 13 under the substrate.
  • the substrate 10 also includes an on-substrate connection pad 14 located in the insulating dielectric layer 12 on the substrate, an under-substrate connection pad 15 located in the under-substrate insulating dielectric layer 13 , and a substrate 11 extending through the substrate.
  • the substrate connection through hole 16 connects the upper substrate connection pad 14 and the lower substrate connection pad 15 to each other.
  • connection pad 14 on the substrate and the connection pad 15 under the substrate may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the substrate connection via 16 may be a through silicon via (TSV).
  • the substrate 10 further includes a first signal transmission area 110 and a second signal transmission area 120 respectively located on opposite sides of the substrate 10 .
  • the first signal transmission area 110 is electrically connected to the first chip structure formed subsequently
  • the second signal transmission area 120 is electrically connected to the interposer formed subsequently.
  • the first signal transmission area 110 and the second signal transmission area 120 are not interconnected.
  • the substrate 10 further includes a third signal transmission area 130 located between the first signal transmission area 110 and the second signal transmission area 120 , and the first chip structure is located on the third signal transmission area 130 .
  • the first signal transmission area 110 and the third signal transmission area 130 are interconnected, and the third signal transmission area 130 and the second signal transmission area 120 are not interconnected.
  • step 402 is performed to form a first chip structure 20 on the substrate 10 , and the first chip structure 20 is electrically connected to the first surface 101 of the substrate 10 .
  • forming the first chip structure 20 includes forming a plurality of first semiconductor chips 21 stacked in sequence in a direction perpendicular to the substrate 10 . In this embodiment, by stacking a plurality of first semiconductor chips upward in sequence, the horizontal area of the semiconductor package component can be saved.
  • an adhesive film 60 is formed on the substrate 10 first, and then the first chip structure 20 is formed on the adhesive film 60 . Two adjacent first semiconductor chips 21 are connected through an adhesive film 60 .
  • step 403 is performed to form an interposer layer 30;
  • the interposer layer 30 has a first interconnection surface 301, and the first interconnection surface 301 has a first interconnection area 31 and a second interconnection area.
  • the first interconnection area 32 has a first solder ball 312 formed on the first interconnection area 31 , a first solder pad 321 is formed on the second interconnection area 32 , and the interposer 30 passes through the first solder pad. 321 is electrically connected to the first surface 101 of the substrate 10 .
  • the carrier tape 2 is pasted on the ring 1, and then the adhesive film 60 is pasted on the carrier tape 2, and then the intermediary layer is pasted on the adhesive film 60.
  • the intermediary layer is the entire
  • the interposer is cut into strips to form units one by one as shown in Figure 8c.
  • an interposer layer 30 is formed on the first chip structure 20 .
  • the single interposer layer 30 formed in FIG. 5c is attached to the first chip structure 20 .
  • an initial first solder ball 312 ′ is first formed on the first interconnection region 31 of the interposer 30 , and is subsequently etched or polished to form a first solder ball 312 ′.
  • the initial first solder ball 312&apos has an initial height in a direction perpendicular to the interposer 30.
  • the interposer layer 30 includes an interposer substrate 33 and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 respectively disposed on the upper surface and the lower surface of the interposer substrate 33 .
  • the interposer substrate 33 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate.
  • the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked layer Structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers.
  • the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be made of green paint.
  • the method further includes: forming a plurality of second bonding pads 311 on the first interconnection area 31 , wherein the number of the first bonding pads 321 is greater than the number of the second bonding pads 311 . quantity, the area of the first bonding pad 321 is smaller than the area of the second bonding pad 311 .
  • the layout design is relatively fixed, while the first bonding pad carries the interconnection between the second package structure and the substrate, so the layout design is more flexible.
  • the first bonding pads are designed to be larger in number and smaller in area, which can improve signal transmission efficiency.
  • the material of the first bonding pad 321 and the second bonding pad 311 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the method further includes: after forming the interposer 30, forming a first conductive line 51; each first semiconductor chip 21 is electrically connected to the substrate 10 through the first conductive line 51. Connect; form a second conductive line 52; the second interconnection area 32 is electrically connected to the substrate 10 through the second conductive line 52.
  • a first connection terminal 211 is formed on the first semiconductor chip 21 , and the first connection terminal 211 is located on the same side as the first signal transmission area 110 , and a first connection terminal 211 is led out from the first connection terminal 211 .
  • a conductive line 51 is connected to the first transmission area 110 to achieve electrical connection between the first semiconductor chip 21 and the substrate 10 .
  • a first bonding pad 321 is formed on the second interconnection area 32 , and a second conductive line 52 is led from the first bonding pad 321 to the second transmission area 120 to realize the connection between the interposer 30 and the substrate 10 electrical connection between them.
  • step 404 is performed to form a plastic compound 40 that seals the first chip structure 20 , the interposer 30 and the first surface 101 of the substrate 10 , wherein,
  • the first solder ball 312 has a surface exposed to the plastic compound 40 , and there is a preset height h between the exposed surface of the first solder ball 312 and the first interconnection surface 301 of the interposer 30 .
  • the forming of the plastic sealant 40 includes:
  • a first packaging mold 91 is formed, the surface of the first packaging mold 91 is parallel to the surface of the substrate 10 , the first packaging mold 91 is located above the first chip structure 20 and the interposer 30 , and There is a certain distance between the first chip structure 20 and the interposer layer 30;
  • a pre-layer of plastic packaging material 400 is formed;
  • Part of the plastic encapsulation material pre-layer 400 is removed by etching to form the plastic encapsulation material 40 and expose the surface of the first solder ball 312 .
  • a first packaging mold 91 is formed on the first chip structure 20 and the interposer 30, and a second packaging mold 92 is formed below the substrate 10.
  • the second packaging mold 92 is parallel to the surface of the substrate 10 .
  • a pre-layer of plastic compound 400 is formed between the first packaging mold 91 and the second packaging mold 92 .
  • the plastic pre-layer 400 completely covers the first surface of the substrate 10, the first chip structure 20, the interposer 30 and the initial first solder ball 312' on the interposer 30.
  • the method further includes: after forming the plastic sealant pre-layer 400, removing the first packaging mold 91 and the second packaging mold 92.
  • part of the pre-layer of plastic compound 400 is removed to form the plastic compound 40 and expose the surface of the first solder ball 312 .
  • a grinding wheel can be used to grind the surface of the plastic sealing material pre-layer 400 to remove part of the plastic sealing material pre-layer 400 and remove part of the initial first solder ball 312' to form a first solder ball with a preset height h. 312.
  • the first solder ball is formed on the first interconnection area, there is no need to expose the first interconnection area, and there is no need to use a special-shaped packaging mold. Instead, only a normal-shaped first packaging mold needs to be used. Since the first packaging mold has a simple shape, the manufacturing process is simple and the cost is low.
  • substrate connection bumps 17 are formed on the second surface 102 of the substrate 10 , and the substrate connection bumps 17 include conductive material.
  • a second packaging structure 70 is formed.
  • the second packaging structure 70 includes a second solder ball 71.
  • the second packaging structure 70 passes through the second solder ball 71 and the first solder ball 312. Electrical connection.
  • the volume of the first solder ball 312 is larger than the volume of the second solder ball 71 .
  • the first solder ball 312 and the second solder ball 71 prevent the lateral flow of solder during the subsequent reflow soldering process, reduce the risk of short circuit between adjacent solder balls, and improve the quality of the first solder ball and the second solder ball. Ball joint strength.
  • the plastic molding compound 40 In a direction perpendicular to the substrate 10 , the plastic molding compound 40 has a first thickness; the second packaging structure 70 includes a second plastic molding compound 73 , and in a direction perpendicular to the substrate 10 , the second molding compound 40 has a first thickness.
  • the plastic molding material 73 has a second thickness; wherein the first thickness is greater than or equal to the second thickness. Since the thickness of the plastic molding material 40 is relatively large, it can fully support the second packaging structure and prevent the first packaging structure from warping toward the second packaging structure.
  • the second packaging structure 70 further includes a second substrate 72.
  • the structure of the second substrate 72 may be the same as or different from the structure of the substrate 10, which will not be described again here.
  • a second conductive block 322 is formed on the substrate 10, and an interposer 30 is formed on the second conductive block 322; the interposer 30 passes through the second conductive block 322.
  • the block 322 is electrically connected to the substrate 10 .
  • the area of the first bonding pad 321 is larger than the area of the second bonding pad 311 .
  • the second interconnection area no longer mainly carries the communication between other packaging structures and the substrate. Therefore, the first bonding pad can use a large area of metal, increasing the heat dissipation area to improve heat dissipation efficiency.
  • a first chip structure 20 is formed on the interposer 30 ; forming the first chip structure 20 includes: forming a plurality of first semiconductors arranged in sequence in a direction parallel to the substrate 10 Chip 21.
  • a first conductive block 201 is formed on the interposer 30, and a first chip structure 20 is formed on the first conductive block 201; each of the first semiconductor chips 20 passes through The first conductive block 201 is electrically connected to the substrate 10 .
  • first packaging mold 91 and a second packaging mold 92 are formed.
  • the first packaging mold and the second packaging mold in this embodiment are the same as the first packaging mold and the second packaging mold in Figures 5a to 5h, and will not be described again here.
  • the first packaging mold 91 and the second packaging mold 92 are used as masks to form a pre-layer of plastic sealant 400.
  • the plastic pre-layer 400 completely covers the first surface of the substrate 10, the first chip structure 20, the interposer 30 and the initial first solder ball 312' on the interposer 30.
  • the first packaging mold 91 and the second packaging mold 92 are removed.
  • part of the pre-layer of plastic encapsulation material 400 is removed to form the plastic encapsulation compound 40, and part of the initial first solder ball 312' is removed to form a first solder ball 312 with a preset height h.
  • substrate connection bumps 17 are formed on the second surface 102 of the substrate 10 , and the substrate connection bumps 17 include conductive material.
  • the second packaging structure 70 includes a second solder ball 71.
  • the second packaging structure 70 passes through the second solder ball 71 and the first solder ball 312. Electrical connection.
  • the second packaging structure in this embodiment is the same as the second packaging structure in Figures 5a to 5h, and will not be described again here.
  • the subsequent second package structure can be connected to the first chip structure and the substrate through the first solder ball on the interposer.
  • first solder ball on the interposer.
  • connections make the combination of different structures more flexible.
  • the first chip structure and the second packaging structure are independently packaged, it is easier to conduct testing and failure analysis.
  • there is a preset height between the top surface of the first solder ball and the first interconnection surface which can ensure that the entire package structure has a relatively thin overall thickness and is relatively thinner than the subsequent second package structure. Good bonding power.

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Abstract

本公开实施例公开了一种半导体封装组件及制备方法，其中，所述半导体封装组件，包括：基板，所述基板具有第一面；第一芯片结构，所述第一芯片结构位于所述基板上，且与所述基板的第一面之间电连接；中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。

Description

半导体封装组件及制备方法
相关申请的交叉引用
本公开基于申请号为202210806540.3、申请日为2022年07月08日、发明名称为“半导体封装组件及制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体封装组件及制备方法。
背景技术
在所有部门，行业和地区，电子行业都在不断要求提供更轻、更快、更小、多功能、更可靠和更具成本效益的产品。为了满足众多不同消费者的这些不断增长的需求，需要集成更多的电路来提供所需的功能。在几乎所有应用中，对减小尺寸，提高性能和改善集成电路功能的需求不断增长。
发明内容
有鉴于此，本公开实施例提供一种半导体封装组件及制备方法。
根据本公开实施例的第一方面，提供了一种半导体封装组件，包括：
基板，所述基板具有第一面；
第一芯片结构，所述第一芯片结构位于所述基板上，且与所述基板的第一面之间电连接；
中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；
塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。
在一些实施例中，所述第一芯片结构包括沿垂直于所述基板方向依次堆叠的多个第一半导体芯片；
所述中介层位于所述第一芯片结构上。
在一些实施例中，还包括：
第一导电线，每个所述第一半导体芯片通过所述第一导电线与所述基板之间电连接；
第二导电线，所述第二互连区域通过所述第二导电线与所述基板之间电连接。
在一些实施例中，所述第一互连区域上形成有多个第二焊垫，其中，所述第一焊垫的数量大于所述第二焊垫的数量，所述第一焊垫的面积小于所述第二焊垫的面积。
在一些实施例中，所述第一芯片结构包括沿平行于所述基板方向依次排布的多个第一半导体芯片；
所述第一芯片结构位于所述中介层上。
在一些实施例中，还包括：
第一导电块，位于所述第一半导体芯片与所述中介层之间，每个所述第一半导体芯片通过所述第一导电块与所述基板之间电连接；
第二导电块，位于所述中介层与所述基板之间，所述中介层通过所述第二导电块与所述基板之间电连接。
在一些实施例中，还包括：
第二封装结构，所述第二封装结构包括第二焊球，所述第二封装结构通过所述第二焊球与所述第一焊球电连接。
在一些实施例中，所述第一焊球的体积大于所述第二焊球的体积。
在一些实施例中，在垂直于所述基板的方向上，所述塑封料具有第一厚度；
所述第二封装结构包括第二塑封料，在垂直于所述基板的方向上，所述第二塑封料具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
根据本公开实施例的第二方面，提供了一种半导体封装组件的制备方法，包括：
提供基板，所述基板具有第一面；
在所述基板上形成第一芯片结构，所述第一芯片结构与所述基板的第一面之间电连接；
形成中介层；所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；
形成塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。
在一些实施例中，所述形成塑封料，包括：
形成第一封装模具，所述第一封装模具的表面平行于所述基板的表面，所述第一封装模具位于所述第一芯片结构和所述中介层的上方，且与所述第一芯片结构和所述中介层之间存在一定距离；
以所述第一封装模具为掩膜，形成塑封料预层；
去除部分塑封料预层，形成塑封料，并暴露所述第一焊球的表面。
在一些实施例中，所述形成第一芯片结构，包括：沿垂直于所述基板方向，形成依次堆叠的多个第一半导体芯片；
在所述第一芯片结构上形成中介层。
在一些实施例中，还包括：
在形成中介层后，
形成第一导电线；每个所述第一半导体芯片通过所述第一导电线与所述基板之间电连接；
形成第二导电线；所述第二互连区域通过所述第二导电线与所述基板之间电连接。
在一些实施例中，还包括：
在所述第一互连区域上形成多个第二焊垫，其中，所述第一焊垫的数量大于所述第二焊垫的数量，所述第一焊垫的面积小于所述第二焊垫的面积。
在一些实施例中，在所述中介层上形成第一芯片结构；
所述形成第一芯片结构，包括：沿平行于所述基板方向，形成依次排布的多个第一半导体芯片。
在一些实施例中，还包括：
在形成基板后，在所述基板上形成第二导电块，在所述第二导电块上形成中介层；所述中介层通过所述第二导电块与所述基板之间电连接；
在形成中介层后，在所述中介层上形成第一导电块，在所述第一导电块上形成第一芯片结构；每个所述第一半导体芯片通过所述第一导电块与所述基板之间电连接。
在一些实施例中，还包括：
形成第二封装结构，所述第二封装结构包括第二焊球，所述第二封装结构通过所述第二焊球与所述第一焊球电连接。
在一些实施例中，所述第一焊球的体积大于所述第二焊球的体积。
在一些实施例中，在垂直于所述基板的方向上，所述塑封料具有第一厚度；
所述第二封装结构包括第二塑封料，在垂直于所述基板的方向上，所述第二塑封料具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一焊球与第一芯片结构以及基板连接，如此，可实现不同类型或 不同规格的结构之间的互连，使得不同结构之间的组合更加灵活。同时因为第一芯片结构和第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。并且第一焊球的顶表面与第一互连面之间存在预设高度，可以保证整个封装结构具有相对较薄的整体厚度的基础上，还与后续的第二封装结构之间具有相对较好的结合力。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体封装组件的结构示意图；
图2为本公开实施例提供的基板的结构示意图；
图3为本公开另一实施例提供的半导体封装组件的结构示意图；
图4为本公开实施例提供的半导体封装组件的制备方法的流程示意图；
图5a至图5h为本公开实施例提供的半导体封装组件在制备过程中的器件结构示意图；
图6a至图6f为本公开另一实施例提供的半导体封装组件在制备过程中的器件结构示意图。
附图标记说明：
1-圆环；2-载带；
10-基板；101-第一面；102-第二面；11-基板衬底；12-基板上绝缘介质层；13-基板下绝缘介质层；14-基板上连接焊盘；15-基板下连接焊盘；16-基板连接通孔；17-基板连接凸块；
20-第一芯片结构；21-第一半导体芯片；211-第一连接端；201-第一导电块；
30-中介层；301-第一互连面；31-第一互连区域；32-第二互连区域；311-第二焊垫；312-第一焊球；312’-初始第一焊球；321-第一焊垫；33-中介衬底；34-中介上绝缘介质层；35-中介下绝缘介质层；322-第二导电块；
40-塑封料；
51-第一导电线；52-第二导电线；
60-粘附膜；
70-第二封装结构；71-第二焊球；72-第二基板；73-第二塑封料；
91-第一封装模具；92-第二封装模具。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附 图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列 项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
基于此，本公开实施例提供了一种半导体封装组件。图1为本公开实施例提供的半导体封装组件的结构示意图。
参见图1，所述半导体封装组件，包括：
基板10，所述基板具有第一面101；
第一芯片结构20，所述第一芯片结构20位于所述基板10上，且与所述基板10的第一面101之间电连接；
中介层30，所述中介层30具有第一互连面301，所述第一互连面301具有第一互连区域31和第二互连区域32，所述第一互连区域31上形成有第一焊球312，所述第二互连区域32上形成有第一焊垫321，所述中介层30通过所述第一焊垫321与所述基板10的第一面101之间电连接；
塑封料40，所述塑封料40密封所述第一芯片结构20、所述中介层30与所述基板10的第一面101，其中，所述第一焊球312具有暴露于所述塑封料40的表面，所述第一焊球312暴露的表面与所述中介层30的第一互连面301之间具有预设高度h。
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一焊球与第一芯片结构以及基板连接，在本公开实施例中，中介层可由包含非有机材料，例如硅中介层或任何一种或多种有机材料组成的结构。通过中介层的设置，可实现不同类型或不同规格的结构之间的互连，使得不同结构之间的组合更加灵活。同时因为第一芯片结构和第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。
在本公开的一个实施例中，第一焊球的顶表面与第一互连面之间存在预设高度h，预设高度h不小于中介层厚度的1/5-1/2，在一些实施例中，如果中介层的厚度为100-200μm，那么预设高度h为50-120μm，通过这样的设置，可以有效的抑制因为塑封料与中介层之间热膨胀系数不匹配导致的应力问题，可以保证整个封装结构具有相对较薄的整体厚度的基础上，还与后续的第二封装结构之间具有相对较好的结合力。
图2为本公开实施例提供的基板的结构示意图。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
参见图2，所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例 如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在本公开实施例中，所述基板10的第一面101即为所述基板上绝缘介质层12的上表面。所述基板10还包括与所述第一面101相背离的第二面102，所述第二面102为所述基板下绝缘介质层13的下表面。
所述基板10还包括位于所述基板上绝缘介质层12内的基板上连接焊盘14，位于所述基板下绝缘介质层13内的基板下连接焊盘15，以及贯穿所述基板衬底11并将所述基板上连接焊盘14和所述基板下连接焊盘15彼此连接的基板连接通孔16。
所述基板上连接焊盘14和所述基板下连接焊盘15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述基板连接通孔16可以为穿硅通孔(TSV)。
所述基板10还包括基板连接凸块17，所述基板连接凸块17位于所述基板10的第二面102上。所述基板连接凸块17可将半导体封装组件电连接到外部装置上，可以从外部装置接收用于操作第一芯片结构的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在第一芯片结构内的数据信号，也可将第一芯片结构内的数据提供给外部装置。
所述基板连接凸块17包括导电材料。在本公开提供的图2所示的实施例中，所述基板连接凸块17为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
继续参见图2，所述基板10还包括分别位于所述基板10相对的两侧的第一信号传输区域110和第二信号传输区域120。所述第一信号传输区域110与第一芯片结构20电连接，所述第二信号传输区域120与所述中介层30电连接，
所述基板10还包括位于所述第一信号传输区域110和第二信号传输区域120之间的第三信号传输区域130，所述第一芯片结构20位于所述第三信号传输区域130上。
在本公开实施例中，所述第一芯片结构与所述中介层的位置关系存在两种情况，一种是如图1所示，所述中介层30位于所述第一芯片结构20的上方，另一种是如图3所示，所述第一芯片结构20位于所述中介层30 的上方。
在如图1所示的实施例中，所述第一芯片结构20包括沿垂直于所述基板10方向依次堆叠的多个第一半导体芯片21；所述中介层30位于所述第一芯片结构20上。
在此实施例中，采用向上依次堆叠多个第一半导体芯片的方式，可以节省半导体封装组件的水平面积。
所述第一半导体芯片可以为DRAM芯片或其他类型的半导体芯片。
继续参见图1，所述半导体封装组件还包括：
第一导电线51，每个所述第一半导体芯片21通过所述第一导电线51与所述基板10之间电连接；
第二导电线52，所述第二互连区域32通过所述第二导电线52与所述基板10之间电连接。
具体地，所述第一半导体芯片21具有第一连接端211，所述第一连接端211与所述第一信号传输区域110位于同一侧，从所述第一连接端211上引出第一导电线51到所述第一传输区域110上，以实现第一半导体芯片21与基板10的电连接。
所述第二互连区域32上形成有第一焊垫321，从所述第一焊垫321上引出第二导电线52到所述第二传输区域120上，以实现中介层30与基板10之间的电连接。
本公开实施例中，所述第一芯片结构与所述基板之间采用引线键合方式进行电连接的方式包括悬垂(Overhang)方式和导线上膜(Film on wire，FOW)方式。
图1所示的实施例中，采用悬垂方式进行引线键合。相邻两个第一半导体芯片21之间通过粘附膜60连接，所述粘附膜60不覆盖其下方一层的第一半导体芯片21上的第一连接端211以及第一导电线51，所述粘附膜60与其下方一层的所述第一半导体芯片21错位设置。
在另一些实施例中，采用导线上膜方式进行引线键合(未图示)。多个所述第一半导体芯片沿垂直于所述基板的方向对齐设置，相邻两个第一半导体芯片之间的粘附膜覆盖其下方一层的第一半导体芯片上的第一连接端以及第一导线线。
可以理解的是，本公开实施例中利用引线的方式进行电连接仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，也可以使用其他方式进行电连接，例如混合键合或者凸块互连。
继续参见图1，所述中介层30包括中介衬底33和分别设置在所述中介衬底33的上表面和下表面上的中介上绝缘介质层34和中介下绝缘介质层35。
所述中介衬底33可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On  Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述中介上绝缘介质层34和所述中介下绝缘介质层35可以为阻焊层，例如所述中介上绝缘介质层34和所述中介下绝缘介质层35的材料可以为绿漆。
所述中介层30的第一互连区域31上形成有多个第二焊垫311，其中，所述第一焊垫321的数量大于所述第二焊垫311的数量，所述第一焊垫321的面积小于所述第二焊垫311的面积。
因为第二焊垫后续需要与第二封装结构进行匹配互连，因此布局设计相对比较固定，而第一焊垫承载的是第二封装结构与基板的互连，因此布局设计更为灵活，将第一焊垫设计成数量较多，面积较小，可以提高信号传输效率。
所述第一焊垫321和所述第二焊垫311的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。
在如图3所示的实施例中，所述第一芯片结构20包括沿平行于所述基板10方向依次排布的多个第一半导体芯片21；所述第一芯片结构20位于所述中介层30上。
在此实施例中，采用在水平方向依次设置多个第一半导体芯片的方式，可以降低半导体封装组件的封装高度。
继续参见图3，所述半导体封装组件还包括：第一导电块201，位于所述第一半导体芯片21与所述中介层30之间，每个所述第一半导体芯片21通过所述第一导电块201与所述基板10之间电连接；第二导电块322，位于所述中介层30与所述基板10之间，所述中介层30通过所述第二导电块322与所述基板10之间电连接。
本实施例中，第一半导体芯片通过第一导电块与中介层互连，中介层与基板互连，因此第一半导体芯片通过第一导电块以及中介层与基板连接。
在一实施例中，所述第一焊垫321的面积大于所述第二焊垫311的面积。
在图3所示的实施例中，由于中介层与基板直接互连，因此第二互连区域不再主要承载其他封装结构与基板的通信，因此第一焊垫可以采用大面积的金属，增加散热面积，提高散热效率。
在一实施例中，参见图1，所述半导体封装组件还包括：第二封装结构70，所述第二封装结构70包括第二焊球71，所述第二封装结构70通过所述第二焊球71与所述第一焊球312电连接。
在一实施例中，所述第一焊球312的体积大于所述第二焊球71的体积。通过这样的配置，使得第一焊球312与第二焊球71在后续回流焊接过程中 防止焊料的横向流动，降低相邻焊球之间短接的风险，提高第一焊球与第二焊球的接合强度。
在垂直于所述基板10的方向上，所述塑封料40具有第一厚度；所述第二封装结构70包括第二塑封料73，在垂直于所述基板10的方向上，所述第二塑封料73具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。由于塑封料40的厚度相对较大，可以充分支撑第二封装结构，防止第一封装结构朝向第二封装结构发生翘曲。
所述第二封装结构70还包括第二基板72，所述第二基板72的结构与所述基板10的结构可以相同或不同，这里不再赘述。
所述第二封装结构包括第二芯片结构(未图示)，所述第二芯片结构可以为通用闪存存储芯片(Universal File Store，UFS)。
本公开实施例提供的半导体封装组件可应用于叠层封装(Package on Package，PoP)结构的多芯片封装(UFS Multi Chip Package，UMCP)。
在本公开实施例中，所述塑封料的顶表面与所述第一焊球的顶表面共面，因此，可以在形成塑封料时，使用正常的封装模具进行封装，无需形成异形封装模具，异形封装模具制作成本高，工艺更为复杂，如此，本公开实施例提供的半导体封装组件能减少成本，同时形成工艺也更为简单。
本公开实施例还提供了一种半导体封装组件的制备方法，具体请参见图4，如图所示，所述方法包括以下步骤：
步骤401：提供基板，所述基板具有第一面；
步骤402：在所述基板上形成第一芯片结构，所述第一芯片结构与所述基板的第一面之间电连接；
步骤403：形成中介层；所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；
步骤404：形成塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。
下面结合具体实施例对本公开实施例提供的半导体封装组件的制备方法再作进一步详细的说明。
图5a至图5h为本公开实施例提供的半导体封装组件在制备过程中的器件结构示意图，图6a至图6e为本公开另一实施例提供的半导体封装组件在制备过程中的器件结构示意图。需要解释的是，图5a至图5h所示的半导体封装组件的制备方法中，先形成第一芯片结构，再形成中介层，而图6a至图6e所示的半导体封装组件的制备方法中，先形成中介层，再形成第一芯片结构。
先参见图5a至图5h，对所述半导体封装组件的制备方法的其中一种实施例进行详细的说明。
首先，参见图5a，执行步骤401，提供基板10，所述基板10具有第一面101。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在本公开实施例中，所述基板10的第一面101即为所述基板上绝缘介质层12的上表面。所述基板10还包括与所述第一面101相背离的第二面102，所述第二面102为所述基板下绝缘介质层13的下表面。
所述基板10还包括位于所述基板上绝缘介质层12内的基板上连接焊盘14，位于所述基板下绝缘介质层13内的基板下连接焊盘15，以及贯穿所述基板衬底11并将所述基板上连接焊盘14和所述基板下连接焊盘15彼此连接的基板连接通孔16。
所述基板上连接焊盘14和所述基板下连接焊盘15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述基板连接通孔16可以为穿硅通孔(TSV)。
所述基板10还包括分别位于所述基板10相对的两侧的第一信号传输区域110和第二信号传输区域120。所述第一信号传输区域110与后续形成的第一芯片结构电连接，所述第二信号传输区域120与后续形成的中介层电连接。
在一些实施例中，第一信号传输区域110与第二信号传输区域120不互连。
所述基板10还包括位于所述第一信号传输区域110和第二信号传输区域120之间的第三信号传输区域130，第一芯片结构位于所述第三信号传输区域130上。
在一些实施例中，第一信号传输区域110与第三信号传输区域130互连，第三信号传输区域130与第二信号传输区域120之间不互连。
接着，参见图5b，执行步骤402，在所述基板10上形成第一芯片结构20，所述第一芯片结构20与所述基板10的第一面101之间电连接。
在一实施例中，所述形成第一芯片结构20，包括：沿垂直于所述基板10方向，形成依次堆叠的多个第一半导体芯片21。在此实施例中，采用向上依次堆叠多个第一半导体芯片的方式，可以节省半导体封装组件的水平面积。
具体地，先在所述基板10上形成粘附膜60，然后在所述粘附膜60上形成第一芯片结构20。相邻两个所述第一半导体芯片21之间通过粘附膜60连接。
接着，参见图5c至图5d，执行步骤403，形成中介层30；所述中介层30具有第一互连面301，所述第一互连面301具有第一互连区域31和第二互连区域32，所述第一互连区域31上形成有第一焊球312，所述第二互连区域32上形成有第一焊垫321，所述中介层30通过所述第一焊垫321与所述基板10的第一面101之间电连接。
具体地，先参见图5c，在圆环1上粘贴载带2，然后在载带2上贴上粘附膜60，然后将中介层粘贴在粘附膜60上，此时的中介层为整片的条状，对中介层进行切割，形成如图8c所示的一个一个的单元。
接着，参见图5d，在所述第一芯片结构20上形成中介层30。
具体地，将图5c中形成的单个中介层30贴在所述第一芯片结构20上。
在本公开的一个实施例中，如图5d所示，先在所述中介层30的第一互连区域31上形成初始第一焊球312’，后续经过刻蚀或研磨后形成为第一焊球312。所述初始第一焊球312’在垂直于中介层30的方向上具有初始高度。
所述中介层30包括中介衬底33和分别设置在所述中介衬底33的上表面和下表面上的中介上绝缘介质层34和中介下绝缘介质层35。
所述中介衬底33可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述中介上绝缘介质层34和所述中介下绝缘介质层35可以为阻焊层，例如所述中介上绝缘介质层34和所述中介下绝缘介质层35的材料可以为绿漆。
继续参见图5d，所述方法还包括：在所述第一互连区域31上形成多个第二焊垫311，其中，所述第一焊垫321的数量大于所述第二焊垫311的数量，所述第一焊垫321的面积小于所述第二焊垫311的面积。
因为第二焊垫后续需要与第二封装结构进行匹配互连，因此布局设计 相对比较固定，而第一焊垫承载的是第二封装结构与基板的互连，因此布局设计更为灵活，将第一焊垫设计成数量较多，面积较小，可以提高信号传输效率。
所述第一焊垫321和所述第二焊垫311的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。
继续参见图5d，所述方法还包括：在形成中介层30后，形成第一导电线51；每个所述第一半导体芯片21通过所述第一导电线51与所述基板10之间电连接；形成第二导电线52；所述第二互连区域32通过所述第二导电线52与所述基板10之间电连接。
具体地，在所述第一半导体芯片21上形成第一连接端211，所述第一连接端211与所述第一信号传输区域110位于同一侧，从所述第一连接端211上引出第一导电线51到所述第一传输区域110上，以实现第一半导体芯片21与基板10的电连接。
所述第二互连区域32上形成有第一焊垫321，从所述第一焊垫321上引出第二导电线52到所述第二传输区域120上，以实现中介层30与基板10之间的电连接。
接着，参见图5e至图5g，执行步骤404，形成塑封料40，所述塑封料40密封所述第一芯片结构20、所述中介层30与所述基板10的第一面101，其中，所述第一焊球312具有暴露于所述塑封料40的表面，所述第一焊球312暴露的表面与所述中介层30的第一互连面301之间具有预设高度h。
所述形成塑封料40，包括：
形成第一封装模具91，所述第一封装模具91的表面平行于所述基板10的表面，所述第一封装模具91位于所述第一芯片结构20和所述中介层30的上方，且与所述第一芯片结构20和所述中介层30之间存在一定距离；
以所述第一封装模具91为掩膜，形成塑封料预层400；
刻蚀去除部分塑封料预层400，形成塑封料40，并暴露所述第一焊球312的表面。
具体地，先参见图5e，在所述第一芯片结构20和所述中介层30上形成第一封装模具91，在所述基板10的下方形成第二封装模具92，所述第二封装模具92平行于所述基板10的表面。
接着，参见图5f，以第一封装模具91和第二封装模具92为掩膜，在第一封装模具91和第二封装模具92之间形成塑封料预层400。
所述塑封料预层400完全覆盖所述基板10的第一面、所述第一芯片结构20、所述中介层30以及中介层30上的初始第一焊球312’。
所述方法还包括：在形成塑封料预层400后，去除第一封装模具91以及第二封装模具92。
接着，参见图5g，去除部分塑封料预层400，形成塑封料40，并暴露所述第一焊球312的表面。
具体地，可以用砂轮在所述塑封料预层400的表面进行打磨，以去除部分塑封料预层400，并去除部分初始第一焊球312’，形成具有预设高度h的第一焊球312。
本公开实施例因为在第一互连区域上形成了第一焊球，所以不需要露出第一互连区域，也就不需要使用异形封装模具，而只需要使用形状正常的第一封装模具，而第一封装模具因为形状简单，所以制作工艺简单，成本较低。
继续参见图5g，在形成塑封料40后，在所述基板10的第二面102上形成基板连接凸块17，所述基板连接凸块17包括导电材料。
接着，参见图5h，形成第二封装结构70，所述第二封装结构70包括第二焊球71，所述第二封装结构70通过所述第二焊球71与所述第一焊球312电连接。
在一实施例中，所述第一焊球312的体积大于所述第二焊球71的体积。通过这样的配置，使得第一焊球312与第二焊球71在后续回流焊接过程中防止焊料的横向流动，降低相邻焊球之间短接的风险，提高第一焊球与第二焊球的接合强度。
在垂直于所述基板10的方向上，所述塑封料40具有第一厚度；所述第二封装结构70包括第二塑封料73，在垂直于所述基板10的方向上，所述第二塑封料73具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。由于塑封料40的厚度相对较大，可以充分支撑第二封装结构，防止第一封装结构朝向第二封装结构发生翘曲。
所述第二封装结构70还包括第二基板72，所述第二基板72的结构与所述基板10的结构可以相同或不同，这里不再赘述。
接下来，参见图6a至图6f，对所述半导体封装组件的制备方法的另一种实施例进行详细的说明。
需要说明的是，图6a至图6f中的基板与图5a至图5h中的基板相似，这里不再赘述。
首先，参见图6a，在形成基板10后，在所述基板10上形成第二导电块322，在所述第二导电块322上形成中介层30；所述中介层30通过所述第二导电块322与所述基板10之间电连接。
在一实施例中，所述第一焊垫321的面积大于所述第二焊垫311的面积。
在图3所示的实施例中，由于中介层与基板直接互连，因此第二互连区域不再主要承载其他封装结构与基板的通信，因此第一焊垫可以采用大面积的金属，增加散热面积，提高散热效率。
接着，参见图6b，在所述中介层30上形成第一芯片结构20；所述形成第一芯片结构20，包括：沿平行于所述基板10方向，形成依次排布的多个第一半导体芯片21。
具体地，在形成中介层30后，在所述中介层30上形成第一导电块201，在所述第一导电块201上形成第一芯片结构20；每个所述第一半导体芯片20通过所述第一导电块201与所述基板10之间电连接。
接着，参见图6c，形成第一封装模具91和第二封装模具92。本实施例中的第一封装模具和第二封装模具与图5a至图5h中的第一封装模具和第二封装模具相同，这里不再赘述。
接着，参见图6d，以第一封装模具91和第二封装模具92为掩膜，形成塑封料预层400。所述塑封料预层400完全覆盖所述基板10的第一面、所述第一芯片结构20、所述中介层30以及中介层30上的初始第一焊球312’。
在形成塑封料预层400后，去除所述第一封装模具91以及第二封装模具92。
接着，参见图6e，去除部分塑封料预层400，形成塑封料40，并去除部分初始第一焊球312’，形成具有预设高度h的第一焊球312。
继续参见图8e，在形成塑封料40后，在所述基板10的第二面102上形成基板连接凸块17，所述基板连接凸块17包括导电材料。
接着，参见图6f，形成第二封装结构70，所述第二封装结构70包括第二焊球71，所述第二封装结构70通过所述第二焊球71与所述第一焊球312电连接。
本实施例中的第二封装结构与图5a至图5h中的第二封装结构相同，这里不再赘述。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，通过设置中介层，后续第二封装结构可以通过中介层上的第一焊球与第一芯片结构以及基板连接，如此，可实现不同类型或不同规格的结构之间的互连，使得不同结构之间的组合更加灵活。同时因为第一芯片结构和第二封装结构是独立封装的，因此也更加容易进行测试和失效分析。并且第一焊球的顶表面与第一互连面之间存在预设高度，可以保证整个封装结构具有相对较薄的整体厚度的基础上，还与后续的第二封装结构之间具有相对较好的结合力。

Claims (19)

  1. 一种半导体封装组件，包括：
    基板，所述基板具有第一面；
    第一芯片结构，所述第一芯片结构位于所述基板上，且与所述基板的第一面之间电连接；
    中介层，所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；
    塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。
  2. 根据权利要求1所述的半导体封装组件，其中，
    所述第一芯片结构包括沿垂直于所述基板方向依次堆叠的多个第一半导体芯片；
    所述中介层位于所述第一芯片结构上。
  3. 根据权利要求2所述的半导体封装组件，其中，还包括：
    第一导电线，每个所述第一半导体芯片通过所述第一导电线与所述基板之间电连接；
    第二导电线，所述第二互连区域通过所述第二导电线与所述基板之间电连接。
  4. 根据权利要求2所述的半导体封装组件，其中，
    所述第一互连区域上形成有多个第二焊垫，其中，所述第一焊垫的数量大于所述第二焊垫的数量，所述第一焊垫的面积小于所述第二焊垫的面积。
  5. 根据权利要求1所述的半导体封装组件，其中，
    所述第一芯片结构包括沿平行于所述基板方向依次排布的多个第一半导体芯片；
    所述第一芯片结构位于所述中介层上。
  6. 根据权利要求5所述的半导体封装组件，其中，还包括：
    第一导电块，位于所述第一半导体芯片与所述中介层之间，每个所述第一半导体芯片通过所述第一导电块与所述基板之间电连接；
    第二导电块，位于所述中介层与所述基板之间，所述中介层通过所述第二导电块与所述基板之间电连接。
  7. 根据权利要求1所述的半导体封装组件，其中，还包括：
    第二封装结构，所述第二封装结构包括第二焊球，所述第二封装结构通过所述第二焊球与所述第一焊球电连接。
  8. 根据权利要求7所述的半导体封装组件，其中，
    所述第一焊球的体积大于所述第二焊球的体积。
  9. 根据权利要求7所述的半导体封装组件，其中，
    在垂直于所述基板的方向上，所述塑封料具有第一厚度；
    所述第二封装结构包括第二塑封料，在垂直于所述基板的方向上，所述第二塑封料具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
  10. 一种半导体封装组件的制备方法，包括：
    提供基板，所述基板具有第一面；
    在所述基板上形成第一芯片结构，所述第一芯片结构与所述基板的第一面之间电连接；
    形成中介层；所述中介层具有第一互连面，所述第一互连面具有第一互连区域和第二互连区域，所述第一互连区域上形成有第一焊球，所述第二互连区域上形成有第一焊垫，所述中介层通过所述第一焊垫与所述基板的第一面之间电连接；
    形成塑封料，所述塑封料密封所述第一芯片结构、所述中介层与所述基板的第一面，其中，所述第一焊球具有暴露于所述塑封料的表面，所述第一焊球暴露的表面与所述中介层的第一互连面之间具有预设高度。
  11. 根据权利要求10所述的方法，其中，
    所述形成塑封料，包括：
    形成第一封装模具，所述第一封装模具的表面平行于所述基板的表面，所述第一封装模具位于所述第一芯片结构和所述中介层的上方，且与所述第一芯片结构和所述中介层之间存在一定距离；
    以所述第一封装模具为掩膜，形成塑封料预层；
    去除部分塑封料预层，形成塑封料，并暴露所述第一焊球的表面。
  12. 根据权利要求10所述的方法，其中，
    所述形成第一芯片结构，包括：沿垂直于所述基板方向，形成依次堆叠的多个第一半导体芯片；
    在所述第一芯片结构上形成中介层。
  13. 根据权利要求12所述的方法，其中，还包括：
    在形成中介层后，
    形成第一导电线；每个所述第一半导体芯片通过所述第一导电线与所述基板之间电连接；
    形成第二导电线；所述第二互连区域通过所述第二导电线与所述基板之间电连接。
  14. 根据权利要求12所述的方法，其中，还包括：
    在所述第一互连区域上形成多个第二焊垫，其中，所述第一焊垫的数量大于所述第二焊垫的数量，所述第一焊垫的面积小于所述第二焊垫的面 积。
  15. 根据权利要求10所述的方法，其中，
    在所述中介层上形成第一芯片结构；
    所述形成第一芯片结构，包括：沿平行于所述基板方向，形成依次排布的多个第一半导体芯片。
  16. 根据权利要求15所述的方法，其中，还包括：
    在形成基板后，在所述基板上形成第二导电块，在所述第二导电块上形成中介层；所述中介层通过所述第二导电块与所述基板之间电连接；
    在形成中介层后，在所述中介层上形成第一导电块，在所述第一导电块上形成第一芯片结构；每个所述第一半导体芯片通过所述第一导电块与所述基板之间电连接。
  17. 根据权利要求10所述的方法，其中，还包括：
    形成第二封装结构，所述第二封装结构包括第二焊球，所述第二封装结构通过所述第二焊球与所述第一焊球电连接。
  18. 根据权利要求17所述的方法，其中，
    所述第一焊球的体积大于所述第二焊球的体积。
  19. 根据权利要求17所述的方法，其中，
    在垂直于所述基板的方向上，所述塑封料具有第一厚度；
    所述第二封装结构包括第二塑封料，在垂直于所述基板的方向上，所述第二塑封料具有第二厚度；其中，所述第一厚度大于或等于所述第二厚度。
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