CN104377192B - 多芯片结构及其形成方法 - Google Patents

多芯片结构及其形成方法 Download PDF

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Publication number
CN104377192B
CN104377192B CN201410371367.4A CN201410371367A CN104377192B CN 104377192 B CN104377192 B CN 104377192B CN 201410371367 A CN201410371367 A CN 201410371367A CN 104377192 B CN104377192 B CN 104377192B
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chip
semiconductor
edge
layer
semiconductor devices
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CN104377192A (zh
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余振华
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种器件，包括堆叠在一起的第一芯片和第二芯片以形成多芯片结构，其中，多个芯片结构嵌入在封装层内。该器件还包括形成在封装层的第一侧的顶面上的重分布层，其中，重分布层连接至第一芯片的有源电路和第二芯片的有源电路，并且重分布层延伸超出第一芯片和第二芯片中的至少一个边缘。本发明还提供了一种形成该器件的方法。

Description

多芯片结构及其形成方法
本申请要求于2013年8月13日提交的标题为“Multi-Chip Structure and Methodof Forming Same”的美国临时专利申请61/865，411号的优先权，其全部内容结合于此作为参考。
技术领域
本发明总体涉及半导体领域，更具体地，涉及多芯片器件及其形成方法。
背景技术
由于各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成度的提高，半导体行业经历了快速发展。在大多数情况下，集成度的这种提高源自于半导体工艺节点的缩小(例如，将工艺节点朝着亚20nm节点缩小)。随着近期对小型化、更高速度、更大带宽以及更低功耗和延迟的需求的增长，需要更小且更富创造性的半导体管芯的封装技术。
由于半导体技术的发展，基于晶圆级封装的半导体器件已作为进一步减小半导体芯片的物理尺寸的有效替代而出现。在基于晶圆级封装的半导体器件中可能具有两种信号布线机制，即，扇入信号布线机制和扇出信号布线机制。在具有扇入信号布线机制的半导体器件中，每个管芯的输入和输出焊盘都被限制在半导体管芯封装内部的区域中。在管芯的区域受限的情况下，因为限制了输入和输出焊盘的节距，所以输入和输出焊盘的数量也受到限制。
在具有扇出信号布线机制的半导体器件中，可以在管芯的区域以外的区域内重分布管芯的输入和输出焊盘。这样，输入和输出焊盘能够将信号传播至比管芯区域更大的区域并且为互连提供额外的空间。因此，能够增加半导体器件的输入和输出焊盘的个数。
在扇出结构中，通过使用重分布层能够实施信号重分布。重分布层可将管芯区域内的输入和输出焊盘与管芯区域以外的另一个输入和输出焊盘连接，这样使得来自半导体管芯的信号可在半导体管芯封装外部传播。
模塑料层可形成在半导体管芯上方。模塑料层可由环氧基树脂等形成。模塑料层中从管芯的边缘至半导体器件的边缘的一部分通常被称为半导体器件的扇出区域。
发明内容
根据本发明的一个方面，提供了一种器件，包括：扇出结构、第一芯片、第二芯片和模塑料层。其中，扇出结构包括：重分布层，设置在扇出结构的第一侧上；介电层，设置在重分布层的上方；和多个第一凸块，设置在介电层上方并且位于扇出结构的第二侧上。第一芯片，设置在扇出结构的第一侧上方，其中，第一芯片包括连接至重分布层的多个第一通孔。第二芯片，设置在第一芯片的上方，其中，第二芯片通过多个第二凸块连接至第一芯片。模塑料层，设置在扇出结构的第一侧的上方，其中，第一芯片和第二芯片均嵌入至模塑料层内，并且第一芯片的至少一个边缘与第二芯片的相应边缘并未垂直对齐。
优选地，第二芯片的顶面暴露在模塑料层的外部。
优选地，第二芯片包括堆叠在一起的多个半导体管芯。
优选地，第二芯片的有源电路电连接至第一凸块。
优选地，该器件还包括：在第一芯片的第一中心线和第二芯片的第二中心线之间的位移。
优选地，该位移被配置为：第一芯片的一边缘与扇出结构的第一边缘对齐；以及第二芯片的一边缘与扇出结构的第二边缘对齐，并且第一边缘和第二边缘位于扇出结构的相对两侧上。
优选地，第一凸块包括焊料、铜以及它们的任意组合。
根据本发明的另一方面，提供了一种器件，包括：第一芯片和第二芯片，堆叠在一起以形成多芯片结构，其中，多芯片结构嵌入在封装层内，并且第一芯片的至少一个边缘与第二芯片的相应边缘并未垂直对齐；重分布层，设置在封装层的第一侧的顶面上，其中，重分布层连接至第一芯片的有源电路和第二芯片的有源电路，同时，重分布层延伸超出第一芯片和第二芯片中的至少一个边缘；以及多个导电凸块，设置在重分布层的上方并且连接至重分布层。
优选地，该器件还包括：介电层，设置在多个导电凸块和封装层的第一侧的顶面之间。
优选地，该器件还包括：多个凸块，设置在第一芯片和第二芯片之间。
优选地，多芯片结构的顶面暴露在封装层的第二侧的外部。
优选地，第二芯片包括堆叠在一起的多个半导体管芯。
优选地，第一芯片和第二芯片被配置为：第一芯片位移至封装层的第一边缘；以及第二芯片位移至封装层的第二边缘，其中，第一边缘和第二边缘位于封装层的相对两侧上。
优选地，第一芯片的一边缘与封装层的第一边缘对齐；以及第二芯片的一边缘与封装层的第二边缘对齐。
根据本发明的另一方面，提供了一种方法，包括：通过粘合层将多个堆叠的半导体管芯附接在载具上；在多个堆叠的半导体管芯的顶面上安装半导体芯片；在载具上方形成模塑料层，其中，多个堆叠的半导体管芯和半导体芯片均嵌入在模塑料层内，并且多个堆叠的半导体管芯的至少一个边缘与半导体芯片的相应边缘并未垂直对齐；研磨模塑料层，直至暴露出半导体芯片的表面；在半导体芯片的表面上形成重分布层；以及在重分布层上方形成多个导电凸块。
优选地，该方法还包括：在半导体芯片的表面上形成重分布层，其中，重分布层延伸超出半导体芯片的一个边缘；以及重分布层延伸超出多个堆叠的半导体管芯的一个边缘。
优选地，该方法还包括：将半导体芯片附接在多个堆叠的半导体管芯上；以及应用回流工艺，使得半导体芯片接合在多个堆叠的半导体管芯的顶面上以形成多芯片结构。
优选地，该方法还包括：在重分布层上沉积介电层。
优选地，该方法还包括：在介电层中形成多个凸块下金属化(UBM)结构；以及在UBM结构上方形成多个导电凸块。
优选地，堆叠的半导体管芯是存储器电路；以及半导体芯片包括逻辑电路。
附图说明
为了更全面地理解本发明及其优势，现将结合附图所进行的描述作为参考，其中：
图1示出了根据本发明不同实施例的多芯片半导体器件的截面图；
图2至图9示出了根据本发明不同实施例的制造图1所示的多芯片半导体器件的中间步骤；
图2示出了根据本发明不同实施例的在载具上安装第一芯片之后的半导体器件的截面图；
图3示出了根据本发明不同实施例的图2所示的半导体器件在第一芯片上安装第二芯片之后的截面图；
图4示出了根据本发明不同实施例的图3所示的半导体器件在载具上方形成封装层之后的截面图；
图5示出了根据本发明不同实施例的图4所示的半导体器件在将研磨工艺应用于封装层的顶面之后的截面图；
图6示出了根据本发明不同实施例的图5所示的半导体器件在封装层的顶部上形成重分布层之后的截面图；
图7示出了根据本发明不同实施例的图6所示的半导体器件在封装层的顶部上形成介电层之后的截面图；
图8示出了根据本发明不同实施例的图7所示的半导体器件在形成多个UBM结构和互连凸块之后的截面图；
图9示出了根据本发明不同实施例的从半导体器件上去除载具的工艺；以及
图10至图20示出了根据本发明不同实施例的多芯片半导体器件的其他示例性实施例。
除非另有说明，否则不同附图中的相应字符和符号通常指代相应部件。绘制附图以清楚地示出不同实施例的相关方面而无需按比例绘制附图。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
将结合具体环境中的实施例(即，具有扇出结构的多芯片半导体器件)来描述本发明。然而，本发明的实施例也可应用于各种半导体器件和封装件。在下文中，将参照附图详细地解释不同实施例。
图1示出了根据本发明的不同实施例的多芯片半导体器件的截面图。多芯片半导体器件100可包括第一芯片102和第二芯片104。具体地，第一芯片102堆叠在第二芯片104的顶部。如图1所示，第一芯片102和第二芯片104通过由导电凸块111形成的连接结构而接合在一起。可以通过回流工艺产生连接结构。
第一芯片102可包括多个堆叠在一起的半导体管芯。如图1所示，通过堆叠的半导体管芯110、120、130和140形成第一芯片102。在每个堆叠的半导体管芯中可具有多个通孔(例如，管芯120中的通孔122、管芯130中的通孔132和管芯140中的通孔142)。通孔122、132和142填充有诸如铜等的导电材料。置于两个相邻的堆叠管芯之间的通孔和导电凸块形成了各种导电通道，各堆叠的半导体管芯中的电路可通过导电通道彼此连接。
第一芯片102内的堆叠的半导体管芯可包括存储器管芯、逻辑管芯、处理器管芯等。应该注意，虽然图1示出了在第一芯片102中的四个堆叠的半导体管芯，但是其仅为实例。同样地，图1所示的通孔的位置和每个堆叠的半导体管芯中的通孔的数量仅为示例性的，但是用于电连接堆叠的管芯的其他配置也在本发明的可预期的范围内。
根据实施例，第二芯片104可包括多种逻辑电路，诸如，中央处理单元(CPU)、图像处理单元(GPU)等。可选地，第二芯片104可包括多种存储器电路，诸如，静态随机存取存储器(SRAM)和动态随机存取存储器(DRAM)等。此外，第二芯片104可包括用于其他合适应用(诸如，射频应用、图像传感器、它们的任意组合等)的集成电路。应该注意，第二芯片104可具有许多实施例，这些实施例也在本发明的范围内。
为了对各个实施例的发明方面做一个基本了解，没有详细地绘出第二芯片104。然而，应该注意，第二芯片104可包括基础的半导体各层，诸如，有源电路层、衬底层、层间介电(ILD)层、金属间介电(IMD)层(未分别示出)等。
第二芯片104可包括衬底。衬底可以是硅衬底。可选地，衬底可以是绝缘体上硅(SOI)衬底。SOI衬底可包括形成在绝缘层(例如，埋氧层等)上方的半导体材料(例如，硅、锗等)层，该绝缘层形成在硅衬底中。此外，可用的其他衬底包括多层衬底、梯度衬底、混合取向衬底等的。
衬底还可包括各种电路(未示出)。形成在衬底上的电路可以是适用于诸如逻辑电路的各种应用的任意类型的电路。在一些实施例中，电路可包括各种n型金属氧化半导体(NMOS)和/或p型金属氧化半导体(PMOS)器件，诸如，晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可互连各电路以执行一种或多种功能。这些功能可包括存储器结构、处理结构、传感器、放大器、功率分配器、输入/输出电路等。
本领域的技术人员应该意识到，上文中提供的实例仅出于说明的目的以进一步解释本发明的应用，但并不旨在以任何方式限制本发明。
第二芯片104还可包括多个通孔106。在一些实施例中，通孔106是衬底通孔(TSV)或硅通孔(TSV)。通孔106可填充有诸如铜、钨等的导电材料。第二芯片104的有源电路层(未示出)可以通过通孔106连接至第一芯片102的有源电路和外部电路(未示出)。
如图1所示，第一芯片102和第二芯片104均嵌入封装层101内。在一些实施例中，第一芯片102的至少一个边缘(例如，第一芯片102的左边缘)不与第二芯片104的相应边缘(例如，第二芯片104的左边缘)垂直对齐。
图1还示出了第一芯片102的顶面暴露在封装层101的外部。根据一些实施例，封装层101可以是由合适的底部填充材料形成的模塑料层。在整篇描述中，封装层101可选地被称为模塑料层101。
模塑料101可填充第一芯片102和第二芯片104之间的间隙。超出第二芯片104的边缘的区域通常被称为扇出区。如图1所示，可有两个扇出区。第一扇出区是超出第二芯片104的左边缘的模塑料区。同样地，第二扇出区是超出第二芯片104的右边缘的模塑料区。
在一些实施例中，模塑料层101可由诸如环氧树脂的合适的材料形成。可以以液态形式应用环氧树脂，并且可在固化工艺之后使其硬化。在可选实施例中，模塑料层101可由可固化材料(诸如，聚合物基材料、树脂基材料、聚酰亚胺、环氧树脂和它们的任意组合)形成。可通过任何合适的涂布技术来形成模塑料层101。
还应该注意，图1所示的扇出区仅为实例。通过移位第一芯片102和/或第二芯片104，多芯片半导体器件100可具有不同的扇出区。下文将参照图13至图20描述这种扇出区的详细结构。
多芯片半导体器件100还可包括扇出结构105。如图1所示，扇出结构105包括形成在模塑料层101上方的重分布层107、形成在重分布层107上方的介电层112以及多个凸块109。
在整篇描述中，扇出结构105中具有重分布层107的一侧可选地被称为扇出结构105的第一侧。另一方面，扇出结构105中不具有重分布层107的一侧被称为扇出结构105的第二侧。
如图1所示，重分布层107形成在第二芯片104的前侧。具体地，重分布层107延伸超出位于封装层101的顶面上的第二芯片104的边缘。重分布层107提供了TSV(例如，通孔106)和随后在扇出结构105的第二侧上方形成的凸块之间的导电路径。通过重分布层可桥接第二芯片104的有源电路层(未示出)，这样使得半导体管芯(例如，第二芯片104)的有源电路层能够电连接至外部电路。重分布层107可由诸如铝、铝合金、铜或铜合金等的金属材料形成。
介电层112形成在重分布层107的上方。在一些实施例中，介电层112由光敏材料(诸如，聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、它们的任意组合等)形成，使用光刻掩模可以很容易地图案化光敏材料。在可选实施例中，介电层112可由氮化物(诸如，氮化硅)、氧化物(诸如，氧化硅)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)以及它们的任意组合等形成。
可通过合适的制造技术来形成介电层112，这些制造工艺包括旋涂、化学汽相沉积(CVD)以及等离子体增强CVD(PECVD)等。还应该注意，本领域的技术人员将会意识到，介电层112还可包括多个介电层。
凸块109形成在扇出结构105的第二侧上。在凸块109的下面可形成多个凸块下金属化(UBM)结构108。下文将参照图8详细描述凸块109和UBM结构108的形成工艺。
图1所示的多芯片半导体器件100的一个有利特征在于扇出结构105有助于多芯片半导体器件100实现更好的热性能、低收缩和翘曲、较小的形状因数以及由于使用的凸块数量减少而节约了成本。
图2至图9示出了根据本发明不同实施例的制造图1所示的多芯片半导体器件的中间步骤。应该注意，图2至图9所示的制造步骤以及多芯片半导体器件仅为实例。本领域的技术人员将会意识到，可具有许多替换、变化和修改。
图2示出了根据本发明不同实施例的在载具上安装第一芯片之后的半导体器件的截面图。可采用载具202以防止半导体器件裂缝、翘曲、破裂等。此外，载具202可有助于通过在载具202上方形成的模塑料层形成扇出结构。
辅助层204形成在载具202的顶部上。在一些实施例中，辅助层204可包括脱模层和粘合层(未分别示出)。脱模层可由诸如聚合物等的合适的材料形成。脱模层可以是UV可固化的。在一些实施例中，脱模层可旋转涂覆在载具202上。
粘合层可旋转涂覆在脱模层上。粘合层可由诸如聚合物等的合适的材料形成。在可选实施例中，粘合层可以是诸如管芯附接膜(DAF)、非导电膜(NCF)等的合适的胶带。可以通过使用化学溶剂、化学机械抛光(CMP)等来去除粘合层。
通过贴片工艺可将第一芯片102安装在载具上。具体地，将第一芯片102贴在载具202的顶部上。第一芯片102通过粘合层接合在载具202上。应该注意，虽然图2示出了第一芯片102可包括四个半导体管芯，但是第一芯片102可容纳任意数量的半导体管芯。
图3示出了根据本发明不同实施例的图2所示的半导体器件在第二芯片安装在第一芯片上之后的截面图。第二芯片104可以通过回流工艺接合在第一芯片102上。采用回流工艺以在第一芯片102和第二芯片104之间形成连接结构。
应该注意，虽然图3示出了在第一芯片102的顶部上堆叠一个半导体管芯(例如，第二芯片104)，但是其仅为实例。本领域的技术人员将会意识到，可具有许多变化、替代和修改。例如，可在第二芯片104的顶部上堆叠附加的管芯。
图4示出了根据本发明不同实施例的图3所示的半导体器件在载具上方形成封装层之后的截面图。如图4所示，封装层101形成在载具202的上方。因此，第一芯片102和第二芯片104的顶面由封装层101覆盖。
根据一些实施例，封装层101可以是由合适的底部填充材料形成的模塑料层。在一些实施例中，底部填充材料层可由环氧树脂形成。可以以液态形式环氧树脂应用，并且可在固化工艺之后使其硬化。在可选实施例中，底部填充材料层可由可固化材料(诸如，聚合物基材料、树脂基材料、聚酰亚胺、环氧树脂和它们的任意组合)形成。可以通过任何合适的涂布技术来形成封装层101。
图5示出了根据本发明不同实施例的图4示出的半导体器件在将研磨工艺应用于封装层的顶面之后的截面图。封装层101的顶面经历了研磨工艺。研磨工艺可采用机械研磨工艺、化学抛光工艺、蚀刻工艺以及它们的任意组合等。
如图5所示，将研磨工艺应用于封装层101的顶面，直至暴露出第二芯片104的顶面。在一些实施例中，第二芯片104的互连结构的顶面可与封装层101的顶面基本上共面。因此，互连结构可暴露在封装层101的外部，这样使得诸如重分布层、凸块等的电接触件可形成在第二芯片104的互连结构上。
图6示出了根据本发明不同实施例的图5所示的半导体器件在封装层的顶部上形成重分布层之后的截面图。在一些实施例中，重分布层107可延伸超出第二芯片104的边缘。因此，最终的结构是扇出结构。
在一些实施例中，可以通过沉积金属层并且随后图案化该金属层来形成重分布层107。在可选实施例中，可以使用镶嵌工艺来形成重分布层107。此外，例如，可以使用例如沉积方法(诸如，物理汽相沉积(PVD))来形成重分布层107。重分布层107可包括铝、铜、钨和/或它们的合金。
图7示出了根据本发明不同实施例的图6所示的半导体器件在封装层的顶部上形成介电层之后的截面图。在一些实施例中，介电层112由光敏材料(诸如，PBO、聚酰亚胺、BCB、它们的任意组合等)形成。
在可选实施例中，介电层112可由一种或多种合适的介电材料(诸如，氧化硅、氮化硅、低k介电材料(诸如碳掺杂的氧化物)、极低k介电材料(诸如多孔碳掺杂的二氧化硅)、聚合物等)形成。可以通过诸如CVD的工艺来形成介电层112，但是也可以利用任何合适的工艺。
图8示出了根据本发明不同实施例的图7所示的半导体器件在形成多个UBM结构和互连凸块之后的截面图。多个UBM结构108形成在介电层112内并且位于重分布层107的上方。UBM结构108在提供低电阻电连接的同时，有助于防止在焊料球和半导体器件的集成电路之间的扩散。
凸块109是半导体器件的输入/输出(I/O)焊盘或互连凸块。在一些实施例中，凸块109可由铜形成。根据另一个实施例，凸块109可以是多个焊料球109。在一些实施例中，焊料球109可包括SAC 405。SAC 405包括95.5％的Sn、4.0％的Ag和0.5％的Cu。可选地，凸块109可以是多个栅格阵列(LGA)焊盘。
图9示出了根据本发明不同实施例的从半导体器件上去除载具的工艺。根据实施例，载具202能够与多芯片半导体器件100分离。可采用各种分离工艺使多芯片半导体器件与载具202分隔开。各种分离工艺可包括化学溶剂、UV曝光、激光烧蚀工艺等。
图10示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了第一芯片102的长度与扇出结构105的长度相同外，多芯片半导体器件1000与图1所示的多芯片半导体器件100相似。这样，封装层101位于第一芯片102和扇出结构105之间。多芯片半导体器件1000的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图11示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了第二芯片104的长度与扇出结构105的长度相同之外，多芯片半导体器件1100与图1所示的多芯片半导体器件100相似。多芯片半导体器件1100的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图12示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了第二芯片104的长度大于第一芯片102的长度之外，多芯片半导体器件1200与图1所示的多芯片半导体器件100相似。多芯片半导体器件1200的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图13示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了第一芯片102和第二芯片104之间可具有位移之外，多芯片半导体器件1300与图1所示的多芯片半导体器件100相似。具体地，第一芯片102的中心线与第二芯片104的中心线未对齐。
如图13所示，与图1所示的多芯片半导体器件100相比，第一芯片102位移到扇出结构105的右边缘。因此，可具有一个扇出区，该扇出区是位于扇出结构105和第一芯片102之间的模塑料区。
如图13所示，第一芯片102的右边缘与扇出结构105的右边缘对齐。同样地，第二芯片104位移至扇出结构105的左边缘。第二芯片104的左边缘与扇出结构105的左边缘对齐。多芯片半导体器件1300的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图14示出了根据本发明的不同实施例的另一个具有扇出结构的多芯片半导体器件。除了第一芯片102和第二芯片104均没有位移至扇出结构105的边缘之外，多芯片半导体器件1400与图13所示的多芯片半导体器件1300相似。多芯片半导体器件1400的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图15示出了根据本发明不同实施例另一个具有扇出结构的多芯片半导体器件的截面图。除了第二芯片104没有位移至扇出结构105的边缘之外，多芯片半导体器件1500与图13所示的多芯片半导体器件1300相似。多芯片半导体器件1500的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图16示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了第一芯片102没有位移至扇出结构105的边缘之外，多芯片半导体器件1600与图13所示的多芯片半导体器件1300相似。多芯片半导体器件1600的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。
图17示出了根据本发明不同实施例的另一个具有扇出结构的多芯片半导体器件的截面图。除了在第一芯片102和第二芯片104之间可具有一个通孔连接件外，多芯片半导体器件1700与图13所示的多芯片半导体器件1300相似。
第一芯片102和第二芯片104之间的位移可包括各种变化。需要第一芯片102和第二芯片104之间存在重叠，这样使得第一芯片102的至少一个通孔通过导电凸块连接至第二芯片104的相应通孔。多芯片半导体器件1700的制造工艺与多芯片半导体器件100的制造工艺相似，因此，为了避免赘述此处不再讨论。除了第一芯片102和第二芯片104之间可具有一个连接通路之外，图18至图20所示的实施例分别与图14至图16中的实施例相似。
根据一个实施例，一种器件包括：扇出结构，该扇出结构包括设置在扇出结构的第一侧上的重分布层、设置在重分布层上方的介电层以及设置在介电层上方并且位于扇出结构的第二侧上的多个第一凸块；第一芯片，设置在扇出结构的第一侧的上方，其中，第一芯片包括多个连接至重分布层的第一通孔；第二芯片，设置在第一芯片的上方，其中，第二芯片通过多个第二凸块连接至第一芯片；以及模塑料层，设置在扇出结构的第一侧的上方，其中，第一芯片和第二芯片嵌入模塑料层内，并且第一芯片的至少一个边缘与第二芯片的相应边缘并未垂直对齐。
根据一个实施例，一种器件包括：第一芯片和第二芯片，堆叠在一起以形成多芯片结构，其中，多芯片结构嵌入封装层中，并且第一芯片的至少一个边缘与第二芯片的相应边缘并未垂直对齐；重分布层，设置在封装层的第一侧的顶面上，其中，重分布层连接至第一芯片和第二芯片的有源电路，并且重分布层延伸超出第一芯片和第二芯片的至少一个边缘；以及多个导电凸块，设置在重分布层的上方并且连接至重分布层。
根据一个实施例，一种方法包括：通过粘合层将多个堆叠的半导体器件附接在载具上；在多个堆叠的半导体管芯的顶面上安装半导体芯片；在载具上方形成模塑料层，其中，多个堆叠的半导体管芯和半导体芯片嵌入模塑料层内，并且堆叠的半导体管芯的至少一个边缘与半导体芯片的相应边缘并未垂直对齐；研磨模塑料层直至露出半导体管芯的表面；在半导体芯片的表面上形成重分布层；以及在重分布层的上方形成多个导电凸块。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结构的工艺、机器、制造、材料组分、装置、方法或步骤本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (20)

1.一种半导体器件，包括：
扇出结构，包括：
重分布层，设置在所述扇出结构的第一侧上；
介电层，设置在所述重分布层的上方；和
多个第一凸块，设置在所述介电层上方并且位于所述扇出结构的第二侧上；
第一芯片，设置在所述扇出结构的第一侧上方，其中，所述第一芯片包括连接至所述重分布层的多个第一通孔；
第二芯片，设置在所述第一芯片的上方，其中，
所述第二芯片通过多个第二凸块连接至所述第一芯片；以及
模塑料层，设置在所述扇出结构的第一侧的上方，其中，所述第一芯片和所述第二芯片均嵌入至所述模塑料层内，并且所述第一芯片的至少一个边缘与所述第二芯片的相应边缘并未垂直对齐，所述第一芯片的一个侧壁和所述第二芯片的一个侧壁暴露在所述模塑料层的外部。
2.根据权利要求1所述的半导体器件，其中，所述第二芯片的顶面暴露在所述模塑料层的外部。
3.根据权利要求1所述的半导体器件，其中，所述第二芯片包括堆叠在一起的多个半导体管芯。
4.根据权利要求1所述的半导体器件，其中，所述第二芯片的有源电路电连接至所述第一凸块。
5.根据权利要求1所述的半导体器件，还包括：
在所述第一芯片的第一中心线和所述第二芯片的第二中心线之间的位移。
6.根据权利要求5所述的半导体器件，其中，
所述位移被配置为：
所述第一芯片的一边缘与所述扇出结构的第一边缘对齐；以及
所述第二芯片的一边缘与所述扇出结构的第二边缘对齐，并且所述第一边缘和所述第二边缘位于所述扇出结构的相对两侧上。
7.根据权利要求1所述的半导体器件，其中，
所述第一凸块包括焊料、铜以及它们的任意组合。
8.一种半导体器件，包括：
第一芯片和第二芯片，堆叠在一起以形成多芯片结构，其中，所述多芯片结构嵌入在封装层内，并且所述第一芯片的至少一个边缘与所述第二芯片的相应边缘并未垂直对齐，所述第一芯片的一个侧壁和所述第二芯片的一个侧壁暴露在所述封装层的外部；
重分布层，设置在所述封装层的第一侧的顶面上，其中，
所述重分布层连接至所述第一芯片的有源电路和所述第二芯片的有源电路；和
所述重分布层延伸超出所述第一芯片和所述第二芯片中的至少一个边缘；以及
多个导电凸块，设置在所述重分布层的上方并且连接至所述重分布层。
9.根据权利要求8所述的半导体器件，还包括：
介电层，设置在所述多个导电凸块和所述封装层的第一侧的顶面之间。
10.根据权利要求8所述的半导体器件，还包括：
多个凸块，设置在所述第一芯片和所述第二芯片之间。
11.根据权利要求8所述的半导体器件，其中，
所述多芯片结构的顶面暴露在所述封装层的第二侧的外部。
12.根据权利要求8所述的半导体器件，其中，
所述第二芯片包括堆叠在一起的多个半导体管芯。
13.根据权利要求8所述的半导体器件，其中，
所述第一芯片和所述第二芯片被配置为：
所述第一芯片位移至所述封装层的第一边缘；以及
所述第二芯片位移至所述封装层的第二边缘，其中，所述第一边缘和所述第二边缘位于所述封装层的相对两侧上。
14.根据权利要求13所述的半导体器件，其中，
所述第一芯片的一边缘与所述封装层的第一边缘对齐；以及
所述第二芯片的一边缘与所述封装层的第二边缘对齐。
15.一种形成半导体器件的方法，包括：
通过粘合层将多个堆叠的半导体管芯附接在载具上；
在所述多个堆叠的半导体管芯的顶面上安装半导体芯片；
在所述载具上方形成模塑料层，其中，所述多个堆叠的半导体管芯和所述半导体芯片均嵌入在所述模塑料层内，并且所述多个堆叠的半导体管芯的至少一个边缘与所述半导体芯片的相应边缘并未垂直对齐，所述半导体芯片的一个侧壁和所述多个堆叠的半导体管芯的一个侧壁暴露在所述模塑料层的外部；
研磨所述模塑料层，直至暴露出所述半导体芯片的表面；
在所述半导体芯片的表面上形成重分布层；以及
在所述重分布层上方形成多个导电凸块。
16.根据权利要求15所述的方法，还包括：
在所述半导体芯片的表面上形成所述重分布层，其中，
所述重分布层延伸超出所述半导体芯片的一个边缘；以及
所述重分布层延伸超出所述多个堆叠的半导体管芯的一个边缘。
17.根据权利要求15所述的方法，还包括：
将所述半导体芯片附接在所述多个堆叠的半导体管芯上；以及
应用回流工艺，使得所述半导体芯片接合在所述多个堆叠的半导体管芯的顶面上以形成多芯片结构。
18.根据权利要求15所述的方法，还包括：
在所述重分布层上沉积介电层。
19.根据权利要求18所述的方法，还包括：
在所述介电层中形成多个凸块下金属化(UBM)结构；以及
在所述凸块下金属化结构上方形成所述多个导电凸块。
20.根据权利要求15所述的方法，其中，
所述堆叠的半导体管芯是存储器电路；以及
所述半导体芯片包括逻辑电路。
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