CN106981459A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106981459A
CN106981459A CN201611235620.9A CN201611235620A CN106981459A CN 106981459 A CN106981459 A CN 106981459A CN 201611235620 A CN201611235620 A CN 201611235620A CN 106981459 A CN106981459 A CN 106981459A
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layer
certain embodiments
nitride
passivation layer
semiconductor devices
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CN106981459B (zh
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张育维
许育铨
李坤讳
彭垂亚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例公开了一种半导体器件及其形成方法。半导体器件包括管芯、导电结构、接合焊盘和钝化层。导电结构位于管芯上方并且电连接至管芯。接合焊盘位于导电结构上方并且电连接至导电结构。钝化层位于接合焊盘上方,其中,钝化层包括具有约2.16到2.18的折射率的基于氮化物的层。本发明实施例涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及半导体器件及其制造方法。
背景技术
非易失性存储器因为其具有在断电的情况下保留信息的能力而用于广泛的应用中并用作长期的永久存储器。非易失性存储器的实例包括但不限于:诸如可编程只读存储器(“PROM”)、可擦除PROM(“EPROM”)、和电可擦除PROM(“EEPROM”)的只读存储器(“ROM”)。非易失性存储器的另一实例是紫外可擦除(“UV-擦除”)PROM。在UV-擦除PROM中,可以通过应用紫外线照射存储器件以激发存储在栅极中的电子而擦除数据,从而电子从栅极向外部区域发射。
发明内容
根据本发明的一个实施例,提供了一种半导体器件,包括:管芯;导电结构,位于所述管芯上方并且电连接至所述管芯;接合焊盘,位于所述导电结构上方并且电连接至所述导电结构;以及钝化层,位于所述接合焊盘上方,其中,所述钝化层包括具有2.16至2.18的折射率的基于氮化物的层。
根据本发明的另一实施例,还提供了一种半导体器件,包括:管芯;以及导电结构,位于所述管芯上方并且电连接至所述管芯,所述导电结构包括多个介电层和位于所述介电层中的多个导电部件,其中,至少一个所述介电层包括具有2.16至2.18的折射率的基于氮化物的层。
在上述半导体器件中,所述基于氮化物的层用作蚀刻停止层。
根据本发明的又一实施例,还提供了一种半导体器件的制造方法,包括:在管芯上方形成导电结构;在所述导电结构上方形成接合焊盘;以及利用大于700瓦的射频在所述接合焊盘上方形成钝化层,其中,所述钝化层包括基于氮化物的层。
附图说明
图1A至图1F是根据一些实施例的示出了半导体器件的制造方法的示意图。
具体实施方式
下列公开提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面将描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。而且,本发明在各个实例中可重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为了便于描述,在此可使用诸如“在...之下”、“在...下面”、“下面的”、“在...上面”、以及“上面的”以及诸如此类的空间关系术语,以描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。空间相对术语旨在包括除了附图中所示的方位之外,在使用中或操作中的器件的不同方位。装置可以以其它方式定位(旋转90度或在其他方位),并且通过在本文中使用的空间关系描述符可同样地作相应地解释。
图1A至图1F是根据一些实施例的示出了半导体器件的制造方法的示意图。
例如,参照图1A,在一些实施例中,提供了管芯102。在一些实施例中,管芯31包括衬底20、集成电路器件22、互连结构23、焊盘24、第一钝化层26、连接件30和第二钝化层28。例如,衬底20包括掺杂或不掺杂的块状硅,或绝缘体上硅(SOI)衬底的有源层。
例如,集成电路器件22是晶体管、电容器、电阻器、二极管、光电二极管、熔丝元件或类似的元件。互连结构23形成在集成电路器件22上方以连接不同的集成电路器件22,从而形成功能电路。在一些实施例中,集成电路器件22包括位于介电层中的栅极结构、源极/漏极区和隔离结构,其中,隔离结构可以是浅沟槽隔离(STI)结构。在一些实施例中,例如,栅极结构包括栅电极和位于栅电极和衬底20之间的栅极介电层。在可选实施例中,栅极结构还包括位于栅电极旁边的间隔件(未示出)。在一些实施例中,例如,栅电极的材料是多晶硅。
在一些实施例中,集成电路器件22可以是一次性可编程(OTP)存储器、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、非易失随机存取存储器(NVRAM)或逻辑电路。在一些实施例中,可使用双极-CMOS-DMOS(BCD)工艺制造集成电路器件22。
在互连结构23上方形成焊盘24。焊盘24和互连结构23电连接(未示出)以提供至集成电路器件22的外部连接。例如,焊盘24包括铝、铜、镍、上述的组合等。
在衬底20和焊盘24上方形成第一钝化层26。第一钝化层26包括诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、它们的组合等的聚合物。通过诸如旋涂、层压、沉积等的合适的制造技术形成第一钝化层26。
连接件30形成在焊盘24上方并可选地电连接至焊盘24。连接件30包括焊料凸块、金凸块、铜凸块、铜柱或由铜或铜合金制成的导电柱。
在第一钝化层26上方和连接件30的旁边形成第二钝化层28。例如,第二钝化层28包括聚合物。聚合物包括聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、它们的组合等。通过诸如旋涂、层压、沉积等的合适的制造技术形成第二钝化层28。
在一些实施例中,在管芯102的背面上方形成粘合层14。粘合层14包括管芯附接膜(DAF)、银膏等。
在一些实施例中,将具有粘合层14的管芯102放置在载体110上方。载体110提供为具有形成在其上的胶层112和介电层114。载体110可以是空白玻璃载体、空白陶瓷载体等。胶层112可由诸如紫外(UV)胶、光热转换(LTHC)胶等的粘合剂形成,但是也可以使用其他类型的粘合剂。在一些实施例中,胶层112在光的热量下可分解,从而将载体110从在其上形成的结构释放。介电层114是形成在胶层112上方。在一些实施例中,介电层114是聚合物层。例如,聚合物包括聚酰亚胺、PBO、BCB、味之素构建膜(Ajinomoto Buildup Film)(ABF)、阻焊膜(SR)等。介电层114是由诸如旋涂、层压、沉积等的合适的制造技术制成的。
在一些实施例中,在载体110上方、管芯102旁边形成通孔116。通孔116的材料可以包括诸如铜、镍、焊料或它们的组合的金属。在可选实施例中,通孔116包括位于通孔116的侧壁的诸如Ti、TiN、Ta、TaN层的阻挡层(未示出)。在载体110上方形成密封剂118以封装管芯102。密封剂118封装管芯102以保护装管芯102免受环境和外部污染物的影响。密封剂118的材料可以包括:包括树脂和填料的模塑料材料,光敏材料,诸如聚苯并恶唑(PBO)、苯并环丁烯(BCB)、它们的任何组合等。在可选实施例中,密封剂118可以由诸如氮化硅的氮化物和诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、任何它们的组合等的氧化物形成。
参照图1B,导电结构119形成在管芯102上方并电连接至管芯102。在一些实施例中,在管芯102、密封剂118和通孔116上方形成导电结构119。在一些实施例中,导电结构119与连接件30和/或通孔16电连接。例如,导电结构119包括多个介电层120-126和位于介电层120-126中的多个导电部件128a-128d。在一些实施例中,例如,可以在后段制程(BEOL)工艺中形成导电结构119。在一些实施例中,导电部件128a-128d的每一个可以包括插塞或导电线。在可选实施例中,导电部件128a-128d是含铜导电材料。在可选实施例中,导电部件128a-128d包括铜、镍、金、银、铝、钨、上述的组合等。形成导电部件128a-128d的方法包括实施电化学镀工艺、化学汽相沉积(CVD)、等离子体增强的化学汽相沉积(PECVD)、物理汽相沉积(PVD)、原子层沉积(ALD)等或上述的组合等。在一些实施例中,形成导电结构119的方法包括图案化介电层、在介电层中形成插塞和在介电层中形成金属层,并重复上述步骤。在所提供的实施例中,介电层120到126具有单层或双层,仅仅为了说明的目的,并且不解释为限制本发明。本领域普通技术人员应该理解,层的数量不受本文中的实施例的限制。类似地,在所提供的实施例中,导电结构119具有四个介电层和四个导电部件,仅仅为了说明的目的,并且不解释为限制本发明。本领域普通技术人员应该理解,介电层和导电部件的数量不受本文中的实施例的限制。
在一些实施例中,介电层120到126包括单层或多层。在一些实施例中,介电层122包括单层122a,以及介电层120、124或126包括多层120a到120c、124a到124b或126a到126b。在一些实施例中,在介电层120、124或126中,层120a到120c、124a到124b或126a到126b的材料是相同或不同的。在一些实施例中,例如,介电层120到126的每个(例如,层120、124或126中,层120a到120c、124a到124b或126a到126b的每个)包括氮化硅(SiNx)、氮化硅(SiC)、低介电常数(低k)材料等。例如,通过沉积、旋涂或层压形成介电层120到126。
在一些实施例中,介电层120到126的至少一个包括具有约2.16到2.18的折射率的压缩的(compressive)的基于氮化物的层。更具体地说,层120a到120c、124a到124b或126a到126b的至少一个包括具有约2.16到2.18的折射率的压缩基于氮化物基的层。例如,在一些实施例中,在最上面的导电部件128d旁边的介电层126具有压缩的基于氮化物的层。在一些实施例中,压缩的基于氮化物的层的材料括氮化硅。例如,在一些实施例中,在介电层126中,层126a是压缩氮化硅层,以及层126b是氧化硅层。在一些实施例中,当压缩的基于氮化物的层具有高紫外线透射率时,用作蚀刻停止层。在一些实施例中,压缩的基于氮化物的层的折射率为约2.16、2.165、2.17、2.175、2.18,包括任何两个前面的值之间的任何范围。在一些实施例中,压缩的基于氮化物的层具有约小于-2×109的压缩应力。在一些实施例中,压缩的基于氮化物的层具有低的Si-H键比。例如,在一些实施例中,压缩的基于氮化物的层中Si-H键与N-H键比率在从约0.25至约0.5的范围内。在一些实施例中,压缩的基于氮化物的层中Si-H键与N-H键比率为约0.25、0.3、0.35、0.4、0.45、0.5,包括任何两个前面的值之间的任何范围。例如,在一些实施例中,在245nm,压缩的基于氮化物的层具有约60%到80%的紫外线透射率。在一些实施例中,在245nm,压缩的基于氮化物的层的紫外线透射率为约60%、65%、70%、75%、80%,包括任何两个前面的值之间的任何范围。此外,例如,压缩的基于氮化物的层具有期望的耐酸性。在一些实施例中,利用大于700瓦的射频(RF)沉积压缩的基于氮化物的层。在一些实施例中,RF是约700瓦至约900瓦。例如,在一些实施例中,使用SiH4和NH3的反应物和N2载体气体,通过PECVD沉积压缩的基于氮化物的层。例如,在一些实施例中,SiH4与NH3的比率小于0.08。例如,可以在约400℃至约1000℃的温度、约2Torr到3Torr的压力下,实施沉积工艺。大于700瓦的高RF使基于氮化物的层成为压缩层。
参照图1C,接合焊盘134形成在导电结构119上方并电连接至导电结构119。在一些实施例中,在导电层119上方形成介电层130,然后,在介电层130的开口132中和介电层130的部分上方形成接合焊盘134。在一些实施例中,介电层130具有多层结构,例如,介电层130包括多个层130a到130d。在一些实施例中,层130a到130d的材料是相同的或不同的。在一些实施例中,例如,层130a到130d的每一个均包括二氧化硅(SiO2)、氮化硅(SiNx)、氮化硅(SiC)、低介电常数(低k)材料等。在可选实施例中,介电层130具有单层结构。例如,通过旋涂或层压形成介电层130。在一些实施例中,介电层130包括具有约2.16到2.18的折射率的压缩的基于氮化物的层。更具体地说,层130a到130d的至少一个包括具有约2.16到2.18的折射率的压缩的基于氮化物的层。例如,在一些实施例中,层130a和130c是诸如压缩氮化硅层的压缩的基于氮化物的层,以及130b和130d是氧化硅层。在一些实施例中,当压缩的基于氮化物的层具有高紫外线透射率时,用作蚀刻停止层。上文讨论了压缩的基于氮化物的层的形成方法和性能,因此这里省略了这些。在所提供的实施例中,介电层130具有4层结构,仅仅为了说明的目的,并且不解释为限制本发明。本领域普通技术人员应该理解,介电层的数量不受本文中的实施例的限制。
在一些实施例中,接合焊盘134包括铝或含铝导电材料。在可选实施例中,接合焊盘134包括铜、镍、金、银、铝、钨、上述的组合等。在一些实施例中,接合焊盘134的形成方法包括实施电化学镀工艺、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)、物理汽相沉积(PVD)、原子层沉积(ALD)等或上述的组合等以形成导电层并图案化该导电层。
参照图1D,在接合焊盘134上方形成钝化层140。钝化层140包括一层或多层合适的介电材料。例如,通过旋涂、层压或沉积形成钝化层140。在一些实施例中,钝化层140具有多层结构。在可选实施例中,钝化层140具有单层结构。在一些实施例中,例如,钝化层140的具有约6,000埃到约8,000埃的厚度。在一些实施例中,钝化层140的厚度为约6000、6500、7000、7500、8000埃,包括任何两个前面的值之间的任何范围。在一些实施例中,钝化层140是共形的层。在一些实施例中,可以通过在接合焊盘134上方共形地沉积钝化材料层来形成钝化层140。
在一些实施例中,钝化层140包括具有约2.16到2.18的折射率的压缩的基于氮化物的层。在一些实施例中,钝化层140具有多层结构,并且钝化层140的每一层是压缩的基于氮化物的层。在一些实施例中,当压缩的基于氮化物的层具有高紫外线透射率时,压缩的基于氮化物的层具有良好的耐酸性以为接合焊盘134提供保护。上文讨论了压缩的基于氮化物的层的形成方法和性能,因此这里省略了这些。在可选实施例中,钝化层140的材料包括诸如聚酰亚胺、阻焊剂、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、前述材料的组合等的聚合物。
在一些实施例中,介电层142进一步形成在接合焊盘134和钝化层140之间。例如,在一些实施例中,介电层142提高接合焊盘140和钝化层134之间粘合。在一些实施例中,在接合焊盘134上方形成介电层142,然后,在介电层142上方形成钝化层140。介电层142具有单层结构或多层结构。在一些实施例中,介电层142的材料与钝化层140的材料不同。在一些实施例中,介电层142包括诸如氧化物或含氮的介电材料的无机介电材料。在一些实施例中,无机介电材料包括氧化硅、氮氧化硅、前述的组合等。例如,在一些实施例中,介电层142的形成方法包括实施CVD或PECVD工艺。在一些实施例中,介电层142是共形的层。更具体地说,可以通过在接合焊盘134上方共形地沉积介电材料层来形成介电层142。在一个示例性实施例中,介电层142的厚度在从200埃到500埃的范围内。
如图1D所示,在一些实施例中,一般来说,在接合焊盘134上方形成钝化层140之后,在所形成的结构上实施针孔测试(pin hole test)。在一些实施例中,在热条件下使用酸溶液实施针孔测试,以确保钝化层140为接合焊盘134提供免于受到酸溶液腐蚀的保护。在一些实施例中,由于钝化层140包括压缩的基于氮化物的层,钝化层140具有良好的抗酸性从而保护接合焊盘134免受酸溶液的腐蚀。因此,半导体器件通过针孔测试。也就是说,接合焊盘134和半导体器件具有良好的可靠性。另一方面,在传统的半导体器件中,用作钝化层并位于接合焊盘上方的拉伸钝化层可能具有裂缝。因此,在针孔测试中,酸溶液通过钝化层中的裂缝腐蚀下面的接合焊盘,尤其是接合焊盘的底部拐角处。换言之,拉伸钝化层不能为接合焊盘提供良好的保护从而降低了半导体器件的可靠性。
参考图1E,图案化钝化层140和介电层142以由此形成开口144并且暴露出接合焊盘134的部分。例如,在一些实施例中,通过诸如湿蚀刻工艺或干蚀刻工艺的蚀刻工艺形成开口144。
在一些实施例中,连接件150形成在开口144中以电连接至接合焊盘134。例如,连接件150为导电凸块。例如,导电凸块为球、柱等。例如,在球栅阵列(BGA)封装中,导电凸块落入相应位置内。例如,连接件150的材料包括无铅合金(例如,金或Sn/Ag/Cu合金)、铅合金(例如,Pb/Sn合金)、铜、铝、铝铜、其他凸块金属材料和/或上述的组合。从而完成本发明的半导体器件100。
参考图1F,在一些实施例中,粘合层112在光热条件下分解,并且然后载体110从半导体器件100释放。此后,翻转半导体器件100。例如,通过激光钻孔工艺在介电层114中形成开口152。半导体器件100进一步电连接到半导体器件200,从而得到诸如PoP器件的堆叠结构。
在一些实施例中,半导体器件200具有衬底204,并且管芯202安装在衬底204的一个表面(例如,顶面)上。接合引线208是用来提供位于衬底204的相同顶面上的管芯202和焊盘206(诸如接合焊盘)之间的电连接。通孔(未示出)可以用于提供焊盘206和位于衬底204的相反表面(例如,底面)上的焊盘212(诸如接合焊盘)之间的电连接。连接件214连接焊盘212并且填充在开口152中以电连接至半导体器件100的通孔116。密封剂210形成在组件上方以保护组件免受环境和外部污染物的影响。
在一些实施例中,钝化层140的至少一个、介电层120到126、在接合焊盘134旁边的介电层130包括具有高紫外线透射率和良好抗酸性的压缩的基于氮化物的层。在一些实施例中,包括压缩的基于氮化物的层的钝化层140保护接合焊盘134免受腐蚀,从而接合焊盘134具有良好的电特性。因此,包括钝化层140和接合焊盘134的半导体器件100以及半导体器件100和半导体器件200的堆叠结构具有良好的可靠性。此外,在一些实施例中,包括压缩的基于氮化物的层的钝化层140和/或介电层120到126和介电层130具有高紫外线透射率,从而半导体器件100能够成为诸如使用双极-CMOS-DMOS(BCD)工艺的电源控制芯片或使用高压技术的触控芯片的需要一次性可编程(OTP)功能的器件。
在一些实施例中,通过在氮化物层中应用大于700瓦的射频(RF)和降低Si-H键比率,所形成的基于氮化物的层是压缩层。与诸如拉伸氮化硅层的拉伸基于氮化物的层相比,诸如压缩氮化硅层的压缩的基于氮化物的层具有良好的抗酸性、高紫外线透射率和在晶圆接合期间良好的粘附性。从而,在一些实施例中,使用压缩的基于氮化物的层作为接合焊盘上面的钝化层,钝化层保护接合焊盘免受在针孔测试期间的酸溶液腐蚀。此外,在一些实施例中,在诸如基于一次性可编程器件的半导体器件中使用压缩的基于氮化物的层作为钝化层和/或介电层,紫外线可以通过钝化层和/或介电层并且可以有效的擦除数据。因此,提供了半导体器件以及半导体器件和另一半导体器件的堆叠结构的电特性,半导体器件以及半导体器件和另一半导体器件的堆叠结构的可靠性是最佳的。
一种半导体器件包括管芯、导电结构、接合焊盘和钝化层。导电结构位于管芯上方并且电连接至管芯。接合焊盘位于导电结构上方并且电连接至导电结构。钝化层位于接合焊盘上方,其中,钝化层包括具有约2.16到2.18的折射率的基于氮化物的层。
一种半导体器件包括管芯和导电结构。导电结构位于管芯上方并且电连接至管芯。导电结构包括多个介电层和位于介电层中的多个导电部件,其中,介电层的至少一个包括具有约2.16到2.18的折射率的基于氮化物的层。
一种半导体器件的制造方法包括以下内容:导电结构形成在管芯上方。在导电结构上方形成接合焊盘。利用大于700瓦的射频(RF)在接合焊盘上方形成钝化层,其中,钝化层包括基于氮化物的层。
根据本发明的一个实施例,提供了一种半导体器件,包括:管芯;导电结构,位于所述管芯上方并且电连接至所述管芯;接合焊盘,位于所述导电结构上方并且电连接至所述导电结构;以及钝化层,位于所述接合焊盘上方,其中,所述钝化层包括具有2.16至2.18的折射率的基于氮化物的层。
在上述半导体器件中,在245nm,所述基于氮化物的层的材料包括氮化硅。
在上述半导体器件中,所述基于氮化物的层具有60%到80%的紫外线透射率。
在上述半导体器件中,所述基于氮化物的层是压缩层。
在上述半导体器件中,还包括位于所述钝化层和所述接合焊盘之间的介电层。
在上述半导体器件中,所述介电层的材料包括氧化硅。
在上述半导体器件中,通过位于所述钝化层和所述介电层中的开口暴露所述接合焊盘。
在上述半导体器件中,所述接合焊盘的材料包括铝或包括含铝导电材料。
根据本发明的另一实施例,还提供了一种半导体器件,包括:管芯;以及导电结构,位于所述管芯上方并且电连接至所述管芯,所述导电结构包括多个介电层和位于所述介电层中的多个导电部件,其中,至少一个所述介电层包括具有2.16至2.18的折射率的基于氮化物的层。
在上述半导体器件中,所述基于氮化物的层的材料包括氮化硅。
在上述半导体器件中,所述基于氮化物的层是压缩层。
在上述半导体器件中,在245nm,所述基于氮化物的层具有60%到80%的紫外线透射率。
在上述半导体器件中,所述基于氮化物的层用作蚀刻停止层。
根据本发明的又一实施例,还提供了一种半导体器件的制造方法,包括:在管芯上方形成导电结构;在所述导电结构上方形成接合焊盘;以及利用大于700瓦的射频在所述接合焊盘上方形成钝化层,其中,所述钝化层包括基于氮化物的层。
在上述制造方法中,通过等离子体增强化学汽相沉积形成所述钝化层。
在上述制造方法中,还包括在所述钝化层和所述接合焊盘之间形成介电层。
在上述制造方法中,还包括在所述钝化层和所述介电层中形成开口以暴露所述接合焊盘的部分。
在上述制造方法中,使用SiH4和NH3的反应物沉积所述钝化层。
在上述制造方法中,SiH4与NH3的比率小于0.08。
在上述制造方法中,所述基于氮化物的层是压缩层。上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本公开的各个方面。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。

Claims (1)

1.一种半导体器件,包括:
管芯;
导电结构,位于所述管芯上方并且电连接至所述管芯;
接合焊盘,位于所述导电结构上方并且电连接至所述导电结构;以及
钝化层,位于所述接合焊盘上方,其中,所述钝化层包括具有2.16至2.18的折射率的基于氮化物的层。
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