CN105895599A - 具有双侧堆叠结构的集成电路封装 - Google Patents

具有双侧堆叠结构的集成电路封装 Download PDF

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Publication number
CN105895599A
CN105895599A CN201610089028.6A CN201610089028A CN105895599A CN 105895599 A CN105895599 A CN 105895599A CN 201610089028 A CN201610089028 A CN 201610089028A CN 105895599 A CN105895599 A CN 105895599A
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China
Prior art keywords
integrated circuit
package
circuit lead
intermediate layer
hole
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CN201610089028.6A
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M·J·李
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Altera Corp
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Altera Corp
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Abstract

本发明涉及一种集成电路封装件，其可以包括附接到第二集成电路管芯的前表面的第一集成电路管芯。由成型复合物制成的中间层被形成为以“扇出”布置围绕第二集成电路管芯，同时留下第二集成电路管芯的表面暴露出来。因此，然后在中间层中形成一组通孔，并且该组通孔被填充有导电材料。这种配置形成双侧堆叠结构。该堆叠结构还可以适用于层叠封装的封装件和扇出晶片级芯片尺寸的封装件，其中该堆叠结构在两个异构或同构集成电路封装件之间形成。

Description

具有双侧堆叠结构的集成电路封装
本申请要求2015年2月18日提交的美国专利申请第14/625,020号的优先权，其全部公开内容通过引用合并于此。
背景技术
在半导体器件组装件中，集成电路管芯(也被称为半导体芯片或“管芯”)可以被安装在封装衬底上。随着对较高性能和密度的需求的增加，很多集成电路封装件已经在每单位面积上合并了更多的集成部件。在印刷电路板上，部件可以被放置地更靠近或者堆叠在一起以降低设备尺寸和成本。例如，管芯堆叠(例如，面对面管芯堆叠、面对背管芯堆叠)集成可能需要多管芯集成电路封装件以获得更好的性能和更高的密度。
另外，个体多管芯集成电路封装件还可以被堆叠在一起，以进一步提高堆叠的封装件的稳定性和可制造性。典型的层叠封装(package-on-package)堆叠技术可以使用具有预安装焊球的封装衬底或者具有直接连接到其各自的接触焊盘的焊球的面对背或面对面封装结构。然而，由于焊球安装工艺和材料成本，这样的器件封装件需要更高的加工成本以实现更精细的间距互连。为了避免使用典型的堆叠技术的昂贵的制造工艺，焊球需要被充分地远离彼此进行放置(即相隔超过300微米)，这不合期望地限制了集成电路封装件的互连密度。
发明内容
根据本发明，提供了用于创建具有双侧堆叠结构的集成电路封装件的装置和方法。
应当理解，可以以许多方式诸如工艺、装置、系统或设备来实现本发明。本发明的若干创造性实施例被描述如下。
本申请公开了一种通过工艺产生的集成电路封装件。产生集成电路封装件的工艺也可以包括提供第一集成电路管芯和第二集成电路管芯，其中第一集成电路管芯被附接到第二集成电路管芯的第一表面。产生集成电路封装件的工艺可以包括在第一集成电路管芯上形成中间层。可以围绕第二集成电路管芯形成中间层。可以在中间层中形成一组导电通孔，其中每个导电通孔被连接到第一集成电路管芯。通过在中间层中形成一组孔来形成该组导电通孔。在形成该组通孔之后，每个孔被填充导电材料。可以执行印刷工艺或挤压铸造工艺以便用导电材料填充该组通孔。
本申请公开了一种制作集成电路封装件的方法。该方法包括将第一集成电路管芯附接到第二集成电路管芯的前表面。然后，围绕第二集成电路管芯形成中间层。该方法进一步包括在第二集成电路管芯的前表面和附加中间层上方形成附加中间层。随后在中间层中形成一组导电通孔。可以执行堵塞或印刷工艺以便用导电材料填充该组通孔。如果需要，第三集成电路管芯被附接在中间层上。第三集成电路管芯可以通过中间层中的导电通孔被电耦接到第一集成电路管芯。可以在中间层中形成一组附加导电通孔。该组附加导电通孔可以通过额外的堵塞或印刷工艺被填充导电材料。
本申请公开了一种制造层叠封装设备的方法。该方法包括将集成电路管芯安装在封装衬底上以形成第一集成电路封装件。用成型复合物包封集成电路管芯，其中一组导电通孔稍后被形成在成型复合物中。该方法进一步包括在第一集成电路管芯和成型复合物上方形成中间层。随后，将第二集成电路封装件安装在第一集成电路封装件上。第二集成电路管芯通过该组导电通孔被电耦接到第一集成电路管芯。
从附图和优选实施例的以下详细描述，本发明的进一步的特征、它的本质和各种优势将更加明显。
附图说明
图1根据本发明的一个实施例示出具有两个集成电路管芯和成型复合物的说明性集成电路封装件的侧视图。
图2根据本发明的一个实施例示出用于形成图1中所示类型的双侧堆叠结构的制造工艺的说明性流程图。
图3根据本发明的一个实施例示出具有堆叠集成电路管芯的说明性层叠封装(PoP)封装件的侧视图。
图4根据本发明的一个实施例示出具有堆叠集成电路管芯的另一个说明性层叠封装(PoP)封装件的侧视图。
图5是根据本发明的一个实施例可被执行以组装集成电路封装件的说明性步骤的流程图。
图6是根据本发明的一个实施例可被执行以组装集成电路封装件的说明性步骤的另一个流程图。
具体实施方式
本文提供的实施例包括集成电路结构和用于创建具有双侧堆叠结构的集成电路封装件的封装技术。
然而，对于本领域技术人员来说显而易见的是，可以在没有参考相应的实施例所描述的这些具体细节中的一些或全部的情况下来实践当前的示例性实施例。在其他情况下，为了避免不必要地混淆当前的实施例，没有详细描述众所周知的操作。
图1根据本发明的一个实施例示出集成电路封装件100的侧视图。如图1所示，为了增加集成电路封装件100的封装密度，集成电路封装件100可以包括用面对面配置堆叠的两个集成电路管芯(例如，第一集成电路管芯101和第二集成电路管芯102)。例如，集成电路管芯101和集成电路管芯102被布置为使得集成电路管芯的相应前表面(例如，有源表面)面向彼此。支撑构件111可以被耦接在集成电路管芯101和集成电路管芯102之间以电连接集成电路管芯101和集成电路管芯102。例如，支撑构件111可以是铜柱。来自集成电路管芯101的信号可以通过支撑构件111行进到集成电路管芯102。还应当理解，在本文中可以采用具有不同配置的各种支撑构件111。作为示例，支撑构件111可以是微凸块。可以分配底部填充材料104诸如环氧树脂以填充集成电路管芯101和集成电路管芯102之间的间隙，以便提高集成电路管芯101和集成电路管芯102之间的键合。
随着对高密度集成电路封装件的需求增加，双侧堆叠结构(例如，堆叠结构120)可以是期望的，以适应精细间距缩放能力并解决与嵌入式集成电路管芯结构相关联的热管理问题。如本文所使用的术语“双侧”表示堆叠结构的顶表面和底表面能够连接到一个或多个集成电路封装件。在示例性实施例中，堆叠结构120可以包括具有信号传输结构(例如，导电通孔106)的中间层(例如，成型复合物103)。作为一个示例，在形成导电通孔106之前，可以围绕集成电路管芯102形成成型复合物103。如图1所示，导电通孔106可以在成型复合物103的顶表面和底表面之间延伸，并且连接到集成电路管芯101上的接触焊盘108以形成信号传输结构。这种堆叠结构通过消除使用具有内置预安装焊球的封装衬底提供了在层叠封装堆叠中进行精细间距缩放的能力，具有内置预安装焊球的封装衬底需要较粗的间距。稍后将参考图2描述由区域105强调的堆叠结构120的更详细描述。
堆叠集成电路管芯101和堆叠集成电路管芯102可以通过微凸块107被耦接到封装衬底125。如图1所示，微凸块107中的每一个被键合到成型复合物103中的导电通孔106中相应的通孔。这种配置允许来自集成电路管芯101的信号通过微凸块107被传达到封装衬底125，并且允许来自衬底126的信号通过微凸块107被传达到管芯101。如图1所示，封装衬底125可以包括一个或多个导电迹线，诸如用于信号路由目的的导电迹线110。一层或多层堆积膜121(也被称为阻焊层)可以被应用于封装衬底125的顶表面和/或底表面上以保护和隔离封装衬底125中的导电迹线免受氧化。
形成于封装衬底125的顶表面上的一组接触焊盘(例如，接触焊盘109)可以通过微凸块107被耦接到成型复合物103。相应地，形成于封装衬底125的底表面上的另一组接触焊盘(例如，接触焊盘122)可以被耦接到焊球123以从集成电路封装件100向外传输信号。可以使用任何期望的常规制造方法来执行接触焊盘109和接触焊盘122的制作，并且因此为了避免不必要地混淆本发明而不详细地描述。可以分配底部填充物104以填充集成电路管芯102、成型复合物103和封装衬底125之间的间隙，以便提高集成电路管芯102、成型复合物103和封装衬底125之间的键合。
随后，导热盖或热扩散盖(例如，热扩散盖115)可以被附接到封装衬底125。如图1所示，热扩散盖115具有“帽形”构型。作为示例，“帽形”热扩散盖115具有通过直立边缘部分从封装件的侧壁升高的平面(例如，表面124)。另外，类似帽子边缘的唇部(例如，唇部126)可以从直立边缘部分向外延伸。应当理解，为了有效地从集成电路封装件100向外传递由集成电路部件诸如集成电路管芯101产生的热量，可以由高导电材料形成热扩散盖115。热扩散盖115可以基本上覆盖集成电路管芯101和封装衬底125的顶部表面以保护集成电路管芯101免受外部污染物和损坏。
图2根据本发明的一个实施例示出了用于形成如由图1的区域105强调的图1的双侧堆叠结构120的制造工艺的说明性流程图。如上所述，堆叠结构120包括具有导电通孔106的中间层(例如，成型复合物103)。
在步骤201中，为了形成堆叠结构120，图1的堆叠集成电路管芯101和堆叠集成电路管芯102可以被反转或翻转以使得集成电路管芯101的顶表面(或有源表面)面朝上。以此方式，成型复合物103可以容易地形成在集成电路管芯101上。成型复合物103可以促进热传递，因此允许从集成电路管芯102更好地散热。成型复合物103还可以保护集成电路管芯101和集成电路管芯102以及它们的电气连接(未示出)免受破坏和危险的环境污染物。成型复合物可以是任何合适的材料，并且在一个实施例中可以由环氧树脂和陶瓷填充材料的混合物组成。
在步骤202中，多个开口(在本文有时被称为孔或通孔)被形成于成型复合物103中。如图2所示，通孔210可以从成型复合物103的顶表面延伸到底表面并延伸到集成电路管芯101上的接触焊盘108以形成信号传输结构。作为一个示例，可以通过钻孔或激光打孔穿过成型复合物103形成通孔210。随后，在步骤203中，通孔210被填充导电金属以形成导电通孔106。例如，可以通过印刷工艺或堵塞工艺形成导电通孔106，其中导电金属(以糊状或粉末的形式)被沉积在通孔210中。可替代地，可以通过铸造工艺(例如，挤压铸造工艺)形成导电通孔106，其中熔融导电金属被挤压到通孔210中且然后凝固。除其他外，导电金属的示例可以包括铜、钨、锡铅、锡铜和锡银铜。
双侧堆叠结构可以被实现以适应各种封装设备配置。图3根据本发明的一个实施例示出具有堆叠集成电路管芯的说明性层叠封装(PoP)封装件300的侧视图。应当理解，PoP封装件300可以与图1的集成电路封装件100共享相似的元件。因此，为了简洁起见，将不再详细描述上面已经描述的结构和元件，诸如底部填充物104、导电通孔106、导电迹线110、导电焊盘109和导电焊盘122、封装衬底125、堆积膜121、微凸块107、焊球123和热扩散盖115。
如图3所示，PoP封装件300可以包括以PoP布置堆叠在一起的两个集成电路封装件(例如，第一集成电路封装件341A和第二集成电路封装件341B)。集成电路封装件中的每一个可以包括由异构技术制成的一个或多个集成电路管芯，其可以被称为异构集成。例如，集成电路管芯可以包括微处理器、专用集成电路(ASIC)、存储器等。在一个实施例中，集成电路封装件341A可以包括实现面对面堆叠的两个集成电路管芯(例如集成电路管芯301和集成电路管芯302)的管芯堆叠。支撑构件111可以耦接在集成电路管芯301和集成电路管芯302之间，用于电气和信号通信。因此，集成电路封装件341B可以包括彼此相邻布置的两个集成电路管芯(例如，第一集成电路管芯303和第二集成电路管芯304)。
为了使用集成电路封装件341A和集成电路封装件341B形成PoP布置，提供了两个双侧堆叠结构(例如，堆叠结构320A和堆叠结构320B)。如图3所示，堆叠结构320A包括以“扇出(fun-out)”(即向外延伸)布置围绕集成电路管芯301的侧壁形成的中间层(例如，成型复合物103)。相应地，在成型复合物103中形成多个通孔(例如，导电通孔106)作为信号传输结构。类似于堆叠结构320A，堆叠结构320B也包括具有信号传输结构(例如，导电线306和导电通孔307)的中间层(例如，中间层333)。如图3所示，在集成电路管芯301的表面和成型复合物103上方形成中间层333，用于结构支撑和物理隔离。中间层333的示例可以包括钝化层、堆积层和预浸渍层。
在图3的实施例中，中间层333可以包括两个层：下层(例如，层310)和上层(例如，层312)。在层310中，将导电通孔106连接到集成电路管芯301上的接触焊盘305的多个导电线(例如，导电线306)可以向外扇出。在层312中，导电通孔307被形成用于电连接导电线306和支撑构件111。在一个实施例中，导电通孔307通过导电线306将来自集成电路管芯301 341A的信号转送到集成电路管芯303和集成电路管芯304(并且反之亦然)。在图3的示例性实施例中，通过钻出或激光打出一个或多个开口或通孔(例如，图2的通孔210)来形成导电通孔307，以使导电线306的一部分暴露出来。紧随其后的是用糊状或粉末形式的导电金属(例如，铜、钨、锡铅、锡铜和锡银铜)填充开口以形成导电通孔307的工艺。可以通过印刷、堵塞或挤压铸造方法来完成这样的工艺。应当理解，导电通孔307的位置、形状和大小仅用于说明的目的，而不是进行限制。
随后，集成电路封装件341B通过堆叠结构320B被堆叠在集成电路封装件341A的顶部上。如图3所示，堆叠结构320B内的信号传输结构(例如，导电线306和导电通孔307)允许集成电路封装件341B中的集成电路管芯303和集成电路管芯304通过支撑构件111电连接到集成电路封装件341A的集成电路管芯302。
为了完成组装，堆叠的集成电路封装件(例如，集成电路封装件341A和集成电路封装件341B)被安装在封装衬底125上。因此，热扩散盖115可以被布置在封装衬底125和堆叠的集成电路封装件结构上方以保护堆叠的集成电路结构免受外部污染物以及允许热量从PoP封装件300中逸出。被布置在封装衬底125的底表面上的焊料凸块或焊球123可以被用于将PoP封装件300连接到外部电路系统。
在某些情况下，可以提供同构集成电路封装件。图4根据本发明的一个实施例示出具有双侧堆叠结构的说明性集成电路封装设备400的侧视图。应当理解，集成电路封装设备400可以与图1和图3的集成电路封装件100和PoP封装件300共享相似的元件。因此，为了简洁起见，将不再详细描述上面已经描述的结构和元件，诸如成型复合物103、导电通孔106和微凸块107。如图4所示，集成电路封装设备400可以包括两个同构晶片级芯片尺寸的封装件(例如，第一封装件425A和第二封装件425B)。术语“同构”可以指具有至少在尺寸、复杂性、功能性、信号类型等方面基本类似的集成电路结构的封装件。例如，封装件425A可以包括集成电路管芯401A，而封装件425B可以包括集成电路管芯401B，其中在这两个封装件中的集成电路管芯彼此是同构的。
集成电路管芯401A和集成电路管芯401B中的每一个可以被成型复合物(例如，成型复合物403A、成型复合物403B等)围绕。类似于图3的成型复合物103，成型复合物403A和成型复合物403B是围绕相应的集成电路管芯形成的“扇出”(即向外延伸)成型复合物(例如，围绕集成电路管芯401A形成成型复合物403A，围绕集成电路管芯401B形成成型复合物403B)。成型复合物的“扇出”布置可以保护集成电路管芯401A和集成电路管芯401B免受外部污染物。该示例仅是说明性的，并且一般来说可以以任何期望的布置形成任何成型复合物403。
在一个实施例中，在每个集成电路管芯的前表面(或有源表面)和它相应的成型复合物上方形成双侧堆叠结构(例如，堆叠结构420A、堆叠结构420B)。双侧堆叠结构可以包括具有信号传输结构的中间层(例如，中间层444A、中间层444B)。例如，为了形成堆叠结构420A，集成电路管芯401A和成型复合物403A可以被反转或翻转，使得集成电路管芯401A的前表面(或有源表面)面朝上。这样一来，中间层444A可以容易地形成在成型复合物403A和集成电路管芯401A上方。
在一个实施例中，中间层444A可以包括两层：下层(例如，层410A)和上层(例如，层412A)。例如，在层410A中，可以形成在另一个“扇出”布置中的多个导电线(例如，导电线406A)并且将其连接到成型复合物403A的导电通孔106和集成电路管芯401A的接触焊盘402A。这样的布置可以延伸集成电路管芯401A的原始连接点(例如，接触焊盘402A)远离集成电路管芯401A的置着区(footprint)，这允许集成电路管芯401A被连接到集成电路封装设备400内的其他电气部件。在层412A中，接触元件诸如焊球408被沉积在焊盘450A上并且可以被电连接到导电线406A以促进进出封装件425A的可靠的信号传输。在一些实施例中，如果需要，封装件425A可以被倒置(或反转)，使得中间层420A朝向封装衬底(未示出)面向下，其中封装件425A被安装在封装衬底上。例如，封装衬底可以是印刷电路板衬底，并且封装件425A可以通过焊球408被连接到印刷电路板。封装件425B的层410B和层412B的架构与封装件425A的层410A和层412A的架构相同。因此，为了简洁起见，应当理解，将不再描述层410B和层412B中所示的部件(例如，接触焊盘402B、导电线406B和焊盘450B)。
为了形成集成电路封装设备400，封装件425B可以被堆叠在封装件425A的顶部上。在将封装件425B堆叠到封装件425A之前，使用类似于上面参考图2所描述的方法，首先在每个封装件的成型复合物(例如，成型复合物103)中形成多个导电通孔(例如，导电通孔106)。这样的配置形成堆叠结构441B，其目的主要是为了适应精细间距缩放能力。相应地，在导电通孔106上形成微凸块107。如图4所示，每个微凸块107被键合到封装件425A的导电通孔106中对应的通孔。
在将封装件425B堆叠到封装件425A期间，微凸块107被定位成与封装件425B的焊盘450B相邻，并且执行回流工艺以建立封装件425A与封装件425B之间的电气和机械键合。来自封装件425A的集成电路管芯401A的信号可以通过微凸块107行进到封装件425B的集成电路管芯401B。应当理解，虽然在图4的实施例中示出了两个芯片尺寸封装件(例如，封装件425A和封装件425B)，但在本文中可以采用任何数量的芯片尺寸封装件。
图5是根据本发明的一个实施例可以由集成电路封装组装仪器执行以组装集成电路封装件的说明性步骤的流程图。应当理解，图3的实施例可以被用作示例以说明下面所描述的步骤。在一个实施例中，集成电路封装件可以是集成电路层叠封装(PoP)设备(例如，图3的PoP封装件300)，其中两个或更多个集成电路封装件被堆叠且一体形成。例如，如图3所示，PoP封装件300可以包括以PoP布置堆叠在一起的两个集成电路封装件(例如，集成电路封装件341A和集成电路封装件341B)。
在第一集成电路封装件(例如，图3的集成电路封装件341A)中，在步骤501处，第一集成电路管芯被附接到第二集成电路管芯的顶表面。在示例性实施例中，一组导电柱(例如，图1的支撑构件111)可以被附接在第一集成电路管芯与第二集成电路管芯之间。例如，如图3所示，第一集成电路管芯(例如，集成电路管芯301)通过支撑构件111被电耦接到第二集成电路管芯(例如，集成电路管芯302)。在另一个示例中，支撑构件111可以包括微凸块。在一个实施例中，支撑构件111可以充当集成电路管芯之间的通信路径。例如，来自集成电路管芯301的信号可以通过支撑构件111被传达到集成电路管芯302。相应地，可以分配底部填充材料(例如，底部填充材料104)以填充集成电路管芯301与集成电路管芯302之间的间隙。
在步骤502处，形成成型复合物以围绕第一集成电路管芯。例如，如图3所示，成型复合物103被形成以“扇出”(即向外延伸)布置围绕集成电路管芯302，同时留下集成电路管芯302的上表面暴露出来。可以执行成型工艺(例如，注塑成型工艺)以将集成电路管芯302的侧壁围封在成型复合物内。
然后在步骤504处，在成型复合物中形成一组导电通孔。在一个实施例中，成型复合物和该组导电通孔共同形成第一双侧堆叠结构(例如，图3的堆叠结构320A)。例如，如图3所示，导电通孔106在成型复合物103的顶表面与底表面之间延伸以形成信号传输结构。可以通过钻孔穿过成型复合物103来形成导电通孔106(或通孔)。随后，每个通孔可以被填充导电金属(例如，铜、钨、锡铅、锡铜和锡银铜)。在一个实施例中，通过印刷工艺形成导电通孔106，其中导电金属(以糊状或粉末的形式)被印刷(或堵塞)到通孔(例如，图2的通孔210)中。在另一个实施例中，通过挤压铸造工艺形成导电通孔106，其中熔融导电金属被挤压到通孔中且然后被凝固。
在步骤504处，在第一集成电路管芯的上表面和成型复合物上方形成中间层。如图3所示，在集成电路管芯301的顶表面和成型复合物103上方形成中间层333。在一个实施例中，中间层333包括两个层：下层(例如，层310)和上层(例如，层312)。在层310中，多个导电线(例如，导电线306)可以被形成并连接到成型复合物103的导电通孔106和集成电路管芯301的接触焊盘305。
在步骤505处，在中间层中形成一组附加导电通孔。在一个实施例中，中间层和该组附加导电通孔共同形成第二双侧堆叠结构(例如，图3的堆叠结构320B)。例如，如图3所示，导电通孔307被形成在中间层的上层(例如，层312)中。可以通过与导电通孔106相似的制作工艺形成导电通孔307。在一个实施例中，堆叠结构可以充当用于连接PoP布置的两个或更多个集成电路封装件的连接桥。导电通孔307可以充当用于在两个集成电路封装件之间的信号传输的连接器。
在步骤506处，在第二集成电路封装件(例如，图3的集成电路封装件341B)中，第三集成电路管芯被附接在第二堆叠结构上。这样的布置形成PoP结构。如图3所示，第三集成电路管芯(例如，集成电路管芯303)可以被附接在堆叠结构320B的中间层312的顶部上。支撑构件111可以耦接在集成电路管芯303和中间层320B之间，用于电气通信。例如，支撑构件111可以是铜柱。来自集成电路管芯303的信号可以通过支撑构件111和307以及导电线306行进到集成电路管芯301。如果需要，附加集成电路管芯可以被附接在中间层上。例如，如图3所示，第四集成电路管芯(例如，集成电路管芯304)可以被附接到中间层320B。支撑构件111可以耦接在集成电路管芯304与中间层320B之间，用于电气连接。
在步骤507处，第一集成电路管芯和成型复合物被附接到封装衬底。在图3所示的示例中，集成电路管芯301和成型复合物103通过微凸块107被安装在封装衬底125上。在一个实施例中，每个微凸块107可以连接到成型复合物103中的导电通孔106中对应的通孔。可以进行回流工艺，使得成型复合物103通过微凸块107被机械连接和电连接到封装衬底125。作为示例，在大约250℃的回流温度下，微凸块107可以被热回流。
在步骤508处，底部填充材料被沉积在第一集成电路管芯和成型复合物下方的封装衬底上。例如，如图3所示，底部填充物104被分配以填充集成电路管芯301、成型复合物103和封装衬底125之间的间隙，以便改进集成电路管芯301、成型复合物103和封装衬底125之间的键合。
在步骤509处，热扩散盖被布置在第一集成电路封装件和第二集成电路封装件上方。可以由高传导材料制成热扩散盖，以便从PoP结构向外有效地传递由集成电路部件(例如，图3的集成电路管芯301、302、303和304)产生的热量。例如，如图3所示，热扩散盖(例如，热扩散盖115)可以充分覆盖集成电路管芯341A和集成电路封装件341B以及封装衬底125的顶表面以保护集成电路管芯301、302、303和304免受外部污染物。
图6是根据本发明的实施例可以由集成电路封装组装仪器执行以组装集成电路封装件的说明性步骤的另一流程图。应当理解，图4的实施例可以被用作示例以说明下面所描述的步骤。
在步骤601处，集成电路管芯被安装在封装衬底上以形成第一集成电路封装件。如图4所示，集成电路管芯(例如，集成电路管芯401A)可以通过焊球408被安装在封装衬底(未示出)上。例如，封装衬底可以是印刷电路板衬底。
在步骤602处，用成型复合物包封集成电路管芯。如图4所示，成型复合物103可以以“扇出”布置围绕集成电路管芯401A的侧壁进行沉积。术语“扇出”可以表示通过从集成电路管芯401A的侧壁向外延伸来形成成型复合物103。在一个实施例中，在步骤603处，在成型复合物103中形成一组导电通孔(例如，导电通孔106)。这样的配置形成堆叠结构425A，如上面参考图3所提到，它的目的可以主要是适应精细间距缩放能力，并且解决与集成电路管芯401A相关联的热管理问题。
在步骤604处，在第一集成电路管芯的前表面(例如，有源表面)和成型复合物上方形成中间层。如图4所示，该中间层可以包括两个层(例如，层410A和层412A)。在层410A中，导电线406A被形成并连接到导电通孔106和集成电路管芯401A的接触焊盘402A。在层412B中，焊盘410A被形成以电连接到导电线406A。相应地，微凸块107可以被焊接到成型复合物103的相对表面上的导电通孔106。
在步骤605处，第二集成电路封装件可以被堆叠在第一集成电路封装件上，从而形成层叠封装设备。第二集成电路封装件(例如，封装件425B)可以与第一集成电路封装件(例如，封装件425B)是同构的，这意味着封装件425B具有与封装件425A至少在大小、复杂性、功能性、信号类型等方面基本类似的包括堆叠结构的集成电路结构。在将封装件425B堆叠到封装件425A期间，微凸块107被回流焊接以形成封装件425A和封装件425B之间的电气和机械键合。同样地，来自集成电路管芯401B的信号可以通过微凸块107行进到封装件425A的集成电路管芯401A。
本文所描述的方法和装置可以被并入任何合适的电路。例如，方法和装置可以被并入到许多类型的设备诸如微处理器或其他集成电路中。示例性集成电路包括可编程阵列逻辑(PAL)、可编程逻辑阵列(PLA)、现场可编程逻辑阵列(FPLA)、电可编程逻辑设备(EPLD)、电可擦除可编程逻辑设备(EEPLD)、逻辑单元阵列(LCA)、现场可编程门阵列(FPGA)、专用标准产品(ASSP)、专用集成电路(ASIC)和微处理器，仅举几例。
虽然以特定的顺序描述了方法操作，但应当理解，可以在所描述的操作之间执行其他操作，可以调节所描述的操作，使得它们发生在不同的时间，或者所描述的操作可以被分布在允许处理操作发生在与处理相关联的各种间隔处的系统中，只要以期望的方式执行交叠操作的处理即可。
附加实施例：
附加实施例1.一种通过工艺产生的集成电路封装件，所述工艺包括：提供第一集成电路管芯；提供具有相对的第一表面和第二表面的第二集成电路管芯，并且将第一集成电路管芯附接到第二集成电路管芯的第一表面；在第一集成电路管芯上且围绕第二集成电路管芯形成中间层；在中间层中形成多个通孔；以及在形成多个通孔之后，用导电材料填充多个通孔。
附加实施例2.根据附加实施例1所述的集成电路封装件，其中第二集成电路管芯的第一表面包括第二集成电路管芯的有源表面，晶体管形成于第二集成电路管芯的有源表面中。
附加实施例3.根据附加实施例1所述的集成电路封装件，其中使用印刷工艺将多个通孔填充导电材料。
附加实施例4.根据附加实施例1所述的集成电路封装件，其中使用挤压铸造工艺将多个通孔填充导电材料。
附加实施例5.根据附加实施例1所述的集成电路封装件，其中导电材料从由铜、钨、锡铅、锡铜和锡银铜组成的群组中选择。
附加实施例6.根据附加实施例1所述的集成电路封装件，其中中间层包括钝化层。
附加实施例7.根据附加实施例1所述的集成电路封装件，其中中间层包括成型层。
附加实施例8.根据附加实施例1所述的集成电路封装件，其中产生集成电路封装件的工艺进一步包括：提供封装衬底并且将中间层附接到封装衬底。
附加实施例9.根据附加实施例8所述的集成电路封装件，其中产生集成电路封装件的工艺进一步包括：将底部填充材料沉积在中间层和第二集成电路管芯下方的封装衬底上。
附加实施例10.根据附加实施例9所述的集成电路封装件，其中产生集成电路封装件的工艺进一步包括：在第一集成电路管芯、第二集成电路管芯和封装衬底上方形成热扩散盖。
附加实施例11.一种制作集成电路封装件的方法，所述方法包括：将第一集成电路管芯附接到第二集成电路管芯的前表面；形成围绕第二集成电路管芯的中间层；在第二集成电路管芯的前表面和中间层上方形成附加中间层；在附加中间层中形成多个通孔；以及执行堵塞工艺以便用导电材料填充多个通孔。
附加实施例12.根据附加实施例11所述的方法，其中将第一集成电路管芯附接到第二集成电路管芯的前表面包括使用多个导电互连将第二集成电路管芯电耦接到第一集成电路管芯。
附加实施例13.根据附加实施例11所述的方法，其中形成中间层包括形成围绕第二集成电路管芯的成型复合物。
附加实施例14.根据附加实施例13所述的方法，其中形成围绕第二集成电路管芯的中间层包括：在中间层中形成多个附加通孔；以及执行额外的堵塞工艺以便用导电材料填充中间层中的多个附加通孔。
附加实施例15.根据附加实施例14所述的方法，进一步包括：通过焊料凸块将第一集成电路管芯和中间层附接到封装衬底，其中焊料凸块中的每一个被键合到多个附加通孔中对应的通孔。
附加实施例16.根据附加实施例15所述的方法，进一步包括：将第三集成电路管芯附接在附加中间层上，其中第三集成电路管芯通过附加中间层中的多个通孔被电耦接到第一集成电路管芯。
附加实施例17.根据附加实施例16所述的方法，进一步包括：将底部填充材料沉积在第一集成电路管芯和中间层下方的封装衬底上。
附加实施例18.根据附加实施例17所述的方法，进一步包括：在第一集成电路管芯、第二集成电路管芯和第三集成电路管芯以及封装衬底上布置热扩散盖。
附加实施例19.一种制造层叠封装设备的方法，所述方法包括：将集成电路管芯安装在封装衬底上以形成第一集成电路封装件；用成型复合物包封集成电路管芯；在成型复合物中形成多个开口，其中多个开口中的每一个通过挤压铸造工艺而填充导电材料以形成多个导电通孔；在集成电路管芯和成型复合物上方形成钝化层；以及通过钝化层将第二集成电路封装件安装在第一集成电路封装件上。
附加实施例20.根据附加实施例19所述的方法，其中通过钝化层将第二集成电路封装件安装在第一集成电路封装件上包括通过焊料凸块将第二集成电路封装件电耦接到第一集成电路封装件，其中焊料凸块中的每一个被键合到多个开口中对应的开口中的导电材料。
附加实施例21.根据附加实施例19所述的方法，其中第二集成电路封装件包括附加集成电路管芯，并且其中将第二集成电路封装件安装在第一集成电路封装件上包括通过多个开口将附加集成电路管芯电耦接到集成电路管芯。
上述仅是本发明的原理的举例说明，并且在不偏离本发明的保护范围和精神的情况下，可以由本领域中的技术人员做出各种修改。可以单独或以任何组合实现上述实施例。

Claims (20)

1.一种通过工艺产生的集成电路封装件，所述工艺包括：
提供第一集成电路管芯；
提供具有相对的第一表面和第二表面的第二集成电路管芯，并且将所述第一集成电路管芯附接到所述第二集成电路管芯的所述第一表面；
在所述第一集成电路管芯上且围绕所述第二集成电路管芯形成中间层；
在所述中间层中形成多个通孔；以及
在形成所述多个通孔之后，用导电材料填充所述多个通孔。
2.根据权利要求1所述的集成电路封装件，其中所述第二集成电路管芯的所述第一表面包括所述第二集成电路管芯的有源表面，晶体管形成于所述有源表面中。
3.根据权利要求1所述的集成电路封装件，其中使用印刷工艺用所述导电材料填充所述多个通孔。
4.根据权利要求1所述的集成电路封装件，其中使用挤压铸造工艺用所述导电材料填充所述多个通孔。
5.根据权利要求1所述的集成电路封装件，其中从由铜、钨、锡铅、锡铜和锡银铜组成的群组中选择所述导电材料。
6.根据权利要求1所述的集成电路封装件，其中所述中间层包括钝化层。
7.根据权利要求1所述的集成电路封装件，其中所述中间层包括成型层。
8.根据权利要求1所述的集成电路封装件，其中产生所述集成电路封装件的所述工艺进一步包括：
提供封装衬底并且将所述中间层附接到所述封装衬底。
9.根据权利要求8所述的集成电路封装件，其中产生所述集成电路封装件的所述工艺进一步包括：
将底部填充材料沉积在所述中间层和所述第二集成电路管芯下方的所述封装衬底上；以及
在所述第一集成电路管芯、所述第二集成电路管芯和所述封装衬底上方形成热扩散盖。
10.一种制作集成电路封装件的方法，所述方法包括：
将第一集成电路管芯附接到第二集成电路管芯的前表面；
形成围绕所述第二集成电路管芯的中间层；
在所述第二集成电路管芯的所述前表面和所述中间层上方形成附加中间层；
在所述附加中间层中形成多个通孔；以及
执行堵塞工艺以便用导电材料填充所述多个通孔。
11.根据权利要求10所述的方法，其中将所述第一集成电路管芯附接到所述第二集成电路管芯的所述前表面包括使用多个导电互连件将所述第二集成电路管芯电耦接到所述第一集成电路管芯。
12.根据权利要求10所述的方法，其中形成所述中间层包括形成围绕所述第二集成电路管芯的成型复合物。
13.根据权利要求12所述的方法，其中形成围绕所述第二集成电路管芯的所述中间层包括：
在所述中间层中形成多个附加通孔；以及
执行附加堵塞工艺以便用所述导电材料填充所述中间层中的所述多个附加通孔。
14.根据权利要求13所述的方法，进一步包括：
通过焊料凸块将所述第一集成电路管芯和所述中间层附接到封装衬底，其中每一个所述焊料凸块被键合到所述多个附加通孔中的相应通孔。
15.根据权利要求14所述的方法，进一步包括：
将第三集成电路管芯附接到所述附加中间层上，其中所述第三集成电路管芯通过所述附加中间层中的所述多个通孔被电耦接到所述第一集成电路管芯。
16.根据权利要求15所述的方法，进一步包括：
将底部填充材料沉积在所述第一集成电路管芯和所述中间层下方的所述封装衬底上。
17.根据权利要求16所述的方法，进一步包括：
在所述第一集成电路管芯、所述第二集成电路管芯和所述第三集成电路管芯以及所述封装衬底上设置热扩散盖。
18.一种制造层叠封装设备的方法，所述方法包括：
将集成电路管芯安装在封装衬底上以形成第一集成电路封装件；
用成型复合物包封所述集成电路管芯；
在所述成型复合物中形成多个开口，其中所述多个开口中的每一个通过挤压铸造工艺填充有导电材料以形成多个导电通孔；
在所述集成电路管芯和所述成型复合物上方形成钝化层；以及
通过所述钝化层将第二集成电路封装件安装在所述第一集成电路封装件上。
19.根据权利要求18所述的方法，其中通过所述钝化层将所述第二集成电路封装件安装在所述第一集成电路封装件上包括通过焊料凸块将所述第二集成电路封装件电耦接到所述第一集成电路封装件，其中每一个所述焊料凸块被键合到所述多个开口中的相应开口中的所述导电材料。
20.根据权利要求18所述的方法，其中所述第二集成电路封装件包括附加集成电路管芯，并且其中将所述第二集成电路封装件安装在所述第一集成电路封装件上包括通过所述多个开口将所述附加集成电路管芯电耦接到所述集成电路管芯。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845625A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 芯片封装结构
CN108155153A (zh) * 2016-12-05 2018-06-12 台湾积体电路制造股份有限公司 用于散热的封装结构的制造方法
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10626012B2 (en) * 2015-04-13 2020-04-21 Infineon Technologies Ag Semiconductor device including a cavity lid
US10340253B2 (en) * 2017-09-26 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
KR102465369B1 (ko) * 2018-03-05 2022-11-10 삼성전자주식회사 패키지 온 패키지의 제조방법 및 그의 본딩 장치
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
TWI718772B (zh) 2019-11-20 2021-02-11 元太科技工業股份有限公司 顯示裝置

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167079A1 (en) * 2001-05-11 2002-11-14 Han-Ping Pu Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
US20080157328A1 (en) * 2006-12-27 2008-07-03 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20080230898A1 (en) * 2007-03-19 2008-09-25 Spansion Llc Semiconductor device and method for manufacturing thereof
US20110210444A1 (en) * 2010-02-26 2011-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Package Using An Interposer
TW201209980A (en) * 2010-08-30 2012-03-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
US20130026609A1 (en) * 2010-01-18 2013-01-31 Marvell World Trade Ltd. Package assembly including a semiconductor substrate with stress relief structure
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN102931102A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装的方法
US8633598B1 (en) * 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法
CN103779235A (zh) * 2012-10-19 2014-05-07 台湾积体电路制造股份有限公司 扇出晶圆级封装结构
CN103915413A (zh) * 2012-12-28 2014-07-09 台湾积体电路制造股份有限公司 层叠封装接合结构

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6370013B1 (en) * 1999-11-30 2002-04-09 Kyocera Corporation Electric element incorporating wiring board
WO2001073843A1 (fr) * 2000-03-29 2001-10-04 Rohm Co., Ltd. Dispositif semi-conducteur
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US7548430B1 (en) * 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US6659512B1 (en) * 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
JP4137659B2 (ja) * 2003-02-13 2008-08-20 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7141884B2 (en) * 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US20080217761A1 (en) * 2007-03-08 2008-09-11 Advanced Chip Engineering Technology Inc. Structure of semiconductor device package and method of the same
US20100103634A1 (en) * 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
KR100909322B1 (ko) * 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
JP5341337B2 (ja) * 2007-10-25 2013-11-13 スパンション エルエルシー 半導体装置及びその製造方法
US7859120B2 (en) * 2008-05-16 2010-12-28 Stats Chippac Ltd. Package system incorporating a flip-chip assembly
JP4278007B1 (ja) * 2008-11-26 2009-06-10 有限会社ナプラ 微細空間への金属充填方法
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9293401B2 (en) * 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US7943428B2 (en) * 2008-12-24 2011-05-17 International Business Machines Corporation Bonded semiconductor substrate including a cooling mechanism
US9299648B2 (en) * 2009-03-04 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with patterned substrate and method of manufacture thereof
US8710634B2 (en) * 2009-03-25 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US8164171B2 (en) * 2009-05-14 2012-04-24 Megica Corporation System-in packages
US8623753B1 (en) * 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8466567B2 (en) * 2010-09-16 2013-06-18 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
US8399305B2 (en) * 2010-09-20 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming dam material with openings around semiconductor die for mold underfill using dispenser and vacuum assist
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US8994176B2 (en) * 2012-12-13 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
KR20150058940A (ko) * 2013-11-21 2015-05-29 삼성전자주식회사 히트 스프레더를 갖는 반도체 패키지

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167079A1 (en) * 2001-05-11 2002-11-14 Han-Ping Pu Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
US6610560B2 (en) * 2001-05-11 2003-08-26 Siliconware Precision Industries Co., Ltd. Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
US20080157328A1 (en) * 2006-12-27 2008-07-03 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20080230898A1 (en) * 2007-03-19 2008-09-25 Spansion Llc Semiconductor device and method for manufacturing thereof
US20130026609A1 (en) * 2010-01-18 2013-01-31 Marvell World Trade Ltd. Package assembly including a semiconductor substrate with stress relief structure
US20110210444A1 (en) * 2010-02-26 2011-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Package Using An Interposer
TW201209980A (en) * 2010-08-30 2012-03-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN102931102A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装的方法
US8633598B1 (en) * 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
CN103988294A (zh) * 2011-10-10 2014-08-13 马维尔国际贸易有限公司 包括具有应力减轻结构的半导体衬底的封装组件
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法
CN103779235A (zh) * 2012-10-19 2014-05-07 台湾积体电路制造股份有限公司 扇出晶圆级封装结构
CN103915413A (zh) * 2012-12-28 2014-07-09 台湾积体电路制造股份有限公司 层叠封装接合结构

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845625A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 芯片封装结构
US11410956B2 (en) 2016-09-19 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump
CN108155153A (zh) * 2016-12-05 2018-06-12 台湾积体电路制造股份有限公司 用于散热的封装结构的制造方法
CN108155153B (zh) * 2016-12-05 2022-11-11 台湾积体电路制造股份有限公司 半导体装置、管芯堆叠结构、封装结构及其制造方法
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
US11417620B2 (en) 2017-03-30 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redestribution layer
US11887952B2 (en) 2017-03-30 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redistribution layer

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