CN107799481A - 半导体封装装置及制造半导体封装装置的方法 - Google Patents

半导体封装装置及制造半导体封装装置的方法 Download PDF

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CN107799481A
CN107799481A CN201710740207.6A CN201710740207A CN107799481A CN 107799481 A CN107799481 A CN 107799481A CN 201710740207 A CN201710740207 A CN 201710740207A CN 107799481 A CN107799481 A CN 107799481A
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electronic building
building brick
encapsulation
circuit layer
electric contact
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CN107799481B (zh
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方绪南
庄淳钧
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

半导体封装装置包括电路层、安置于所述电路层上的电子组件、封装元件及第一包封物。所述封装元件安置于所述电路层上。所述封装元件包含电连接到所述电路层的至少两个电触点。所述第一包封物安置于所述电路层上。所述第一包封物包封所述电子组件及所述封装元件并且暴露所述封装元件的所述电触点。

Description

半导体封装装置及制造半导体封装装置的方法
相关申请案的交叉参考
本申请案主张2016年8月31日提交的第62/382,032号美国临时申请案的权益和优先权，所述申请案的内容以全文引用的方式并入本文中。
技术领域
本公开大体上涉及一种半导体封装装置及一种制造半导体封装装置的方法。本公开涉及一种包含扇出结构的半导体封装装置及一种制造半导体封装装置的方法。
背景技术
比较扇出技术可包含面向上技术或面向下技术。在面向上技术中，多个电子组件(包含有源组件及无源组件)安置于载体上并且暴露电连接垫/端子/触点/电极。再分布层(RDL)形成于电子组件上并且电连接到电子组件的所暴露电连接垫/端子/触点/电极。然而，由于电子组件的厚度或高度的变化，电子组件的电连接垫/端子/触点/电极不位于基本上同一高度处，这将不利地影响RDL的形成。
发明内容
在一个方面中，根据一些实施例，半导体封装装置包括电路层、安置于所述电路层上的电子组件、封装元件及第一包封物。封装元件安置于电路层上。封装元件包含电连接到电路层的至少两个电触点。第一包封物安置于电路层上。第一包封物包封电子组件及封装元件并且暴露所述封装元件的电触点。
在另一方面中，根据一些实施例，半导体封装装置包括电路层、安置于所述电路层上的第一电子组件、封装元件及第二包封物。封装元件安置于电路层上。封装元件包含第二电子组件及包封所述第二电子组件的第一包封物。第二包封物安置于电路层上并且包封第一电子组件及封装元件。邻近于或基本上处于第一包封物与第二包封物之间的边界的第一包封物的填料具有平面表面。边界基本上垂直于电路层的表面。
在又一方面中，根据一些实施例，制造半导体封装装置的方法包括(a)提供第一载体；(b)将电子组件及封装元件放置于所述第一载体上，所述电子组件包含电触点并且所述封装元件包含电极；(c)形成第一包封物以覆盖所述电子组件及所述封装元件并且暴露所述电触点及所述电极；及(d)将电路层形成于所述第一包封物上并且电连接到所述电触点及所述电极。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本公开的各方面。应注意，各种特征可能未按比例绘制，且附图中所描绘特征的尺寸可能出于论述的清楚起见而任意增大或减小。
图1A说明根据本公开的一些实施例的半导体封装装置的截面图。
图1B说明根据本公开的一些实施例的封装元件的截面图。
图1C说明根据本公开的一些实施例的封装元件的截面图。
图1D说明根据本公开的一些实施例的封装元件的截面图。
图1E说明根据本公开的一些实施例的封装元件的放大图。
图2A、图2B、图2C及图2D说明根据本公开的一些实施例的制造封装元件的方法。
图3A及图3B说明根据本公开的一些实施例的封装元件的放大图。
图4A、图4B、图4C、图4D及图4E说明根据本公开的一些实施例的制造半导体封装装置的方法。
在整个图式及具体实施方式中使用共同参考数字来指示相同或类似元件。根据以下结合附图作出的详细描述将容易地理解本公开。
具体实施方式
图1A说明根据本公开的第一方面的半导体封装装置1的一些实施例的截面图。半导体封装装置1包含电路层10、电子组件11、封装元件12及封装体(或包封物)13。
电路层10包含互连层(例如，再分布层，RDL)10r及介电层10d。互连层10r的一部分由介电层10d覆盖或包封，而互连层10r的另一部分从介电层10d暴露以提供用于电子组件11及封装元件12的电连接。在一些实施例中，介电层10d可包含模制化合物、预浸复合纤维(例如，预浸料)、掺杂硼磷的硅玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅玻璃(USG)、其中两者或多于两者的任何组合等等。模制化合物的实例可包含(但不限于)包含分散在其中的填料的环氧树脂。预浸料的实例可包含(但不限于)通过堆叠或层压多个预浸材料/片材而形成的多层结构。在一些实施例中，取决于设计规范可存在任何数目的互连层10r。在一些实施例中，电路层10的厚度约为20微米(μm)。
电子组件11安置于电路层10上。电子组件11可为有源组件，例如，集成电路(IC)芯片或裸片。电子组件11可为无源组件，例如，电容器、电阻器或电感器。电子组件11可电连接到另一电子组件、封装元件12及/或电路层10(例如，电连接到从介电层10d暴露的互连层10r)中的一或多者，并且可借助于倒装芯片或引线键合技术获得电连接。
封装元件12安置于电路层10上并且电连接到从介电层10d暴露的互连层10r的部分。在一些实施例中，封装元件12的上表面121与电子组件11的后表面(或后侧)111基本上共面。
图1B说明根据本公开的一些实施例的封装元件12的截面图。如图1B中所展示，封装元件12包含电子组件12a及覆盖或包封电子组件12a的封装体(或包封物)12b。
电子组件12a可为无源组件，例如，电容器、电阻器或电感器。在一些实施例中，电子组件12a是包含两个电极12a1及12a2的双端口元件。电极12a1及12a2布置在基本上平行于电路层10的上表面的平面处。在一些实施例中，电气组件12a可为有源组件，例如，晶体管、IC芯片或包含多于两个电极的裸片。电极12a1及12a2分别通过焊料层12d电连接到电触点12a3及12a4。电触点12a3及12a4从封装体12b暴露并且电连接到电路层10的互连层10r(例如，导电垫)。电触点12a3及12a4布置在基本上平行于电路层10的上表面的平面处。在一些实施例中，电触点12a3及12a4包含铜，或另一金属或金属合金。在一些实施例中，封装体12b包含环氧树脂(包含填料)、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、具有分散在其中的硅酮的材料，或其中两者或多于两者的组合。
图1C说明根据本公开的一些实施例的封装元件12'的截面图。封装元件12'类似于图1B中所展示的封装元件12，不同之处在于，封装元件12'不包含焊料层12d及电触点12a3、12a4。举例来说，电极12a1及12a2从封装体12b暴露并且电连接到电路层10的互连层10r。电极12a1及12a2布置在基本上平行于电路层10的上表面的平面处。
图1D说明根据本公开的一些实施例的封装元件12”的截面图。封装元件12”类似于图1B中所展示的封装元件12，不同之处在于，封装元件12”进一步包含电触点12a3、12a4与电路层10的互连层10r之间的钝化层12p。在一些实施例中，钝化层12p包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧、二氧化铪，或另一金属或非金属氧化物或氮化物。
如图1B、图1C及图1D中所展示，由于电子组件12a的厚度小于电子组件11的厚度，因此封装体12b用于覆盖或包封电子组件12a，使得封装元件12、12'或12”的总厚度与电子组件11的厚度基本上相同。举例来说，封装元件12的上表面121(参看图1A)与电子组件11的后表面(或后侧)111基本上共面(或对准)。
参考图1A，封装体13安置于电路层10上，以覆盖或包封电子组件11及封装元件12。在一些实施例中，封装元件12的上表面121及电子组件11的后表面111从封装体13暴露。在一些实施例中，封装体13的上表面131与封装元件12的上表面121及电子组件11的后表面111基本上共面。在一些实施例中，封装体13包含环氧树脂(包含填料)、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、具有分散在其中的硅酮的材料，或其中两者或多于两者的组合。
在一些实施例中，封装体13及封装体12b包含相同材料。或者，封装体13及封装体12b包含不同材料。在一些实施例中，如果封装体12b及封装体13由不同材料构成，那么可减少翘曲问题。举例来说，封装体12b可具有约120℃的玻璃化转变温度(Tg)、在约13℃-1至约58℃-1的范围内的热膨胀系数(CTE)及约6GPa的挠曲模数，而封装体13可具有约120℃的Tg、在约7℃-1至约28℃-1的范围内的CTE及约30GPa的挠曲模数。
图1E是根据本公开的一些实施例的展示封装元件12与封装体13之间的边界的半导体封装装置1的一部分的放大图。
封装体13包含多个填料13f并且封装体12b包含多个填料12f。如图1E中所展示，由于封装体12b及封装体13不在单个过程中形成，因此填料13f及填料12f在封装元件12与封装体13之间的边界处不连续。邻近于或基本上处于边界处的填料12f的一部分被切断。在一些实施例中，封装元件12与封装体13之间的边界基本上垂直于电路层10的上表面。
图2A、图2B、图2C及图2D是根据本公开的制造半导体封装装置的方法的一些实施例的在各个制造阶段处的半导体结构的截面图。已简化各图以更清楚地呈现本公开的各方面。
参考图2A，提供载体29，其中粘合剂29a(例如，条带)安置于所述载体上。在一些实施例中，载体29是金属板、玻璃衬底或硅衬底。多个电触点22a3及22a4通过粘合剂29a附接到载体29，这可有助于促进连续过程。焊料22d随后安置于电触点22a3及22a4上。
参考图2B，电子组件22a安置于电触点22a3、22a4上并且通过焊料22d附接到电触点22a3、22a4。电子组件22a可为无源组件，例如，电容器、电阻器或电感器。在一些实施例中，电子组件22a是包含两个电极22a1及22a2的双端口元件。在其它实施例中，电气组件22a可为有源组件，例如，晶体管、IC芯片或包含多于两个电极的裸片。
参考图2C，封装体(或包封物)22b形成于载体29上，以覆盖电子组件22a、焊料22d及电触点22a3、22a4。在一些实施例中，封装体22b包含环氧树脂(包含填料)、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、具有分散在其中的硅酮的材料，或其中两者或多于两者的组合。在一些实施例中，封装体22b可通过例如传递模塑或压缩成型等模制技术形成。
参考图2D，从封装体22b移除载体29及粘合剂29a以暴露电触点22a3及22a4。随后，可执行单体化以分离出个别封装元件22。也就是说，通过封装体22b执行单体化。可(例如)通过使用划片机、激光器或其它适当的切割技术执行单体化。在一些实施例中，封装元件22与图1B中所展示的封装元件12相同或相似。
图3A说明根据本公开的一些实施例的在单体化之前封装体22b中的填料22f并且图3B说明在单体化之后封装体22b中的填料22f'。如图3A及图3B中所展示，邻近于切割线的填料22f'的一部分被切断。举例来说，填料22f'的截面表面是平面的或基本上平面的，并且与切割线基本上共面。
图4A、图4B、图4C、图4D及图4E是根据本公开的制造半导体封装装置的方法的一些实施例的在各个制造阶段处的半导体结构的截面图。已简化各图以更清楚地呈现本公开的各方面。
参考图4A，提供载体49，其中粘合剂49a(例如，条带)安置于所述载体上。在一些实施例中，载体49是金属板、玻璃衬底或硅衬底。电子组件41及封装元件42通过粘合剂49a附接到载体49。电气组件41中的至少一者可为有源组件，例如，IC芯片或裸片。电气组件41中的至少一者可为无源组件，例如，电容器、电阻器或电感器。在一些实施例中，封装元件42与图1B中所展示的封装元件12相同或相似。或者，封装元件42可为图1C或图1D中所展示的封装元件12'或12”。在一些实施例中，封装元件42的电触点42a3及42a4与电子组件41的电触点41c基本上共面(或对准)。
参考图4B，封装体(或包封物)43形成于载体49上，以覆盖电子组件41及封装元件42。在一些实施例中，封装体43包含环氧树脂(包含填料)、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或酚类材料、具有分散在其中的硅酮的材料，或其中两者或多于两者的组合。在一些实施例中，封装体43可通过例如传递模塑或压缩成型等模制技术形成。在一些实施例中，封装体43及封装元件42的封装体包含相同材料。或者，封装体43及封装元件42的封装体包含不同材料。
参考图4C，移除封装体43的一部分以暴露电子组件41的电触点41c及封装元件42的电触点42a3及42a4。在一些实施例中，可通过磨削、蚀刻或其它合适的过程移除封装体43的所述部分。在一些实施例中，电触点42a3及42a4可用作缓冲层。
参考图4D，从封装体43移除载体49及粘合剂49a，以暴露每个电子组件41的后表面411及封装元件42的表面421。
电路层40随后形成于封装体43上并且电连接到电子组件41的电触点41c及封装元件42的电触点42a3及42a4。电路层10包含一或多个互连层(例如，RDL)40r及覆盖或封装互连层40r的一或多个介电层40d。在一些实施例中，取决于设计规范，可存在任何数目的互连层40r及介电层40d。在一些实施例中，电路层40可通过以下操作形成：(i)在封装体43上形成第一介电层；(ii)在第一介电层中形成多个开口以暴露电子组件41的电触点41c及封装元件42的电触点42a3及42a4；(iii)在第一介电层上形成第一互连层并且延伸到开口中以与电子组件41的导电触点41c及封装元件42的电触点42a3及42a4电接触；(iv)在第一互连层上形成第二介电层；(v)在第二介电层中形成多个开口以暴露第一互连层的一部分；及(vi)在第二介电层上形成导电层46u(例如，凸块下金属化(UBM)层)并且延伸到开口中以与第一互连层的暴露部分电接触。
参考图4E，电触点46(例如，受控塌陷芯片连接(C4)垫)形成或安置于导电层46u上以形成如图1A中所展示的半导体封装装置1。在一些实施例中，保护层(未展示)可形成于电子组件41的后表面411及封装元件42的表面421上。
如图4A至图4D中所展示，电子组件41的后表面411附接到载体49并且形成封装体43。在移除封装体43的一部分以暴露电子组件41的电触点41c及封装元件42的电触点42a3及42a4之后，形成电路层40以电连接到电子组件41的电触点41c及封装元件42的电触点42a3及42a4。此过程称为“面向上”过程。
在一些实施例中，具有小于电子组件41的厚度的电子组件可直接安置于载体49上。然而，由于电子组件的不同厚度或高度，电子组件的电连接垫/端子/触点/电极不位于基本上同一高度处。因此，在用于移除如图4C中所展示的封装体43的一部分的操作之后，具有更大厚度的电子组件41的电触点41c从封装体43暴露，而具有较小厚度的电子组件的电触点保持由封装体43覆盖。因此，在用于形成如图4D中所展示的电路层40的操作期间，电路层40的互连层或RDL不连接到具有较小厚度的电子组件，这将不利地影响电子组件的性能。
如在本公开的图4A、图4B、图4C、图4D及图4E中所展示，由于具有较小厚度的电子组件通过封装体包封以形成封装元件(例如，封装元件42或图1B、图1C及图1D中所展示的封装元件12、12'及12”)，因此电触点42a3及42a4与电子组件41的电触点41c基本上共面(或对准)。由于相对较薄的电子组件的减小高度通过封装体补偿，因此可形成电路层40，以便电连接到较薄电子组件及较厚电子组件41两者。
如本文中所使用，术语“大致”、“基本上”、“实质”和“约”用于描述及解释小的变化。当与事件或情形结合使用时，所述术语可指代其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差值小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“基本上”或“约”相同。举例来说，“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
如果两个表面之间的位移不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为这两个表面是共面的或基本上共面。如果表面的最高点与最低点之间的差值不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为表面是平面的或基本上平面。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”及“电导率”指代传递电流的能力。导电材料通常指示展现对于电流流动的极少或零对抗的材料。电导率的一个量度为西门子每米(S/m)。通常，导电材料为电导率大于约104S/m(例如，至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度变化。除非另外指定，否则材料的电导率是在室温下测量。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”及“所述(the)”包含复数个参考物。在一些实施例的描述中，提供于另一组件“上”或“上面”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
虽然已参考本公开的特定实施例描述及说明本公开，但这些描述及说明并不限制本公开。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内替代等效组件而不脱离如由所附权利要求书定义的本公开的真实精神及范围。所述说明可能未必按比例绘制。归因于制造过程及公差，本公开中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本公开的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改，以使具体情况、材料、物质组成、方法或工艺适应于本公开的目标、精神及范围。所有此类修改既定在所附权利要求书的范围内。虽然本文公开的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组并非本发明的限制。

Claims (23)

1.一种半导体封装装置，其包括：
电路层；
安置于所述电路层上的电子组件；
安置于所述电路层上的封装元件，所述封装元件包含电连接到所述电路层的至少两个电触点；及
安置于所述电路层上的第一包封物，所述第一包封物包封所述电子组件及所述封装元件并且暴露所述封装元件的所述电触点。
2.根据权利要求1所述的半导体封装装置，其中所述封装元件包含无源组件及第二包封物，并且所述电触点从所述第二包封物暴露。
3.根据权利要求2所述的半导体封装装置，其中
所述无源组件包含电连接到所述电触点的两个电极；及
所述两个电极布置在一平面处，并且所述平面基本上平行于所述电路层的表面。
4.根据权利要求3所述的半导体封装装置，其中所述封装元件包含焊料层，并且所述电极通过所述焊料层连接到所述电触点。
5.根据权利要求2所述的半导体封装装置，其中所述电触点包含所述无源组件的两个电极。
6.根据权利要求2所述的半导体封装装置，其中所述第一包封物及所述第二包封物包含不同材料。
7.根据权利要求2所述的半导体封装装置，其中
所述第二包封物包含多个填料；
邻近于所述第一包封物与所述第二包封物之间的边界的所述填料中的至少一者具有平面表面；及
所述边界基本上垂直于所述电路层的表面。
8.根据权利要求1所述的半导体封装装置，其中
所述第一包封物具有面对所述电路层的第一表面；及
所述第一包封物的所述第一表面与所述电触点的暴露表面基本上共面。
9.根据权利要求1所述的半导体封装装置，其中
所述第一包封物具有背对所述电路层的第二表面；及
所述第一包封物的所述第二表面与所述电子组件的后表面基本上共面。
10.根据权利要求1所述的半导体封装装置，其中所述电路层包含再分布层及介电层。
11.根据权利要求1所述的半导体封装装置，其中所述封装元件包含有源组件及第二包封物，并且所述电触点从所述第二包封物暴露。
12.一种半导体封装装置，其包括：
电路层；
安置于所述电路层上的第一电子组件；
安置于所述电路层上的封装元件，所述封装元件包含第二电子组件并且第一包封物包封所述第二电子组件；及
第二包封物，其安置于所述电路层上并且包封所述第一电子组件及所述封装元件，
其中邻近于所述第一包封物与所述第二包封物之间的边界的所述第一包封物的填料具有平面表面，并且所述边界基本上垂直于所述电路层的表面。
13.根据权利要求12所述的半导体封装装置，其中
所述第二电子组件包含从所述第一包封物暴露的两个电极；及
所述电极布置在一平面处，并且所述平面基本上平行于所述电路层的表面。
14.根据权利要求12所述的半导体封装装置，其中
所述封装元件包含电触点及焊料：
所述第二电子组件包含通过所述焊料连接到所述电触点的两个电极；
所述电触点从所述第一包封物暴露。
15.根据权利要求12所述的半导体封装装置，其中所述第一包封物及所述第二包封物由不同材料构成。
16.根据权利要求12所述的半导体封装装置，其中
所述第二包封物具有背对所述电路层的第一表面；及
所述第二包封物的所述第一表面与所述第一电子组件的后表面基本上共面。
17.根据权利要求12所述的半导体封装装置，其中所述电路层包括再分布层及介电层。
18.一种制造半导体封装装置的方法，所述方法包括：
(a)提供第一载体；
(b)将电子组件及封装元件放置于所述第一载体上，所述电子组件包含电触点并且所述封装元件包含电极；
(c)形成第一包封物以覆盖所述电子组件及所述封装元件并且暴露所述电触点及所述电极；及
(d)在所述第一包封物上形成电路层并且电连接到所述电触点及所述电极。
19.根据权利要求18所述的方法，其中操作(c)进一步包括：
在所述第一载体上形成所述第一包封物以覆盖所述电子组件及所述封装元件；及
移除所述第一包封物的一部分以暴露所述电触点及所述电极。
20.根据权利要求19所述的方法，其中通过磨削移除所述第一包封物的所述部分。
21.根据权利要求19所述的方法，其进一步包括：
提供第二载体；
将多个第二电子组件放置于所述第二载体上，所述第二电子组件中的每一者包含所述第二载体上的电极；
在所述第二载体上形成第二包封物以覆盖所述第二电子组件；
移除所述第二载体以暴露所述第二电子组件中的每一者的所述电极；及
单体化所述第二包封物以形成多个间隔开的封装元件。
22.根据权利要求21所述的方法，其中所述第二电子组件是有源组件或无源组件。
23.根据权利要求18所述的方法，其中操作(d)进一步包括：
在所述第一包封物上形成介电层以覆盖所述电触点及所述电极；
在所述介电层中形成多个开口以暴露所述电触点及所述电极；及
在所述介电层上及在所述开口内形成导电层以电连接到所述电触点及所述电极。
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