CN204696098U - 多芯片模块及半导体封装件 - Google Patents

多芯片模块及半导体封装件 Download PDF

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Publication number
CN204696098U
CN204696098U CN201520248806.2U CN201520248806U CN204696098U CN 204696098 U CN204696098 U CN 204696098U CN 201520248806 U CN201520248806 U CN 201520248806U CN 204696098 U CN204696098 U CN 204696098U
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China
Prior art keywords
semiconductor package
cross tie
substrate
package part
tie part
Prior art date
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Expired - Fee Related
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CN201520248806.2U
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English (en)
Inventor
罗立德
雷佐尔·拉赫曼·卡恩
胡坤忠
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Broadcom Corp
Zyray Wireless Inc
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Zyray Wireless Inc
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Publication of CN204696098U publication Critical patent/CN204696098U/zh
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Abstract

本文提供了一种多芯片模块及半导体封装件，该多芯片模块包括：至少两个半导体封装件，所述至少两个半导体封装件中的每个包括：基板，具有第一表面和与所述第一表面相对的第二表面；至少一个半导体管芯，耦接至所述基板的所述第一表面；以及第一封装材料，封装所述至少一个管芯和所述基板的所述第一表面；以及第二封装材料，至少部分封装所述至少两个半导体封装件。

Description

多芯片模块及半导体封装件
相关申请的交叉引用
本申请要求于2014年4月22日提交的美国临时申请第61/982,442号和于2014年4月28日提交的美国专利申请第14/263,718号的优先权，其全部内容通过引用并入本文。
技术领域
本文描述的主题涉及用于半导体封装件的重构技术。
背景技术
对于移动无线设备，期望这些设备执行的功能的数量随着时间继续增加，并且被开发以在这些设备中实现来执行这些功能的半导体管芯或者芯片的数目也因此增加。因此，将多个管芯或者芯片结合到单个封装件里的能力变得更加重要，因为这提供了关于X、Y和Z尺寸的较小形状因子的益处和降低的成本。
实用新型内容
描述了用于半导体封装件的重构技术的方法、系统和装置，该半导体封装件的重构技术基本上如附图所示和/或在本文中结合至少一个附图来描述，如在权利要求中更完整提出。
本公开提供了一种多芯片模块，包括：至少两个半导体封装件，所述至少两个半导体封装件中的每个包括：基板，具有第一表面和与所述第一表面相对的第二表面；至少一个半导体管芯，耦接至所述基板的所述第一表面；以及第一封装材料，封装所述至少一个管芯和所述基板的所述第一表面；以及第二封装材料，至少部分封装所述至少两个半导体封装件。
在上述多芯片模块中，所述至少两个半导体封装件中的每个进一步包括：多个互连件，耦接至所述基板的所述第二表面，所述多个互连件通过所述第二封装材料被部分封装。
在上述多芯片模块中，所述多个互连件包括多个焊球。
在上述多芯片模块中，所述至少两个半导体封装件中的第一半导体封装件侧向邻近于所述至少两个半导体封装件中的第二半导体封装件，使得所述第一半导体封装件的所述基板基本上与所述第二半导体封装件的所述基板共面。
在上述多芯片模块中，所述至少两个半导体封装件中的至少一个包括多个管芯。
在上述多芯片模块中，所述至少两个半导体封装件中的至少一个包括耦接至所述至少两个半导体封装件中的所述至少一个的至少相应的第一表面的屏蔽层。
上述多芯片模块进一步包括：互连件，耦接所述至少两个半导体封装件，所述互连件被所述第二封装材料封装。
在上述多芯片模块中，所述互连件包括接合线。
本公开提供了一种方法，包括：放置第一半导体封装件和第二半导体封装件，使得所述第一半导体封装件侧向邻近于所述第二半导体封装件，所述第一半导体封装件和所述第二半导体封装件中的每个具有第一表面和与所述第一表面相对的第二表面，所述第二表面中的每个具有多个互连件；以及在封装材料中至少部分封装所述第一半导体封装件和所述第二半导体封装件。
在上述方法中，所述放置包括：将粘合材料层施加至所述第一半导体封装件的所述第一表面和所述第二半导体封装件的所述第一表面。
在上述方法中，所述至少部分封装包括：在所述第一半导体封装件和所述第二半导体封装件的所述多个互连件上施加至少一膜层；在所述至少一膜层与所述第一半导体封装件和所述第二半导体封装件的所述第二表面之间施加封装材料；以及去除所述至少一膜层，所述第一半导体封装件和所述第二半导体封装件的所述多个互连件通过所述封装材料而被至少部分暴露。
在上述方法中，所述多个互连件包括多个焊球。
在上述方法中，所述第一半导体封装件或者所述第二半导体封装件中的至少一个包括在所述第一半导体封装件或者所述第二半导体封装件中的所述至少一个的所述第一表面上基本上包围至少一个集成电路管芯的屏蔽层。
上述方法进一步包括：利用互连件电气并机械地耦接所述第一半导体封装件与所述第二半导体封装件；并且所述至少部分封装包括利用所述第二封装材料封装所述互连件。
在上述方法中，所述电气并机械地耦接包括：利用至少一个接合线将所述第一半导体封装件与所述第二半导体封装件耦接在一起。
本公开提供了一种半导体封装件，包括：基板，具有第一表面和与所述第一表面相对的第二表面；一个或多个第一互连件，耦接至所述基板的所述第一表面；一个或多个第二互连件，耦接至所述基板的所述第一表面；以及封装材料，完全封装所述一个或多个第一互连件和所述基板的所述第一表面，并且部分封装所述一个或多个第二互连件，使得所述一个或多个第二互连件通过所述封装材料被部分暴露。
在上述半导体封装件中，所述一个或多个第一互连件和所述一个或多个第二互连件是焊球。
上述半导体封装件进一步包括：集成电路管芯，被安装至所述基板的所述第一表面。
在上述半导体封装件中，所述一个或多个第一互连件经由在所述基板的所述第一表面上形成的绝缘层中的第一组开口耦接至所述基板的所述第一表面，并且所述一个或多个第二互连件经由形成在所述绝缘层中的第二组开口耦接至所述基板的所述第一表面，其中，所述第一组开口具有第一宽度并且所述第二组开口具有小于所述第一宽度的第二宽度。
在上述半导体封装件中，小于所述第一宽度的所述第二宽度使所述一个或多个第二互连件与所述基板的所述第一表面的间隔距离大于所述一个或多个第一互连件与所述基板的所述第一表面的间隔距离。
附图说明
并入本文中并组成说明书的一部分的附图示出了实施方式，并与说明书一起进一步用来解释实施方式的原理，并使得相关领域的技术人员能够实施和使用实施方式。
图1示出了根据本文描述的实施方式的重构的多芯片模块的截面图。
图2示出了根据本文描述的实施方式的提供用于形成重构的多芯片模块的示例步骤的流程图。
图3A示出了根据本文描述的实施方式的被放置为侧向邻近于彼此的三个半导体封装件的截面图。
图3B示出了根据本文描述的实施方式的三个半导体封装件在被附接至粘合材料层之后的截面图。
图3C示出了根据本文描述的实施方式的三个半导体封装件在通过一个或多个互连件耦接之后的截面图。
图3D示出了根据本文描述的实施方式的在三个半导体封装件上执行的膜辅助模制工艺的截面图。
图3E示出了根据本文描述的实施方式的重构的多芯片模块的截面图。
图3F至图3G示出了根据实施方式的可被重构的条封装件和板封装件的示例。
图3H至图3I示出了根据实施方式的可被重构的封装(encapsulated，封包)的条封装件和板封装件的示例。
图4示出了根据本文描述的实施方式的包括自对准特征的半导体封装件的截面图。
图5示出了根据本文描述的实施方式的提供用于形成包括自对准特征的半导体封装件的示例步骤的流程图。
图6A示出了根据本文描述的实施方式的基板在经由一个或多个第一开口而暴露该基板的导电层的一个或多个第一区域之后的截面图。
图6B示出了根据本文描述的实施方式的基板在经由一个或多个第二开口而暴露导电层的一个或多个第二区域之后的截面图。
图6C示出了根据本文描述的实施方式的基板在被附接至粘合材料层之后的截面图。
图6D示出了根据本文描述的实施方式的基板在导电层的一个或多个第一区域上形成一个或多个第一互连件之后的截面图。
图6E示出了根据本文描述的实施方式的在图6D中示出的基板的平面图。
图6F示出了根据本文描述的实施方式的基板在导电层的一个或多个第二区域上形成一个或多个第二互连件之后的截面图。
图6G示出了根据本文描述的实施方式的在图6F中示出的基板的平面图。
图6H示出了根据本文描述的实施方式的在基板上执行的膜辅助模制工艺的截面图。
图6I示出了根据本文描述的实施方式的基板在完成膜辅助模制工艺之后的截面图。
图6J示出了根据本文描述的实施方式的在图6I中示出的基板的平面图。
图6K示出了根据本文描述的实施方式的基板在通过封装基板的封装材料形成穿塑孔(through-mold vias)之后的截面图。
图6L示出了根据本文描述的实施方式的在图6K中示出的基板的平面图。
图6M和图6N示出了根据实施方式的可并行处理的条基板和板基板的示例。
图6O和图6P示出了根据实施方式的可并行处理的封装的条基板和板基板的示例。
现将参考附图描述实施方式。在附图中，类似的参考标号表示相同或者功能上类似的元件。另外，参考标号的最左边的数字确定参考标号第一次出现的附图。
具体实施方式
I.引言
本说明书公开多个示例性实施方式。本专利申请的范围不限于公开的实施方式，还包括公开的实施方式、以及公开的实施方式的修改的组合。
在本说明书中引用“一个实施方式”、“实施方式”、“示例实施方式”等表示所描述的实施方式可包括特定的特征、结构或特性，但是每个实施方式无需包括特定的特征、结构或特性。此外，这种短语不一定指同一实施方式。此外，当特定特征、结构或特性结合实施方式进行了说明时，应当认为这是在本领域技术人员的知识范围内结合其他实施方式(不管明确描述与否)来影响这种特征、结构或特性。
在实施方式中，提供用于半导体封装件的各种重构技术。根据实施方式，重构技术被用于将多个半导体封装件封装为单个多芯片模块。根据这种实施方式，每个半导体封装件可以在重构之前被装配和/或测试。在重构过程中，也可以使用一个或多个互连件(例如，接合线)电气并机械地连接半导体封装件。耦接至每个封装件的基板的焊球可以在重构之后部分地暴露，通过暴露使单个多芯片模块能够耦接至另一设备(例如，电路板)。
根据另一实施方式，重构技术被用于使用自对准特征将多个半导体封装件连接为层叠封装件模块。根据这种实施方式，自对准特征是包括在封装件中的位于层叠封装件模块的底部上的至少一个部分暴露的焊球。该至少一个部分暴露的焊球用作通过封装材料封装(且因此，不可视)的其他焊球的参照系。在使用至少一个部分暴露的焊料模具确定这些其他焊球的位置之后，可以在对应于其他焊球的位置上形成穿塑孔。然后可以使用这些焊球将层叠封装件模块的顶部封装件耦接至底部封装件。因此，至少一个部分暴露的焊球可以有利地用于补偿在底部封装件的重构过程中出现的任何潜在未对准。
在实施方式中，描述了多芯片模块。该多芯片模块包括至少两个半导体封装件。至少两个半导体封装件中的每个包括基板、至少一个半导体管芯及第一封装材料。对于每个封装件，基板具有第一表面和与第一表面相对的第二表面，该至少一个半导体管芯耦接至基板的第一表面，并且第一封装材料封装至少一个管芯和基板的第一表面。多芯片模块进一步包括至少部分封装至少两个半导体封装件的第二封装材料。
描述了示例性方法。该方法包括使第一半导体封装件和第二半导体封装件放置为使得第一半导体封装件侧向邻近于第二半导体封装件。第一半导体封装件和第二半导体封装件的每个具有第一表面和与第一表面相对的第二表面。每个第二表面具有多个互连件。第一半导体封装件和第二半导体封装件在封装材料中至少部分被封装。
还描述了半导体封装件。半导体封装件包括基板、一个或多个第一互连件、一个或多个第二互连件及封装材料。基板具有第一表面和与第一表面相对的第二表面。一个或多个第一互连件耦接至基板的第一表面。一个或多个第二互连件也耦接至基板的第一表面。封装材料封装一个或多个第一互连件和基板的第一表面，并且部分封装一个或多个第二互连件，使得一个或多个第二互连件部分被暴露(即，部分没有被封装材料覆盖，且因此从外部可接入半导体封装件)。
II.示例性实施方式
A.用于多芯片模块的重构技术
如上所述，除了机械地耦接在一起(例如，通过封装材料保持在一起、通过接合线或者其他导体连接等)之外，多芯片模块可以形成为包括可选择地电气耦接在一起(例如，通过接合线等)的多个半导体封装件。半导体封装件被并排地放置为侧向邻近于彼此(例如，封装件的基板基本上彼此共面)。在实施方式中，这种多芯片模块可以以各种方式配置。
例如，图1示出了根据示例性实施方式的重构的多芯片模块100的截面图。如图1中所示，多芯片模块100包括第一半导体封装件102A和第二半导体封装件102B，该第二半导体封装件102B被放置为侧向邻近于第一半导体封装件102A(即，封装件102A和封装件102B在图1中的水平面116上基本上是共面的)。根据实施方式，第一半导体封装件102A和/或第二半导体封装件102B可以包括基板和耦接至基板的一个或多个半导体管芯。根据另一实施方式，第一半导体封装件102A和/或第二半导体封装件102B可以是包括耦接至晶圆的一个或多个半导体管芯的晶圆级封装件(即，晶圆级封装件不包括封装件基板)。
可以通过封装材料封装一个或多个半导体管芯。基板可以包括一个或多个导电层、通孔、介电层等。第一半导体封装件102A和第二半导体封装件102B的每个也可以包括多个互连件108，该互连件108被用于接口连接位于其中的一个或多个半导体管芯与电路板(例如，印刷电路板)(未示出)。互连件108可以包括但不限于，焊球、引脚、导柱、表面安装技术(SMT)焊盘和/或类似物。
第一半导体封装件102A和第二半导体封装件102B可以电气并机械地经由一个或多个互连件110彼此耦接。一个或多个互连件110可以包括一个或多个接合线(也称为“丝焊”)、一个或多个无源组件(例如，一个或多个电阻器)和/或类似物。
通过至少部分封装第一半导体封装件102A、第二半导体封装件102B以及封装材料106中的一个或多个互连件110，可以使第一半导体封装件102A和第二半导体封装件102B重构在一起。例如，如图1中所示，第一半导体封装件102A和第二半导体封装件102B的上表面112A和上表面112B、底表面114A和底表面114B、侧表面、第一半导体封装件102A和第二半导体封装件102B之间的空间、以及一个或多个互连件110通过封装材料106来封装。此外，通过封装材料106使互连件108部分被封装，从而使多芯片模块100能够通过互连件108的暴露部分耦接至电路板。
根据实施方式，封装材料106可以包括与用于封装第一半导体封装件102A和第二半导体封装件102B的一个或多个半导体管芯的封装材料不同的材料。例如，封装材料106可以包括具有相对大的填充物尺寸(例如，40至50微米的填充物尺寸)和/或具有基本上标准的或者较高的α粒子放射率的低级材料，然而封装包括在第一半导体封装件102A和第二半导体封装件102B中的一个或多个半导体管芯的封装材料可以包括高级材料，诸如具有相对低的α粒子放射率的填充物尺寸(例如，填充物尺寸小于20微米和/或α粒子率低于封装材料106)的材料。
虽然图1示出了多芯片模块100包括两个半导体封装件，但应注意，在某些实施方式中，多芯片模块100可以包括任意数量的半导体封装件。根据该实施方式，半导体封装件可以以任何方式被放置为邻近于彼此。
在实施方式中，半导体封装件102A和半导体封装件102B(和另外的封装件)可以以各种方式重构为多芯片模块。例如，图2示出了流程图200，该流程图200是根据实施方式的用于形成重构的多芯片模块的过程。为了说明性的目的，以下参考图3A至图3E描述流程图200。图3A至图3E示出了根据实施方式的三个半导体封装件302A、302B和302C的截面图。应注意，不需要在所有的实施方式中执行流程图200的所有步骤。基于本文中提供的讨论，其他结构和操作的实施方式对于本技术领域的技术人员来说是显而易见的。
流程图200开始于步骤202。在步骤202中，第一半导体封装件和第二半导体封装件被放置为使得第一半导体封装件侧向邻近于第二半导体封装件。第一半导体封装件和第二半导体封装件中的每个具有第一表面和与第一表面相对的第二表面。每个第二表面具有多个互连件。
例如，图3A示出了放置为侧向邻近于彼此的三个半导体封装件302A、302B和302C的截面图。第一半导体封装件302A具有第一表面336和与第一表面336相对的第二表面338。第一半导体封装件302A可以包括一个或多个半导体管芯(例如，第一半导体管芯304和第二半导体管芯306)、基板308和耦接至第二表面338的互连件阵列326，一个或多个半导体管芯可以堆叠(如在图3A中)或者放置为邻近于彼此。可以使用粘合材料层310将第一半导体管芯304的非活性表面装配至第二半导体管芯306的非活性表面。基板308可以包括芯层350(例如，介电材料层)，芯层350具有第一表面312和与第一表面312相对的第二表面314。基板308还可以包括形成在第一表面312上的第一导电层320和形成在第二表面314上的第二导电层322。基板308可以进一步包括在第一表面312和第一导电层320上形成的第一绝缘层316和在第二表面314和第二导电层322上形成的第二绝缘层318。第一绝缘层316和第二绝缘层318的示例可以包括但不限于，钝化层或者焊剂遮盖层。在实施方式中，可以在芯层350上进一步堆叠导电层和/或电气绝缘层。
多个接合线330可以将第一半导体管芯304的活性表面上的端子(未示出)耦接至第一导电层320(例如，至传导性的迹线、焊盘和/或其他特征)。第二半导体管芯306可以具有将第二半导体管芯306的活性表面上的端子(未示出)耦接至第一导电层320的多个互连件328。互连件328的示例可以包括但不限于，焊球、引脚、SMT焊盘和/或类似物。
互连件326可以用于将第一半导体封装件302A装配至电路板(未示出)(例如，通过回流焊接等)。互连件326可以是但不限于，焊球、引脚、导柱、表面安装技术(SMT)焊盘和/或类似物。如图3A中所示，互连件326耦接至基板308的第二导电层322。互连件326通过包括在芯层350中的通孔324穿过基板308电耦接至第一导电层320。接合线330和互连件328因此耦接至互连件326，从而使第一半导体管芯304和第二半导体管芯306的信号能够电耦接至互连件326。
封装材料352覆盖第一半导体管芯304、第二半导体管芯306、接合线330、互连件328及第一绝缘层316。封装材料352可以是相关领域的技术人员已知的任何合适类型的封装材料(高级、中级或低级)。在一个实施方式中，封装材料352可以包括高级材料(例如，具有小于20微米的最大填充物尺寸和/或具有低α粒子发射率的材料)。
第二半导体封装件302B和第三半导体封装件302C可以以与第一半导体封装件302A类似的方式配置。因而，为了便于说明，不分开详细描述封装件302B和封装件302C的结构。应注意，第一半导体封装件302A、第二半导体封装件302B及第三半导体封装件302C的每个可以包括具有变化的尺寸和/或功能的任意数量的半导体管芯。另外，第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C可以各自包括不同的特征。例如，如图3A中所示，第三半导体封装件302C包括电磁干扰(EMI)屏蔽层358。EMI屏蔽层358可以包括金属(例如，铜、镍、金、银、铂、钴、钛、铬、锆、钼、钌、铪、钨、铼和/或类似物)。在封装件302C的示例中，EMI屏蔽层358包围封装件基板的顶表面上的一对堆叠的管芯。以这种方式，EMI屏蔽层358执行关于在操作过程中从一个或两个管芯中发出的辐射和/或关于在操作过程中保护一个或多个管芯免受在封装件302C外部的源产生的EMI的EMI屏蔽。
如上所述，半导体封装件302A、半导体封装件302B和半导体封装件302C放置为侧向邻近于彼此。例如，半导体封装件302A、半导体封装件302B和半导体封装件302C可以放置为使得第一半导体封装件302A的基板308基本上与第二半导体封装件302B的基板共面，并且使得第二半导体封装件302B的基板基本上与第三半导体封装件302C的基板共面。
根据实施方式，步骤202还可以包括将第一半导体封装件的第一表面和第二半导体封装件的第一表面附接至粘合材料层。例如，如图3B中所示，第一半导体封装件302A的第一表面336、第二半导体封装件302B的第一表面354和第三半导体封装件302C的第一表面356附接至粘合材料层340。粘合材料层340可以是具有粘合材料(树脂、粘胶剂等，能够暂时施加(apply，涂覆)粘合材料层340，并且随后从封装件去除粘合材料层340)在其表面上的片或者带(例如，纸张、塑料等)。
根据另一实施方式，步骤202还可以包括将其他半导体封装件放置为紧邻半导体封装件302A、半导体封装件302B和半导体封装件302C以形成条半导体封装件(例如，单个纵列)或者板半导体封装件(例如，多维阵列)。这些其他半导体封装件可以用于形成其他一个或多个多芯片模块。
例如，图3F至图3G示出了根据实施方式的可以包括半导体封装件组的条和板的示例。具体地，图3F示出了在粘合材料层340上布置为条格式的半导体封装件的第一组370A、半导体封装件的第二组370B、半导体封装件的第三组370C和半导体封装件的第四组370D。第一组370A、第二组370B、第三组370C和第四组370D的每个可以包括多个半导体封装件(例如，第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C，如图3A至图3B所示)。图3G示出了在粘合材料层340上布置为板格式的第一组半导体封装件370A、第二组半导体封装件370B、第三组半导体封装件370C、第四组半导体封装件370D、第五组半导体封装件370E和第六组半导体封装件370F。如图3G中所示，第一组370A、第二组370B、第三组370C、第四组370D、第五组370E和第六组370F可以布置成基本上统一的横行和/或纵列，但是实施方式的范围在这方面不受限制。
根据另一实施方式，第一半导体封装件和第二半导体封装件可以通过一个或多个互连件机械并电气地耦接。例如，如图3C中所示，第一半导体封装件302A和第二半导体封装件302B通过互连件342机械并电气地耦接，并且第二半导体封装件302B和第三半导体封装件302C通过互连件344机械并电气地耦接。互连件342和互连件344可以使来自位于第一半导体封装件302A的半导体管芯的信号能够在位于第二半导体封装件302B和/或第三半导体封装件302C的半导体管芯之间被传送。例如，互连件342和互连件344的每个可以耦接至各自的半导体封装件(例如，半导体封装件302A、半导体封装件302B和半导体封装件302C)的各自的第一导电层(例如，第一导电层320)。例如，互连件342和互连件344中的每个可以耦接至第三导电层(例如，第三导电层334)，该第三导电层包括在各个半导体封装件的第二绝缘层(例如，第二绝缘层318)中。第三导电层通过通孔(例如，通孔332)耦接至第一导电层。
互连件342和互连件344可以包括一个或多个接合线、一个或多个无源组件(例如，一个或多个电阻器)和/或类似物。互连件342和互连件344可以以任何方式(包括通过拾取和放置装置、引线接合装置等)来施加。虽然互连件342和344在图3C中示出为各自耦接第一封装件至第二封装件，但是可以存在任意数量的互连件以耦接具体的封装件至一个或多个其他封装件，任意数量的互连件包括几个、几十个、数百个、乃至数千个的许多互连件。
回到图2，在步骤204，第一半导体封装件和第二半导体封装件至少部分在封装材料中被封装。根据实施方式，第一半导体封装件和第二半导体封装件可以使用膜辅助模制工艺、插入模制工艺(例如，橡胶插入模制工艺)和/或类似物至少部分地在封装材料中被封装。例如，图3D示出了膜辅助模制工艺，其中，一层或多层膜346可以在第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C的互连件326上被施加。例如，膜346可以是与互连件326一致的和/或可以在压力或者压缩下保持邻近于互连件326的弹性材料的塑料或者其他层。此后，在膜346与粘合材料层340之间的第一半导体封装件302A、第二半导体封装件302B、和第三半导体封装件302C的一侧(如通过箭头364示出的)施加封装材料348。封装材料348可以是如相关领域的技术人员已知的任何合适的封装材料。在实施方式中，封装材料348可以包括低级材料(例如，具有40微米至50微米的最大填充物尺寸和/或具有比较高的α粒子放射率(例如，大于0.02α粒子/小时·cm2)的材料)。
在注入并对封装材料348进行固化之后，将一层或多层膜346从互连件326去除和/或将粘合材料层340从第一半导体封装件302A的第一表面336、第二半导体封装件302B的第一表面354和第三半导体封装件302C的第一表面356去除，从而形成包括部分暴露的互连件326的多芯片模块。
根据其中其他半导体封装件放置为紧邻条格式或者板格式的半导体封装件302A、半导体封装件302B和半导体封装件302C的实施方式(例如，如图3F至图3G所示)，步骤204可以包括在封装材料348中至少部分地封装条半导体封装件或者板半导体封装件。
例如，图3H至图3I示出了根据实施方式的可以包括半导体封装件组的封装的条和板的示例。具体地，图3H示出了在封装材料348中封装第一组半导体封装件370A、第二组半导体封装件370B、第三组半导体封装件370C和第四组半导体封装件370D的封装的条380。图3I示出了在封装材料348中封装第一组半导体封装件370A、第二组半导体封装件370B、第三组半导体封装件370C、第四组半导体封装件370D、第五组半导体封装件370E和第六组半导体封装件370F的封装板382。如图3H至图3I的每个所示，包括在第一组370A、第二组370B、第三组370C、第四组370D、第五组370E和/或第六组370F的每个中的半导体封装件(例如，如图3E中所示的第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C)的互连件326部分被暴露，使得互连件326从封装材料348突出。
返回至图2，在步骤206中，封装的第一半导体封装件和第二半导体封装件与条或者板分离(singulate，单一化)以形成多芯片模块。例如，根据其中其他半导体封装件以条格式或者板格式(例如，如图3F至图3G所示)放置为紧邻半导体封装件302A、半导体封装件302B和半导体封装件302C并且随后通过封装材料348封装(如以上关于步骤204的描述，并且如图3H至图3I中示出)的实施方式，流程图200可以选择性地包括将半导体封装件组(例如，第一组370A、第二组370B、第三组370C、第四组370D、第五组370E和/或第六组370F，如图3H至图3I所示)的条或者板分离为不同的多芯片模块的步骤206。半导体封装件可以以相关领域的技术人员已知的任何合适的方式被分离，以物理分开半导体封装件组与其他半导体封装件组。例如，半导体封装件可以通过锯、刨槽机、激光器或者根据任何其他分离技术来分离。
图3E示出了产生的多芯片模块300。如图3E中所示，通过封装材料348部分封装第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C的每个。具体地，通过封装材料348封装邻近于第一半导体封装件302A、第二半导体封装件302B和第三半导体封装件302C的每个的空间，通过封装材料348封装第一半导体封装件302A的第二表面338、第二半导体封装件302B的第二表面360和第三半导体封装件302C的第三表面362，并且通过封装材料348封装互连件342和互连件344。第一半导体封装件302A的第一表面336、第二半导体封装件302B的第一表面354和第三半导体封装件302C的第一表面356可以是左侧暴露的。虽然实施方式的范围在这方面不受限制。例如，根据某些实施方式，也可以通过封装材料348封装第一半导体封装件302A的第一表面336、第二半导体封装件302B的第一表面354和第三半导体封装件302C的第一表面356(如图1中所示)。互连件326部分被暴露，使得互连件326从封装材料348突出。互连件326由于在膜辅助模制过程中一层或多层膜346的施加而部分地从左侧暴露，如图3D中所示。
因此，可以使用互连件326的暴露部分将多芯片模块300装配至电路板(例如，PCB)。如上所述，在实施方式中，相对于封装一个或多个封装件302A、封装件302B和/或封装件302C的封装材料352的等级(例如，高级)，将多芯片模块300保持在一起的封装材料348可以是低级材料，以节省多芯片模块成本。
B.用于使用自对准特征的层叠封装件模块的重构技术
如上所述，可以形成包括具有两组互连件的半导体封装件的半导体封装件。封装件的封装材料完全将一个或多个第一互连件封装在封装件的基板表面上，并且部分将一个或多个第二互连件封装在基板表面上，使得一个或多个第二互连件被部分暴露(即，部分没有被封装材料覆盖，且因此可从外部接入半导体封装件)。在实施方式中可以以各种方式配置这种封装件。
例如，图4示出了根据示例性实施方式的包括一种或多种自对准特征的半导体封装件400的截面图。如图4中所示，半导体封装件400包括基板402、一个或多个半导体管芯(例如，半导体管芯404)、多个第一互连件408和一个或多个第二互连件410。基板402具有第一表面412和与第一表面412相对的第二表面414。基板402可以包括一个或多个导电层、通孔、绝缘层等。第一互连件408和一个或多个第二互连件410可以耦接至基板402的第一表面412。半导体管芯404可以装配至第一表面412(例如，通过使用粘合材料(图4中未示出))。封装材料406可以封装一个或多个半导体管芯404、第一互连件408、基板402的第一表面412和邻近于基板402的空间。根据实施方式，封装材料406还可以封装第二表面414。封装材料406部分封装一个或多个第二互连件410，使得一个或多个第二互连件410的每个的一部分穿过封装材料406而突出。封装材料406可以是相关领域的技术人员已知的任何合适的封装材料。
另一半导体封装件(未示出)可以经由第一互连件408耦接至半导体封装件400的顶部，从而形成层叠封装件模块。为了将另一半导体封装件耦接至第一互连件408，可以在封装材料406中对应于第一互连件408的位置处形成穿塑孔。因为第一互连件408由于被封装材料406封装而不可视，所以第二互连件410可以用作参照系以确定穿塑孔将要形成的位置。例如，在半导体封装件400的制造过程中，可以预定第一互连件408与一个或多个第二互连件410之间的距离。因此，因为由于一个或多个第二互连件410被部分暴露而使一个或多个第二互连件410的位置是已知的(例如，可以通过成像设备等确定)，所以可以使用预定的距离确定第一互连件408的位置。
第一互连件408和一个或多个第二互连件410可以包括但不限于，焊球、引脚、表面安装技术(SMT)焊盘和/或类似物。
在实施方式中，半导体封装件400可以以各种方式形成。例如，图5示出了流程图500，该流程图500是用于形成包括一种或多种自对准特征的半导体封装件的过程。流程图500的步骤不一定需要按示出的顺序执行。流程图500的所有步骤不需要在所有的实施方式中执行。出于说明性的目的，以下参考图6A至图6I描述流程图500。图6A至图6D、图6F、图6H和图6I示出了基板602的截面图，以及图6E、图6G和图6J分别示出了图6D、图6F和图6I中示出的基板602的平面图。应注意，不是流程图500的所有步骤都需要在所有的实施方式中执行。基于本文中提供的讨论，其他结构和操作的实施方式对相关领域的技术人员是显而易见。
流程图500开始于步骤502。在步骤502中，形成在基板上的导电层的一个或多个区域经由一个或多个第一开口暴露，其中，一个或多个区域的每个具有第一宽度。例如，如图6A中所示，基板602可以包括芯层636，该芯层636具有第一表面604和与第一表面604相对的第二表面606。芯层636可以包括介电材料。基板602也可以包括形成在第一表面604上的第一导电层612和形成在第二表面606上的第二导电层614。导电层612和导电层614可以各自包括一个或多个导电性特征，诸如用于装配诸如焊球、凸块等的互连件的焊盘。基板602可以进一步包括在第一表面604和第一导电层612上形成的第一绝缘层608和在第二表面606和第二导电层614上形成的第二绝缘层610。第一绝缘层608和第二绝缘层610的示例可以包括但不限于，钝化层或者焊剂遮蔽层。第一导电层612和第二导电层614可以经由包括在芯层636中的通孔630电气耦接。可以在芯层636上显示另外的导电层和/或电气绝缘层。
根据步骤502，第一开口616可以形成在第一绝缘层608中以暴露第一导电层612的第一区域。第一开口616可以具有第一宽度w1。第一开口616可以以任何方式形成在第一绝缘层608中，该方式包括通过刻蚀过程、通过显影过程(例如，第一绝缘层608由聚合物制成的情况)等。
在步骤504中，经由至少一个第二开口暴露导电层的至少一个第二区域，其中，至少一个第二开口具有小于第一宽度的第二宽度。例如，如图6B中所示，第二开口618形成在第一绝缘层608中，从而使导电层612的第二区域暴露。如图所示，在图6B中，第二开口618具有小于第一宽度w1的第二宽度w2。
根据实施方式，流程图500可以选择性地包括将基板附接至粘合材料的步骤。例如，如图6C中所示，第二绝缘层610的底表面620附接至粘合材料层622。粘合材料层622可以是在其表面上具有粘合材料(树脂、粘胶剂等)的片或者带(例如，纸、塑料等)，该片或者带能实现暂时施加粘合材料层340，并且随后从基板602上去除粘合材料层340。应注意，其他基板可以紧邻粘合材料层622上的基板602而放置以形成条基板(例如，单个纵列)或者板基板(例如，多维阵列)。这些其他基板可以用于形成其他半导体封装件。
例如，图6M和图6N示出了根据实施方式的可以并行处理的条基板和板基板的示例。具体地，图6M示出了在粘合材料层622上布置为条格式的第一基板602A、第二基板602B、第三基板602C和第四基板602D。图6N示出了在粘合材料层622上布置为板格式的第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F。如图6N中所示，第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F可以布置成基本上统一的横行和/或纵列，但是实施方式的范围在这方面不受限制。
在步骤506中，一个或多个第一互连件形成在导电层的一个或多个第一区域上。例如，如图6D和图6E所示，第一互连件624形成在导电层612的第一区域上。第一互连件624可以包括但不限于，焊球、引脚、表面安装技术(SMT)焊盘和/或类似物。导电层612的第一区域可以包括焊球、焊盘或者用于接纳第一互连件624的其他导电性特征。
在步骤508，一个或多个第二互连件形成在导电层的一个或多个第二区域上。例如，如图6F至图6G所示，第二互连件626形成在第一导电层612的第二区域上。第二互连件626可以包括但不限于，焊球、引脚、表面安装技术(SMT)焊盘和/或类似物。根据实施方式，第一互连件624和第二互连件626是相同的形状和/或尺寸。然而，如图6F中所示，第二互连件626相比第一互连件624各自具有到第一导电层612的更大的间隔距离–即，第二互连件626相比第一互连件624被放置得离第一导电层612更高(例如，具有更远的中心点和最外边缘)。间隔距离上的该差异是由于第二开口的宽度小于第一开口的宽度，如以上关于图6B所示出。第二开口的较小宽度防止第二互连件626安放为与第一互连件626由于第一开口的更大的宽度而可以安放的与第一导电层612一样接近。
如图6F和图6G中进一步示出，一个或多个半导体管芯628也可以耦接至基板602。例如，一个或多个半导体管芯628可以通过互连件631耦接至第一导电层612(例如，以放置第一导电层612的焊盘等)。
在步骤510，基板和一个或多个第一互连件利用封装材料被封装并且至少一个第二互连件利用封装材料部分被封装，使得至少一个第二互连件远离封装材料而突出。根据实施方式，可以使用膜辅助模制工艺来施加封装材料。例如，如图6H中所示，可以在第二互连件626上施加一层或多层膜632。
此后，从基板602的一侧(如通过箭头636示出)施加(例如，注入或者传递)封装材料634。应注意，封装材料634可以在步骤510中按与以上关于步骤204(图2)所描述的类似方式或者以替代方式来施加。
在注入封装材料634之后，一层或多层膜632从第二互连件626去除和/或粘合材料层622从第二绝缘层610的底表面620去除，从而形成包括用于确定形成穿塑孔的位置的自对准特征的半导体封装件。图6I至图6J示出了产生的半导体封装件600的示图。如图6I中所示，通过封装材料634封装半导体管芯628、第一互连件624、第一绝缘层608和邻近于基板602的空间，并且通过封装材料634部分封装第二互连件626，使得第二互连件626远离封装材料634而突出。
根据其中其他基板放置为紧邻条格式或者板格式的基板602(例如，如图6M至图6N所示)的实施方式，步骤510可以包括在封装材料634中至少部分封装条基板或者板基板。
例如，图6O至图6P示出了根据实施方式的可以包括基板的封装条和封装板的示例。具体地，图6O示出了在封装材料634中封装第一基板602A、第二基板602B、第三基板602C和第四基板602D的封装条680。图6P示出了在封装材料634中封装第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F的封装板682。如图6O至图6P的每个所示，第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F中的每个的第二互连件626被封装材料634部分封装，使得第二互连件626远离封装材料634而突出。
根据实施方式，另一半导体封装件(未示出)可以经由第一互连件624耦接至半导体封装件600的顶部，从而形成层叠封装件模块。为了将另一半导体封装件耦接至第一互连件624，可以在封装材料643中对应于第一互连件624的位置处形成穿塑孔。因为第一互连件624由于被封装材料634封装而不可视，所以第二互连件626可以用作参考系以确定要形成的穿塑孔的位置。例如，在半导体封装件600的制造过程中，可以预定第一互连件624与一个或多个第二互连件626之间的相对位置和/或距离。因此，因为由于第二互连件626被部分暴露而使第二互连件626的位置是已知的，所以可以使用相对位置/预定距离确定第一互连件624的位置。
例如，图6K示出了根据实施方式的具有形成在其中的穿塑孔636的半导体封装件600的截面图。图6L示出了图6K中示出的半导体封装件600的平面图。如图6K至图6L所示，基于第一互连件624与第二互连件626之间的预定距离，穿塑孔636形成在封装材料634中的对应于第一互连件624的位置处。例如，穿塑孔636A形成到第二互连件626的预定距离d1，并且穿塑孔636B形成到第二互连件626的预定距离d2。替代地，穿塑孔636B可以基于第一互连件624A与第一互连件624B之间的预定距离形成。例如，如图6K中所示，穿塑孔636B可以形成到第一互连件624A的预定距离d3。
穿塑孔636可以以任何方式形成，包括通过激光烧蚀工艺、钻孔(例如，机械钻孔、激光钻孔等)、通过刻蚀工艺等。
返回至图5，在步骤512中，多个互连件附接至用于装配电路板的基板。根据实施方式，多个第三互连件640可以耦接至第二导电层614，该多个第三互连件640用于将半导体封装件600装配至电路板(未示出)(例如，通过回流焊接等)。第三互连件640可以是但不限于，焊球、引脚、导柱、表面安装技术(SMT)焊盘和/或类似物。如图6K中所示，第三互连件640通过包括在芯层636中的通孔630电气连接穿过基板602至第一导电层612。第一互连件624、第二互连件626和互连件631可以因此电气耦接至第三互连件640，从而使半导体管芯628和经由互连件624/626耦接至半导体封装件600的另一半导体封装件的信号能够电气耦接至第三互连件640。
应注意，虽然图6E、图6G和图6L描述了第一互连件624被布置为球栅阵列(BGA)，但应注意，第一互连件624可以根据其他图案来布置。
在步骤514，封装基板与条或者板分离以形成至少一个半导体封装件。根据其中其他基板被放置为紧邻条格式或者板格式的基板602并且经历流程图500描述的过程以形成包括一种或多种自对准特征的其他半导体封装件的实施方式，流程图500可以选择性地包括用于将这种半导体封装件的条或者板分离为不同的半导体封装件的步骤514。半导体封装件可以以相关领域的技术人员已知的任何合适的方式被分离，以使半导体封装件彼此物理分开。例如，半导体封装件可以通过锯、刨槽机、激光器或者根据任何其他分离技术来分离。
III.结论
尽管上面描述了多个实施方式，但是应当理解的是，它们只是以示例而非限制的方式提出。对本领域技术人员显而易见，在不偏离实施方式的精神和范围的条件下，可对其中的形式和细节做出不同的改变。因此，实施方式的宽度及范围仅受以下权利要求及其等效物的限定而不受上述示例性实施方式限制。

Claims (10)

1.一种多芯片模块，其特征在于，包括：
至少两个半导体封装件，所述至少两个半导体封装件中的每个包括：
基板，具有第一表面和与所述第一表面相对的第二表面；
至少一个半导体管芯，耦接至所述基板的所述第一表面；以及
第一封装材料，封装所述至少一个管芯和所述基板的所述第一表面；以及
第二封装材料，至少部分封装所述至少两个半导体封装件。
2.根据权利要求1所述的多芯片模块，其特征在于，所述至少两个半导体封装件中的每个进一步包括：
多个互连件，耦接至所述基板的所述第二表面，所述多个互连件通过所述第二封装材料被部分封装。
3.根据权利要求1所述的多芯片模块，其特征在于，所述至少两个半导体封装件中的第一半导体封装件侧向邻近于所述至少两个半导体封装件中的第二半导体封装件，使得所述第一半导体封装件的所述基板与所述第二半导体封装件的所述基板共面。
4.根据权利要求1所述的多芯片模块，其特征在于，所述至少两个半导体封装件中的至少一个包括多个管芯。
5.根据权利要求1所述的多芯片模块，其特征在于，所述至少两个半导体封装件中的至少一个包括耦接至所述至少两个半导体封装件中的所述至少一个的至少相应的第一表面的屏蔽层。
6.根据权利要求1所述的多芯片模块，其特征在于，进一步包括：
互连件，耦接所述至少两个半导体封装件，所述互连件被所述第二封装材料封装。
7.一种半导体封装件，其特征在于，包括：
基板，具有第一表面和与所述第一表面相对的第二表面；
一个或多个第一互连件，耦接至所述基板的所述第一表面；
一个或多个第二互连件，耦接至所述基板的所述第一表面；以及
封装材料，完全封装所述一个或多个第一互连件和所述基板的所述第一表面，并且部分封装所述一个或多个第二互连件，使得所述一个或多个第二互连件通过所述封装材料被部分暴露。
8.根据权利要求7所述的半导体封装件，其特征在于，所述一个或多个第一互连件和所述一个或多个第二互连件是焊球。
9.根据权利要求7所述的半导体封装件，其特征在于，所述一个或多个第一互连件经由在所述基板的所述第一表面上形成的绝缘层中的第一组开口耦接至所述基板的所述第一表面，并且所述一个或多个第二互连件经由形成在所述绝缘层中的第二组开口耦接至所述基板的所述第一表面，其中，所述第一组开口具有第一宽度并且所述第二组开口具有小于所述第一宽度的第二宽度。
10.根据权利要求7所述的半导体封装件，其特征在于，小于第一宽度的第二宽度使所述一个或多个第二互连件与所述基板的所述第一表面的间隔距离大于所述一个或多个第一互连件与所述基板的所述第一表面的间隔距离。
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