TW201543639A - 用於半導體封裝之重構技術 - Google Patents

用於半導體封裝之重構技術 Download PDF

Info

Publication number
TW201543639A
TW201543639A TW104112903A TW104112903A TW201543639A TW 201543639 A TW201543639 A TW 201543639A TW 104112903 A TW104112903 A TW 104112903A TW 104112903 A TW104112903 A TW 104112903A TW 201543639 A TW201543639 A TW 201543639A
Authority
TW
Taiwan
Prior art keywords
semiconductor package
substrate
semiconductor
package
interconnect
Prior art date
Application number
TW104112903A
Other languages
English (en)
Other versions
TWI546927B (zh
Inventor
Edward Law
Rezaur Rahman Khan
Kun-Zhong Hu
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of TW201543639A publication Critical patent/TW201543639A/zh
Application granted granted Critical
Publication of TWI546927B publication Critical patent/TWI546927B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本文提供了一種用於半導體封裝件的重構技術。一種重構技術被用於將複數個半導體封裝件封裝為單個多芯片模塊。耦接至每個封裝件的焊球在重構之後可以部分暴露，該暴露使封裝件能够耦接至另一設備。另一重構技術被用於使用一種或複數種自對準特徵將複數個半導體封裝件耦接成層疊封裝件模塊。一種或複數種自對準特徵是包括在層疊封裝件模塊的底部封裝件中的一個或複數個暴露的焊球。一個或複數個暴露的焊球用作藉由封裝材料封裝的其他焊球的參照系。在確定這些其他焊球的位置之後，可以在封裝材料中對應於另一焊球的位置處形成穿塑孔。然後可以使用這些焊球將層疊封裝件模塊的頂部封裝件耦接至底部封裝件。

Description

用於半導體封裝件的重構技術
本申請要求於2014年4月22日提交的美國臨時申請第61/982,442號和於2014年4月28日提交的美國專利申請第14/263,718號的優先權，其全部內容引用至本文。
本文描述的主題有關於一種用於半導體封裝件的重構技術。
對於移動無線設備，期望這些設備執行的功能的數量隨著時間繼續增加，並且被開發以在這些設備中實現來執行這些功能的半導體管芯或者芯片的數目也因此增加。因此，將複數個管芯或者芯片結合到單個封裝件裡的能力變得更加重要，因為這提供了關於X、Y和Z尺寸的較小形狀因子的益處和降低的成本。
描述了用於半導體封裝件的重構技術的方法、系統和裝置，該半導體封裝件的重構技術基本上如附圖所示和/或在本文中結合至少一個附圖來描述，如在申請專利範圍中更完整提出。
本公開提供了一種多芯片模塊，包括：至少兩個半導體封裝件，前述至少兩個半導體封裝件中的每個包括：基板，具有第一表面和與前述第一表面相對的第二表面；至少一個半導體管芯，耦接至前述基 板的前述第一表面；以及第一封裝材料，封裝前述至少一個管芯和前述基板的前述第一表面；以及第二封裝材料，至少部分封裝前述至少兩個半導體封裝件。
在前述多芯片模塊中，前述至少兩個半導體封裝件中的每個進一步包括：複數個互連件，耦接至前述基板的前述第二表面，前述複數個互連件藉由前述第二封裝材料被部分封裝。
在前述多芯片模塊中，前述複數個互連件包括複數個焊球。
在前述多芯片模塊中，前述至少兩個半導體封裝件中的第一半導體封裝件側向鄰近於前述至少兩個半導體封裝件中的第二半導體封裝件，使得前述第一半導體封裝件的前述基板基本上與前述第二半導體封裝件的前述基板共平面。
在前述多芯片模塊中，前述至少兩個半導體封裝件中的至少一個包括複數個管芯。
在前述多芯片模塊中，前述至少兩個半導體封裝件中的至少一個包括耦接至前述至少兩個半導體封裝件中的前述至少一個的至少相應的第一表面的屏蔽層。
前述多芯片模塊進一步包括：互連件，耦接前述至少兩個半導體封裝件，前述互連件被前述第二封裝材料封裝。
在前述多芯片模塊中，前述互連件包括接合線。
本公開提供了一種方法，包括：放置第一半導體封裝件和第二半導體封裝件，使得前述第一半導體封裝件側向鄰近於前述第二半導體封裝件，前述第一半導體封裝件和前述第二半導體封裝件中的每個具有第一表面和與前述第一表面相對的第二表面，前述第二表面中的每 個具有複數個互連件；以及在封裝材料中至少部分封裝前述第一半導體封裝件和前述第二半導體封裝件。
在前述方法中，前述放置包括：將黏合材料層施加至前述第一半導體封裝件的前述第一表面和前述第二半導體封裝件的前述第一表面。
在前述方法中，前述至少部分封裝包括：在前述第一半導體封裝件和前述第二半導體封裝件的前述複數個互連件上施加至少一膜層；在前述至少一膜層與前述第一半導體封裝件和前述第二半導體封裝件的前述第二表面之間施加封裝材料；以及去除前述至少一膜層，前述第一半導體封裝件和前述第二半導體封裝件的前述複數個互連件通過前述封裝材料而被至少部分暴露。
在上述方法中，前述複數個互連件包括複數個焊球。
在上述方法中，前述第一半導體封裝件或者前述第二半導體封裝件中的至少一個包括在前述第一半導體封裝件或者前述第二半導體封裝件中的前述至少一個的前述第一表面上基本上包圍至少一個集成電路管芯的屏蔽層。
前述方法進一步包括：利用互連件電性並機械性地耦接前述第一半導體封裝件與前述第二半導體封裝件；並且前述至少部分封裝包括利用前述第二封裝材料封裝前述互連件。
在前述方法中，前述電性並機械性地耦接係包括：利用至少一個接合線將前述第一半導體封裝件與前述第二半導體封裝件耦接在一起。
本公開提供了一種半導體封裝件，包括：基板，具有第一表面和與前述第一表面相對的第二表面；一個或複數個第一互連件，耦接至 前述基板的前述第一表面；一個或複數個第二互連件，耦接至前述基板的前述第一表面；以及封裝材料，完全封裝前述一個或複數個第一互連件和前述基板的前述第一表面，並且部分封裝前述一個或複數個第二互連件，使得前述一個或複數個第二互連件通過前述封裝材料被部分暴露。
在前述半導體封裝件中，前述一個或複數個第一互連件和前述一個或複數個第二互連件是焊球。
前述半導體封裝件進一步包括：集成電路管芯，被安裝至前述基板的前述第一表面。
在前述半導體封裝件中，前述一個或複數個第一互連件經由在前述基板的前述第一表面上形成的絕緣層中的第一組開口耦接至前述基板的前述第一表面，並且前述一個或複數個第二互連件經由形成在前述絕緣層中的第二組開口耦接至前述基板的前述第一表面，其中，前述第一組開口具有第一寬度並且前述第二組開口具有小於前述第一寬度的第二寬度。
在前述半導體封裝件中，小於前述第一寬度的前述第二寬度使前述一個或複數個第二互連件與前述基板的前述第一表面的間隔距離大於前述一個或複數個第一互連件與前述基板的前述第一表面的間隔距離。
100‧‧‧多芯片模塊
102A‧‧‧第一半導體封裝件
102B‧‧‧第二半導體封裝件
106、348、352、406、634、643‧‧‧封裝材料
108、110、326、328、342、344、631‧‧‧互連件
112A、112B‧‧‧上表面
114A、114B、620‧‧‧底表面
116‧‧‧水平面
200、500‧‧‧流程圖
302A‧‧‧第一半導體封裝件
302B‧‧‧第一半導體封裝件
302C‧‧‧第三半導體封裝件
304‧‧‧第一半導體管芯
306‧‧‧第二半導體管芯
308、402、602‧‧‧基板
310、340、622‧‧‧黏合材料層
312‧‧‧第一表面
314‧‧‧第二表面
316、608‧‧‧第一絕緣層
318、610‧‧‧第二絕緣層
320、612‧‧‧第一導電層
322、614‧‧‧第二導電層
330‧‧‧接合線
332、630‧‧‧通孔
336、354、356、412、604‧‧‧第一表面
338、414、606‧‧‧第二表面
346、632‧‧‧膜
350、636‧‧‧芯層
358‧‧‧電磁干擾屏蔽層(EMI屏蔽層)
364‧‧‧箭頭
370A‧‧‧第一組(第一組半導體封裝件)
370B‧‧‧第二組(第二組半導體封裝件)
370C‧‧‧第三組(第三組半導體封裝件)
370D‧‧‧第四組(第四組半導體封裝件)
370E‧‧‧第五組(第五組半導體封裝件)
370F‧‧‧第六組(第六組半導體封裝件)
380‧‧‧條
400、600‧‧‧半導體封裝件
404、628‧‧‧半導體管芯
408、624、624A、624B‧‧‧第一互連件
410、626‧‧‧第二互連件
602A‧‧‧第一基板
602B‧‧‧第二基板
602C‧‧‧第三基板
602D‧‧‧第四基板
602E‧‧‧第五基板
602F‧‧‧第六基板
616‧‧‧第一開口
618‧‧‧第二開口
636、636A、636B‧‧‧穿塑孔
640‧‧‧第三互連件
682‧‧‧封裝板
d1、d2‧‧‧預定距離
w1‧‧‧第一寬度
w2‧‧‧第二寬度
圖1示出了根據本文描述的實施方式的重構的多芯片模塊的剖視圖。
圖2示出了根據本文描述的實施方式的提供用於形成重構的多芯片模塊的示例步驟的流程圖。
圖3A示出了根據本文描述的實施方式的被放置為側向鄰近於彼此的三個半導體封裝件的剖視圖。
圖3B示出了根據本文描述的實施方式的三個半導體封裝件在被附接至黏合材料層之後的剖視圖。
圖3C示出了根據本文描述的實施方式的三個半導體封裝件在藉由一個或複數個互連件耦接之後的剖視圖。
圖3D示出了根據本文描述的實施方式的在三個半導體封裝件上執行的膜輔助模製步驟的剖視圖。
圖3E示出了根據本文描述的實施方式的重構的多芯片模塊的剖視圖。
圖3F至圖3G示出了根據實施方式的可被重構的條封裝件和板封裝件的示例。
圖3H至圖3I示出了根據實施方式的可被重構的封裝(encapsulated，封包)的條封裝件和板封裝件的示例。
圖4示出了根據本文描述的實施方式的包括自對準特徵的半導體封裝件的剖視圖。
圖5示出了根據本文描述的實施方式的提供用於形成包括自對準特徵的半導體封裝件的示例步驟的流程圖。
圖6A示出了根據本文描述的實施方式的基板在經由一個或複數個第一開口而暴露該基板的導電層的一個或複數個第一區域之後的剖視圖。
圖6B示出了根據本文描述的實施方式的基板在經由一個或複數個第二開口而暴露導電層的一個或複數個第二區域之後的剖視圖。
圖6C示出了根據本文描述的實施方式的基板在被附接至黏合材料層之後的剖視圖。
圖6D示出了根據本文描述的實施方式的基板在導電層的一個或複數個第一區域上形成一個或複數個第一互連件之後的剖視圖。
圖6E示出了根據本文描述的實施方式的在圖6D中示出的基板的平面圖。
圖6F示出了根據本文描述的實施方式的基板在導電層的一個或複數個第二區域上形成一個或複數個第二互連件之後的剖視圖。
圖6G示出了根據本文描述的實施方式的在圖6F中示出的基板的平面圖。
圖6H示出了根據本文描述的實施方式的在基板上執行的膜輔助模製步驟的剖視圖。
圖6I示出了根據本文描述的實施方式的基板在完成膜輔助模製步驟之後的剖視圖。
圖6J示出了根據本文描述的實施方式的在圖6I中示出的基板的平面圖。
圖6K示出了根據本文描述的實施方式的基板在藉由封裝基板的封裝材料形成穿塑孔(through-mold vias)之後的剖視圖。
圖6L示出了根據本文描述的實施方式的在圖6K中示出的基板的平面圖。
圖6M和圖6N示出了根據實施方式的可並行處理的條基板和板基板的示例。
圖6O和圖6P示出了根據實施方式的可並行處理的封裝的條基板和板基板的示例。
取入本文中並組成說明書的一部分的附圖示出了實施方式，並與說明書一起進一步用來解釋實施方式的原理，並使得所屬技術領域中具有通常知識者能够實施和使用實施方式。
現將參考附圖描述實施方式。在附圖中，類似的參考標號表示相同或者功能上類似的元件。另外，參考標號的最左邊的數字確定參考標號第一次出現的附圖。
I.引言
本說明書公開複數個示例性實施方式。本專利申請的範圍不限於公開的實施方式，還包括公開的實施方式、以及公開的實施方式的修改的組合。
在本說明書中引用“一個實施方式”、“實施方式”、“示例實施方式”等表示所描述的實施方式可包括特定的特徵、結構或特性，但是每個實施方式無需包括特定的特徵、結構或特性。此外，這種用語不一定指同一實施方式。此外，當特定特徵、結構或特性結合實施方式進行了說明時，應當認為這是在所屬技術領域中具有通常知識者的知識範圍內結合其他實施方式(不管明確描述與否)來影響這種特徵、結構或特性。
在實施方式中，提供用於半導體封裝件的各種重構技術。根據實施方式，重構技術被用於將複數個半導體封裝件封裝為單個多芯片模塊。根據這種實施方式，每個半導體封裝件可以在重構之前被裝配和/或測試。在重構過程中，也可以使用一個或複數個互連件(例如，接合線)電性並機械性地連接半導體封裝件。耦接至每個封裝件的基 板的焊球可以在重構之後部分地暴露，藉由暴露使單個多芯片模塊能够耦接至另一設備(例如，電路板)。
根據另一實施方式，重構技術被用於使用自對準特徵將複數個半導體封裝件連接為層疊封裝件模塊。根據這種實施方式，自對準特徵是包括在封裝件中的位於層疊封裝件模塊的底部上的至少一個部分暴露的焊球。該至少一個部分暴露的焊球用作藉由封裝材料封裝(且因此，不可視)的其他焊球的參照系。在使用至少一個部分暴露的焊料模具確定這些其他焊球的位置之後，可以在對應於其他焊球的位置上形成穿塑孔。然後可以使用這些焊球將層疊封裝件模塊的頂部封裝件耦接至底部封裝件。因此，至少一個部分暴露的焊球可以有利地用於補償在底部封裝件的重構過程中出現的任何潜在未對準。
在實施方式中，描述了多芯片模塊。該多芯片模塊包括至少兩個半導體封裝件。至少兩個半導體封裝件中的每個包括基板、至少一個半導體管芯及第一封裝材料。對於每個封裝件，基板具有第一表面和與第一表面相對的第二表面，該至少一個半導體管芯耦接至基板的第一表面，並且第一封裝材料封裝至少一個管芯和基板的第一表面。多芯片模塊進一步包括至少部分封裝至少兩個半導體封裝件的第二封裝材料。
描述了示例性方法。該方法包括使第一半導體封裝件和第二半導體封裝件放置為使得第一半導體封裝件側向鄰近於第二半導體封裝件。第一半導體封裝件和第二半導體封裝件的每個具有第一表面和與第一表面相對的第二表面。每個第二表面具有複數個互連件。第一半導體封裝件和第二半導體封裝件在封裝材料中至少部分被封裝。
還描述了半導體封裝件。半導體封裝件包括基板、一個或複數個第一互連件、一個或複數個第二互連件及封裝材料。基板具有第一表面和與第一表面相對的第二表面。一個或複數個第一互連件耦接至基板的第一表面。一個或複數個第二互連件也耦接至基板的第一表面。封裝材料封裝一個或複數個第一互連件和基板的第一表面，並且部分封裝一個或複數個第二互連件，使得一個或複數個第二互連件部分被暴露(亦即，部分沒有被封裝材料覆蓋，且因此從外部可接入半導體封裝件)。
II.示例性實施方式
A.用於多芯片模塊的重構技術
如上所述，除了機械性地耦接在一起(例如，藉由封裝材料保持在一起、藉由接合線或者其他導體連接等)之外，多芯片模塊可以形成為包括可選擇地電性耦接在一起(例如，藉由接合線等)的複數個半導體封裝件。半導體封裝件被並排地放置為側向鄰近於彼此(例如，封裝件的基板基本上彼此共平面)。在實施方式中，這種多芯片模塊可以以各種方式配置。
例如，圖1示出了根據示例性實施方式的重構的多芯片模塊100的剖視圖。如圖1中所示，多芯片模塊100包括第一半導體封裝件102A和第二半導體封裝件102B，該第二半導體封裝件102B被放置為側向鄰近於第一半導體封裝件102A(亦即，第一半導體封裝件102A和第一半導體封裝件102B在圖1中的水平面116上基本上是共平面的)。根據實施方式，第一半導體封裝件102A和/或第二半導體封裝件102B可以包括基板和耦接至基板的一個或複數個半導體管芯。根據另一實施方式，第一半導體封裝件102A和/或第二半導體封裝件102B可以 是包括耦接至晶圓的一個或複數個半導體管芯的晶圓級封裝件(亦即，晶圓級封裝件不包括封裝件基板)。
可以藉由封裝材料封裝一個或複數個半導體管芯。基板可以包括一個或複數個導電層、通孔、介電層等。第一半導體封裝件102A和第二半導體封裝件102B的每個也可以包括複數個互連件108，該互連件108被用於接口連接位於其中的一個或複數個半導體管芯與電路板(例如，印刷電路板)(未示出)。互連件108可以包括但不限於焊球、引脚、導柱、表面安裝技術(SMT)焊盤和/或類似物。
第一半導體封裝件102A和第二半導體封裝件102B可以電性並機械性地經由一個或複數個互連件110彼此耦接。一個或複數個互連件110可以包括一個或複數個接合線(也稱為“絲焊”)、一個或複數個無源組件(例如，一個或複數個電阻器)和/或類似物。
藉由至少部分封裝第一半導體封裝件102A、第二半導體封裝件102B以及封裝材料106中的一個或複數個互連件110，可以使第一半導體封裝件102A和第二半導體封裝件102B重構在一起。例如，如圖1中所示，第一半導體封裝件102A和第二半導體封裝件102B的上表面112A和上表面112B、底表面114A和底表面114B、側表面、第一半導體封裝件102A和第二半導體封裝件102B之間的空間、以及一個或複數個互連件110藉由封裝材料106來封裝。此外，藉由封裝材料106使互連件108部分被封裝，從而使多芯片模塊100能够藉由互連件108的暴露部分耦接至電路板。
根據實施方式，封裝材料106可以包括與用於封裝第一半導體封裝件102A和第二半導體封裝件102B的一個或複數個半導體管芯的封裝材料不同的材料。例如，封裝材料106可以包括具有相對大的填充 物尺寸(例如，40至50微米的填充物尺寸)和/或具有基本上標準的或者較高的α粒子放射率的低級材料，然而封裝包括在第一半導體封裝件102A和第二半導體封裝件102B中的一個或複數個半導體管芯的封裝材料可以包括高級材料，諸如具有相對低的α粒子放射率的填充物尺寸(例如，填充物尺寸小於20微米和/或α粒子率低於封裝材料106)的材料。
雖然圖1示出了多芯片模塊100包括兩個半導體封裝件，但應注意，在某些實施方式中，多芯片模塊100可以包括任意數量的半導體封裝件。根據該實施方式，半導體封裝件可以以任何方式被放置為鄰近於彼此。
在實施方式中，半導體封裝件102A和半導體封裝件102B(和另外的封裝件)可以以各種方式重構為多芯片模塊。例如，圖2示出了流程圖200，該流程圖200是根據實施方式的用於形成重構的多芯片模塊的過程。為了說明性的目的，以下參考圖3A至圖3E描述流程圖200。圖3A至圖3E示出了根據實施方式的三個半導體封裝件302A、302B和302C的剖視圖。應注意，不需要在所有的實施方式中執行流程圖200的所有步驟。基於本文中提供的討論，其他結構和操作的實施方式對於所屬技術領域中具有通常知識者來說是顯而易見的。
流程圖200開始於步驟202。在步驟202中，第一半導體封裝件和第二半導體封裝件被放置為使得第一半導體封裝件側向鄰近於第二半導體封裝件。第一半導體封裝件和第二半導體封裝件中的每個具有第一表面和與第一表面相對的第二表面。每個第二表面具有複數個互連件。
例如，圖3A示出了放置為側向鄰近於彼此的三個半導體封裝件302A、302B和302C的剖視圖。第一半導體封裝件302A具有第一表面336和與第一表面336相對的第二表面338。第一半導體封裝件302A可以包括一個或複數個半導體管芯(例如，第一半導體管芯304和第二半導體管芯306)、基板308和耦接至第二表面338的互連件326的陣列，一個或複數個半導體管芯可以堆疊(如在圖3A中)或者放置為鄰近於彼此。可以使用黏合材料層310將第一半導體管芯304的非活性表面裝配至第二半導體管芯306的非活性表面。基板308可以包括芯層350(例如，介電材料層)，芯層350具有第一表面312和與第一表面312相對的第二表面314。基板308還可以包括形成在第一表面312上的第一導電層320和形成在第二表面314上的第二導電層322。基板308可以進一步包括在第一表面312和第一導電層320上形成的第一絕緣層316和在第二表面314和第二導電層322上形成的第二絕緣層318。第一絕緣層316和第二絕緣層318的示例可以包括但不限於，鈍化層或者焊劑遮蓋層。在實施方式中，可以在芯層350上進一步堆疊導電層和/或電性絕緣層。
複數個接合線330可以將第一半導體管芯304的活性表面上的端子(未示出)耦接至第一導電層320(例如，至傳導性的配線、焊盤和/或其他特徵)。第二半導體管芯306可以具有將第二半導體管芯306的活性表面上的端子(未示出)耦接至第一導電層320的複數個互連件328。互連件328的示例可以包括但不限於焊球、引脚、SMT焊盤和/或類似物。
互連件326可以用於將第一半導體封裝件302A裝配至電路板(未示出)(例如，藉由回流焊接等)。互連件326可以是但不限於焊球、 引脚、導柱、表面安裝技術(SMT)焊盤和/或類似物。如圖3A中所示，互連件326耦接至基板308的第二導電層322。互連件326藉由包括在芯層350中的通孔324穿過基板308電性耦接至第一導電層320。接合線330和互連件328因此耦接至互連件326，從而使第一半導體管芯304和第二半導體管芯306的信號能够電性耦接至互連件326。
封裝材料352覆蓋第一半導體管芯304、第二半導體管芯306、接合線330、互連件328及第一絕緣層316。封裝材料352可以是所屬技術領域中具有通常知識者已知的任何合適類型的封裝材料(高級、中級或低級)。在一個實施方式中，封裝材料352可以包括高級材料(例如，具有小於20微米的最大填充物尺寸和/或具有低α粒子發射率的材料)。
第二半導體封裝件302B和第三半導體封裝件302C可以以與第一半導體封裝件302A類似的方式配置。因而，為了便於說明，不分開詳細描述封裝件302B和封裝件302C的結構。應注意，第一半導體封裝件302A、第二半導體封裝件302B及第三半導體封裝件302C的每個可以包括具有變化的尺寸和/或功能的任意數量的半導體管芯。另外，第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C可以各自包括不同的特徵。例如，如圖3A中所示，第三半導體封裝件302C包括電磁干擾(EMI)屏蔽層358。EMI屏蔽層358可以包括金屬(例如，銅、鎳、金、銀、鉑、鈷、鈦、鉻、鋯、鉬、釕、鉿、鎢、錸和/或類似物)。在封裝件302C的示例中，EMI屏蔽層358包圍封裝件基板的頂表面上的一對堆疊的管芯。以這種方式，EMI屏蔽層358執行關於在操作過程中從一個或兩個管芯中發出的輻 射和/或關於在操作過程中保護一個或複數個管芯免受在封裝件302C外部的源產生的EMI的EMI屏蔽。
如上所述，半導體封裝件302A、半導體封裝件302B和半導體封裝件302C放置為側向鄰近於彼此。例如，半導體封裝件302A、半導體封裝件302B和半導體封裝件302C可以放置為使得第一半導體封裝件302A的基板308基本上與第二半導體封裝件302B的基板共平面，並且使得第二半導體封裝件302B的基板基本上與第三半導體封裝件302C的基板共平面。
根據實施方式，步驟202還可以包括將第一半導體封裝件的第一表面和第二半導體封裝件的第一表面附接至黏合材料層。例如，如圖3B中所示，第一半導體封裝件302A的第一表面336、第二半導體封裝件302B的第一表面354和第三半導體封裝件302C的第一表面356附接至黏合材料層340。黏合材料層340可以是具有黏合材料(樹脂、黏膠劑等，能够暫時施加(apply，塗覆)黏合材料層340，並且隨後從封裝件去除黏合材料層340)在其表面上的片或者帶(例如，紙張、塑料等)。
根據另一實施方式，步驟202還可以包括將其他半導體封裝件放置為緊鄰半導體封裝件302A、半導體封裝件302B和半導體封裝件302C以形成條半導體封裝件(例如，單個縱列)或者板半導體封裝件(例如，多維陣列)。這些其他半導體封裝件可以用於形成其他一個或複數個多芯片模塊。
例如，圖3F至圖3G示出了根據實施方式的可以包括半導體封裝件組的條和板的示例。具體地，圖3F示出了在黏合材料層340上布置為條格式的半導體封裝件的第一組370A、半導體封裝件的第二組 370B、半導體封裝件的第三組370C和半導體封裝件的第四組370D。第一組370A、第二組370B、第三組370C和第四組370D的每個可以包括複數個半導體封裝件(例如，第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C，如圖3A至圖3B所示)。圖3G示出了在黏合材料層340上布置為板格式的第一組半導體封裝件370A、第二組半導體封裝件370B、第三組半導體封裝件370C、第四組半導體封裝件370D、第五組半導體封裝件370E和第六組半導體封裝件370F。如圖3G中所示，第一組370A、第二組370B、第三組370C、第四組370D、第五組370E和第六組370F可以布置成基本上統一的橫列(row)和/或縱行(column)，但是實施方式的範圍在這方面不受限制。
根據另一實施方式，第一半導體封裝件和第二半導體封裝件可以藉由一個或複數個互連件機械性並電性地耦接。例如，如圖3C中所示，第一半導體封裝件302A和第二半導體封裝件302B藉由互連件342機械並電性地耦接，並且第二半導體封裝件302B和第三半導體封裝件302C藉由互連件344機械性並電性地耦接。互連件342和互連件344可以使來自位於第一半導體封裝件302A的半導體管芯的信號能够在位於第二半導體封裝件302B和/或第三半導體封裝件302C的半導體管芯之間被傳送。例如，互連件342和互連件344的每個可以耦接至各自的半導體封裝件(例如，半導體封裝件302A、半導體封裝件302B和半導體封裝件302C)的各自的第一導電層(例如，第一導電層320)。例如，互連件342和互連件344中的每個可以耦接至第三導電層(例如，第三導電層334)，該第三導電層包括在各個半導 體封裝件的第二絕緣層(例如，第二絕緣層318)中。第三導電層藉由通孔(例如，通孔332)耦接至第一導電層。
互連件342和互連件344可以包括一個或複數個接合線、一個或複數個無源組件(例如，一個或複數個電阻器)和/或類似物。互連件342和互連件344可以以任何方式(包括藉由拾取和放置裝置、引線接合裝置等)來施加。雖然互連件342和344在圖3C中示出為各自耦接第一封裝件至第二封裝件，但是可以存在任意數量的互連件以耦接具體的封裝件至一個或複數個其他封裝件，任意數量的互連件包括幾個、幾十個、數百個、乃至數千個的許多互連件。
回到圖2，在步驟204，第一半導體封裝件和第二半導體封裝件至少部分在封裝材料中被封裝。根據實施方式，第一半導體封裝件和第二半導體封裝件可以使用膜輔助模製步驟、插入模製步驟(例如，橡膠插入模製步驟)和/或類似物至少部分地在封裝材料中被封裝。例如，圖3D示出了膜輔助模製步驟，其中，一層或多層膜346可以在第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C的互連件326上被施加。例如，膜346可以是與互連件326一致的和/或可以在壓力或者壓縮下保持鄰近於互連件326的彈性材料的塑料或者其他層。此後，在膜346與黏合材料層340之間的第一半導體封裝件302A、第二半導體封裝件302B、和第三半導體封裝件302C的一側(如藉由箭頭364示出的)施加封裝材料348。封裝材料348可以是如所屬技術領域中具有通常知識者已知的任何合適的封裝材料。在實施方式中，封裝材料348可以包括低級材料(例如，具有40微米至50微米的最大填充物尺寸和/或具有比較高的α粒子放射率(例如，大於0.02 α粒子/小時．cm2)的材料)。
在注入並對封裝材料348進行固化之後，將一層或多層膜346從互連件326去除和/或將黏合材料層340從第一半導體封裝件302A的第一表面336、第二半導體封裝件302B的第一表面354和第三半導體封裝件302C的第一表面356去除，從而形成包括部分暴露的互連件326的多芯片模塊。
根據其中其他半導體封裝件放置為緊鄰條格式或者板格式的半導體封裝件302A、半導體封裝件302B和半導體封裝件302C的實施方式(例如，如圖3F至圖3G所示)，步驟204可以包括在封裝材料348中至少部分地封裝條半導體封裝件或者板半導體封裝件。
例如，圖3H至圖3I示出了根據實施方式的可以包括半導體封裝件組的封裝的條和板的示例。具體地，圖3H示出了在封裝材料348中封裝第一組半導體封裝件370A、第二組半導體封裝件370B、第三組半導體封裝件370C和第四組半導體封裝件370D的封裝的條380。圖3I示出了在封裝材料348中封裝第一組半導體封裝件370A、第二組半導體封裝件370B、第三組半導體封裝件370C、第四組半導體封裝件370D、第五組半導體封裝件370E和第六組半導體封裝件370F的封裝板382。如圖3H至圖3I的每個所示，包括在第一組370A、第二組370B、第三組370C、第四組370D、第五組370E和/或第六組370F的每個中的半導體封裝件(例如，如圖3E中所示的第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C)的互連件326部分被暴露，使得互連件326從封裝材料348突出。
返回至圖2，在步驟206中，封裝的第一半導體封裝件和第二半導體封裝件與條或者板分離(singulate，單一化)以形成多芯片模塊。例如，根據其中其他半導體封裝件以條格式或者板格式(例如，如圖 3F至圖3G所示)放置為緊鄰半導體封裝件302A、半導體封裝件302B和半導體封裝件302C並且隨後藉由封裝材料348封裝(如以上關於步驟204的描述，並且如圖3H至圖3I中示出)的實施方式，流程圖200可以選擇性地包括將半導體封裝件組(例如，第一組370A、第二組370B、第三組370C、第四組370D、第五組370E和/或第六組370F，如圖3H至圖3I所示)的條或者板分離為不同的多芯片模塊的步驟206。半導體封裝件可以以相關領域的技術人員已知的任何合適的方式被分離，以物理分開半導體封裝件組與其他半導體封裝件組。例如，半導體封裝件可以藉由鋸、刨槽機、雷射器或者根據任何其他分離技術來分離。
圖3E示出了產生的多芯片模塊300。如圖3E中所示，藉由封裝材料348部分封裝第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C的每個。具體地，藉由封裝材料348封裝鄰近於第一半導體封裝件302A、第二半導體封裝件302B和第三半導體封裝件302C的每個的空間，藉由封裝材料348封裝第一半導體封裝件302A的第二表面338、第二半導體封裝件302B的第二表面360和第三半導體封裝件302C的第三表面362，並且藉由封裝材料348封裝互連件342和互連件344。第一半導體封裝件302A的第一表面336、第二半導體封裝件302B的第一表面354和第三半導體封裝件302C的第一表面356可以是左側暴露的。然而實施方式的範圍在這方面不受限制。例如，根據某些實施方式，也可以藉由封裝材料348封裝第一半導體封裝件302A的第一表面336、第二半導體封裝件302B的第一表面354和第三半導體封裝件302C的第一表面356(如圖1中所示)。互連件326部分被暴露，使得互連件326從封裝材料348 突出。互連件326由於在膜輔助模製過程中一層或多層膜346的施加而部分地從左側暴露，如圖3D中所示。
因此，可以使用互連件326的暴露部分將多芯片模塊300裝配至電路板(例如，PCB)。如上所述，在實施方式中，相對於封裝一個或複數個封裝件302A、封裝件302B和/或封裝件302C的封裝材料352的等級(例如，高級)，將多芯片模塊300保持在一起的封裝材料348可以是低級材料，以節省多芯片模塊成本。
B.用於使用自對準特徵的層疊封裝件模塊的重構技術
如上所述，可以形成包括具有兩組互連件的半導體封裝件的半導體封裝件。封裝件的封裝材料完全將一個或複數個第一互連件封裝在封裝件的基板表面上，並且部分將一個或複數個第二互連件封裝在基板表面上，使得一個或複數個第二互連件被部分暴露(亦即，部分沒有被封裝材料覆蓋，且因此可從外部接入半導體封裝件)。在實施方式中可以以各種方式配置這種封裝件。
例如，圖4示出了根據示例性實施方式的包括一種或複數種自對準特徵的半導體封裝件400的剖視圖。如圖4中所示，半導體封裝件400包括基板402、一個或複數個半導體管芯(例如，半導體管芯404)、複數個第一互連件408和一個或複數個第二互連件410。基板402具有第一表面412和與第一表面412相對的第二表面414。基板402可以包括一個或複數個導電層、通孔、絕緣層等。第一互連件408和一個或複數個第二互連件410可以耦接至基板402的第一表面412。半導體管芯404可以裝配至第一表面412(例如，藉由使用黏合材料(圖4中未示出))。封裝材料406可以封裝一個或複數個半導體管芯404、第一互連件408、基板402的第一表面412和鄰近於基板402的空間。 根據實施方式，封裝材料406還可以封裝第二表面414。封裝材料406部分封裝一個或複數個第二互連件410，使得一個或複數個第二互連件410的每個的一部分穿過封裝材料406而突出。封裝材料406可以是所屬技術領域中具有通常知識者已知的任何合適的封裝材料。
另一半導體封裝件(未示出)可以經由第一互連件408耦接至半導體封裝件400的頂部，從而形成層疊封裝件模塊。為了將另一半導體封裝件耦接至第一互連件408，可以在封裝材料406中對應於第一互連件408的位置處形成穿塑孔。因為第一互連件408由於被封裝材料406封裝而不可視，所以第二互連件410可以用作參照系以確定穿塑孔將要形成的位置。例如，在半導體封裝件400的製造過程中，可以預定第一互連件408與一個或複數個第二互連件410之間的距離。因此，因為由於一個或複數個第二互連件410被部分暴露而使一個或複數個第二互連件410的位置是已知的(例如，可以藉由成像設備等確定)，所以可以使用預定的距離確定第一互連件408的位置。
第一互連件408和一個或複數個第二互連件410可以包括但不限於焊球、引脚、表面安裝技術(SMT)焊盤和/或類似物。
在實施方式中，半導體封裝件400可以以各種方式形成。例如，圖5示出了流程圖500，該流程圖500是用於形成包括一種或複數種自對準特徵的半導體封裝件的過程。流程圖500的步驟不一定需要按示出的順序執行。流程圖500的所有步驟不需要在所有的實施方式中執行。出於說明性的目的，以下參考圖6A至圖6I描述流程圖500。圖6A至圖6D、圖6F、圖6H和圖6I示出了基板602的剖視圖，以及圖6E、圖6G和圖6J分別示出了圖6D、圖6F和圖6I中示出的基板602的平面圖。應注意，不是流程圖500的所有步驟都需要在所有的 實施方式中執行。基於本文中提供的討論，其他結構和操作的實施方式對相關領域的技術人員是顯而易見。
流程圖500開始於步驟502。在步驟502中，形成在基板上的導電層的一個或複數個區域經由一個或複數個第一開口暴露，其中，一個或複數個區域的每個具有第一寬度。例如，如圖6A中所示，基板602可以包括芯層636，該芯層636具有第一表面604和與第一表面604相對的第二表面606。芯層636可以包括介電材料。基板602也可以包括形成在第一表面604上的第一導電層612和形成在第二表面606上的第二導電層614。導電層612和導電層614可以各自包括一個或複數個導電性特徵，諸如用於裝配諸如焊球、凸塊等的互連件的焊盤。基板602可以進一步包括在第一表面604和第一導電層612上形成的第一絕緣層608和在第二表面606和第二導電層614上形成的第二絕緣層610。第一絕緣層608和第二絕緣層610的示例可以包括但不限於，鈍化層或者焊劑遮蔽層。第一導電層612和第二導電層614可以經由包括在芯層636中的通孔630電性耦接。可以在芯層636上顯示另外的導電層和/或電性絕緣層。
根據步驟502，第一開口616可以形成在第一絕緣層608中以暴露第一導電層612的第一區域。第一開口616可以具有第一寬度w1。第一開口616可以以任何方式形成在第一絕緣層608中，該方式包括藉由刻蝕過程、藉由顯影過程(例如，第一絕緣層608由聚合物製成的情况)等。
在步驟504中，經由至少一個第二開口暴露導電層的至少一個第二區域，其中，至少一個第二開口具有小於第一寬度的第二寬度。例如，如圖6B中所示，第二開口618形成在第一絕緣層608中，從而 使導電層612的第二區域暴露。如圖所示，在圖6B中，第二開口618具有小於第一寬度w1的第二寬度w2。
根據實施方式，流程圖500可以選擇性地包括將基板附接至黏合材料的步驟。例如，如圖6C中所示，第二絕緣層610的底表面620附接至黏合材料層622。黏合材料層622可以是在其表面上具有黏合材料(樹脂、黏膠劑等)的片或者帶(例如，紙、塑料等)，該片或者帶能實現暫時施加黏合材料層340，並且隨後從基板602上去除黏合材料層340。應注意，其他基板可以緊鄰黏合材料層622上的基板602而放置以形成條基板(例如，單個縱列)或者板基板(例如，多維陣列)。這些其他基板可以用於形成其他半導體封裝件。
例如，圖6M和圖6N示出了根據實施方式的可以並行處理的條基板和板基板的示例。具體地，圖6M示出了在黏合材料層622上布置為條格式的第一基板602A、第二基板602B、第三基板602C和第四基板602D。圖6N示出了在黏合材料層622上布置為板格式的第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F。如圖6N中所示，第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F可以布置成基本上統一的橫列和/或縱行，但是實施方式的範圍在這方面不受限制。
在步驟506中，一個或複數個第一互連件形成在導電層的一個或複數個第一區域上。例如，如圖6D和圖6E所示，第一互連件624形成在導電層612的第一區域上。第一互連件624可以包括但不限於焊球、引脚、表面安裝技術(SMT)焊盤和/或類似物。導電層612 的第一區域可以包括焊球、焊盤或者用於接納第一互連件624的其他導電性特徵。
在步驟508，一個或複數個第二互連件形成在導電層的一個或複數個第二區域上。例如，如圖6F至圖6G所示，第二互連件626形成在第一導電層612的第二區域上。第二互連件626可以包括但不限於焊球、引脚、表面安裝技術(SMT)焊盤和/或類似物。根據實施方式，第一互連件624和第二互連件626是相同的形狀和/或尺寸。然而，如圖6F中所示，第二互連件626相比第一互連件624各自具有到第一導電層612的更大的間隔距離，亦即第二互連件626相比第一互連件624被放置得離第一導電層612更高(例如，具有更遠的中心點和最外邊緣)。間隔距離上的該差異是由於第二開口的寬度小於第一開口的寬度，如以上關於圖6B所示出。第二開口的較小寬度防止第二互連件626安放為與第一互連件626由於第一開口的更大的寬度而可以安放的與第一導電層612一樣接近。
如圖6F和圖6G中進一步示出，一個或複數個半導體管芯628也可以耦接至基板602。例如，一個或複數個半導體管芯628可以藉由互連件631耦接至第一導電層612(例如，以放置第一導電層612的焊盤等)。
在步驟510，基板和一個或複數個第一互連件利用封裝材料被封裝並且至少一個第二互連件利用封裝材料部分被封裝，使得至少一個第二互連件遠離封裝材料而突出。根據實施方式，可以使用膜輔助模製步驟來施加封裝材料。例如，如圖6H中所示，可以在第二互連件626上施加一層或多層膜632。
此後，從基板602的一側(如藉由箭頭636示出)施加(例如，注入或者傳遞)封裝材料634。應注意，封裝材料634可以在步驟510中按與以上關於步驟204(圖2)所描述的類似方式或者以替代方式來施加。
在注入封裝材料634之後，一層或多層膜632從第二互連件626去除和/或黏合材料層622從第二絕緣層610的底表面620去除，從而形成包括用於確定形成穿塑孔的位置的自對準特徵的半導體封裝件。圖6I至圖6J示出了產生的半導體封裝件600的示圖。如圖6I中所示，藉由封裝材料634封裝半導體管芯628、第一互連件624、第一絕緣層608和鄰近於基板602的空間，並且藉由封裝材料634部分封裝第二互連件626，使得第二互連件626遠離封裝材料634而突出。
根據其中其他基板放置為緊鄰條格式或者板格式的基板602(例如，如圖6M至圖6N所示)的實施方式，步驟510可以包括在封裝材料634中至少部分封裝條基板或者板基板。
例如，圖6O至圖6P示出了根據實施方式的可以包括基板的封裝條和封裝板的示例。具體地，圖6O示出了在封裝材料634中封裝第一基板602A、第二基板602B、第三基板602C和第四基板602D的封裝條680。圖6P示出了在封裝材料634中封裝第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F的封裝板682。如圖6O至圖6P的每個所示，第一基板602A、第二基板602B、第三基板602C、第四基板602D、第五基板602E和第六基板602F中的每個的第二互連件626被封裝材料634部分封裝，使得第二互連件626遠離封裝材料634而突出。
根據實施方式，另一半導體封裝件(未示出)可以經由第一互連件624耦接至半導體封裝件600的頂部，從而形成層疊封裝件模塊。為了將另一半導體封裝件耦接至第一互連件624，可以在封裝材料643中對應於第一互連件624的位置處形成穿塑孔。因為第一互連件624由於被封裝材料634封裝而不可視，所以第二互連件626可以用作參考系以確定要形成的穿塑孔的位置。例如，在半導體封裝件600的製造過程中，可以預定第一互連件624與一個或複數個第二互連件626之間的相對位置和/或距離。因此，因為由於第二互連件626被部分暴露而使第二互連件626的位置是已知的，所以可以使用相對位置/預定距離確定第一互連件624的位置。
例如，圖6K示出了根據實施方式的具有形成在其中的穿塑孔636的半導體封裝件600的剖視圖。圖6L示出了圖6K中示出的半導體封裝件600的平面圖。如圖6K至圖6L所示，基於第一互連件624與第二互連件626之間的預定距離，穿塑孔636形成在封裝材料634中的對應於第一互連件624的位置處。例如，穿塑孔636A形成到第二互連件626的預定距離d1，並且穿塑孔636B形成到第二互連件626的預定距離d2。替代地，穿塑孔636B可以基於第一互連件624A與第一互連件624B之間的預定距離形成。例如，如圖6K中所示，穿塑孔636B可以形成到第一互連件624A的預定距離d3。
穿塑孔636可以以任何方式形成，包括藉由雷射燒蝕步驟、鑽孔(例如，機械鑽孔、雷射鑽孔等)、藉由刻蝕步驟等。
返回至圖5，在步驟512中，複數個互連件附接至用於裝配電路板的基板。根據實施方式，複數個第三互連件640可以耦接至第二導電層614，該複數個第三互連件640用於將半導體封裝件600裝配至 電路板(未示出)(例如，藉由回流焊接等)。第三互連件640可以是但不限於焊球、引脚、導柱、表面安裝技術(SMT)焊盤和/或類似物。如圖6K中所示，第三互連件640藉由包括在芯層636中的通孔630電性連接穿過基板602至第一導電層612。第一互連件624、第二互連件626和互連件631可以因此電性耦接至第三互連件640，從而使半導體管芯628和經由互連件624/626耦接至半導體封裝件600的另一半導體封裝件的信號能够電性耦接至第三互連件640。
應注意，雖然圖6E、圖6G和圖6L描述了第一互連件624被布置為球栅陣列(BGA)，但應注意，第一互連件624可以根據其他圖案來布置。
在步驟514，封裝基板與條或者板分離以形成至少一個半導體封裝件。根據其中其他基板被放置為緊鄰條格式或者板格式的基板602並且經歷流程圖500描述的過程以形成包括一種或複數種自對準特徵的其他半導體封裝件的實施方式，流程圖500可以選擇性地包括用於將這種半導體封裝件的條或者板分離為不同的半導體封裝件的步驟514。半導體封裝件可以以所屬技術領域中具有通常知識者已知的任何合適的方式被分離，以使半導體封裝件彼此物理分開。例如，半導體封裝件可以藉由鋸、刨槽機、雷射器或者根據任何其他分離技術來分離。
III.結論
儘管上面描述了複數個實施方式，但是應當理解的是，它們只是以示例而非限制的方式提出。對所屬技術領域中具有通常知識者顯而易見，在不偏離實施方式的精神和範圍的條件下，可對其中的形式和 細節做出不同的改變。因此，實施方式的寬度及範圍僅受以下權利要求及其等效物的限定而不受上述示例性實施方式限制。
100‧‧‧多芯片模塊
102A‧‧‧第一半導體封裝件
102B‧‧‧第二半導體封裝件
106‧‧‧封裝材料
108、110‧‧‧互連件
112A、112B‧‧‧上表面
114A、114B‧‧‧底表面
116‧‧‧水平面

Claims (10)

  1. 一種多芯片模塊，包括：至少兩個半導體封裝件，前述至少兩個半導體封裝件中的每個包括：基板，具有第一表面和與前述第一表面相對的第二表面；至少一個半導體管芯，耦接至前述基板的前述第一表面；以及第一封裝材料，封裝前述至少一個管芯和前述基板的前述第一表面；以及第二封裝材料，至少部分封裝前述至少兩個半導體封裝件。
  2. 如請求項1所記載之多芯片模塊，其中前述至少兩個半導體封裝件中的每個進一步包括：複數個互連件，耦接至前述基板的前述第二表面，前述複數個互連件藉由前述第二封裝材料被部分封裝。
  3. 如請求項1所記載之多芯片模塊，其中前述至少兩個半導體封裝件中的第一半導體封裝件側向鄰近於前述至少兩個半導體封裝件中的第二半導體封裝件，使得前述第一半導體封裝件的前述基板與前述第二半導體封裝件的前述基板共平面。
  4. 如請求項1所記載之多芯片模塊，其中前述至少兩個半導體封裝件中的至少一個包括複數個管芯。
  5. 如請求項1所記載之多芯片模塊，其中前述至少兩個半導體封裝件中的至少一個包括耦接至前述至少兩個半導體封裝件中的前述至少一個的至少相應的第一表面的屏蔽層。
  6. 如請求項1所記載之多芯片模塊，進一步包括：互連件，耦接前述至少兩個半導體封裝件，前述互連件被前述第二封裝材料封裝。
  7. 一種方法，包括：放置第一半導體封裝件和第二半導體封裝件，使得前述第一半導體封裝件側向鄰近於前述第二半導體封裝件，前述第一半導體封裝件和前述第二半導體封裝件中的每個具有第一表面 和與前述第一表面相對的第二表面，前述第二表面中的每個具有複數個互連件；以及在封裝材料中至少部分封裝前述第一半導體封裝件和前述第二半導體封裝件。
  8. 一種半導體封裝件，包括：基板，具有第一表面和與前述第一表面相對的第二表面；一個或複數個第一互連件，耦接至前述基板的前述第一表面；一個或複數個第二互連件，耦接至前述基板的前述第一表面；以及封裝材料，完全封裝前述一個或複數個第一互連件和前述基板的前述第一表面，並且部分封裝前述一個或複數個第二互連件，使得前述一個或複數個第二互連件藉由前述封裝材料被部分暴露。
  9. 如請求項8所記載之半導體封裝件，其中前述一個或複數個第一互連件經由在前述基板的前述第一表面上形成的絕緣層中的第一組開口耦接至前述基板的前述第一表面，並且前述一個或複數個第二互連件經由形成在前述絕緣層中的第二組開口耦接至前述基板的前述第一表面，其中，前述第一組開口具有第一寬度並且前述第二組開口具有小於前述第一寬度的第二寬度。
  10. 如請求項8所記載之半導體封裝件，其中小於第一寬度的第二寬度使前述一個或複數個第二互連件與前述基板的前述第一表面的間隔距離大於前述一個或複數個第一互連件與前述基板的前述第一表面的間隔距離。
TW104112903A 2014-04-22 2015-04-22 用於半導體封裝件的重構技術 TWI546927B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461982442P 2014-04-22 2014-04-22
US14/263,718 US20150303172A1 (en) 2014-04-22 2014-04-28 Reconstitution techniques for semiconductor packages

Publications (2)

Publication Number Publication Date
TW201543639A true TW201543639A (zh) 2015-11-16
TWI546927B TWI546927B (zh) 2016-08-21

Family

ID=52997173

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104112903A TWI546927B (zh) 2014-04-22 2015-04-22 用於半導體封裝件的重構技術

Country Status (5)

Country Link
US (1) US20150303172A1 (zh)
EP (1) EP2937900A3 (zh)
CN (2) CN204696098U (zh)
HK (1) HK1215894A1 (zh)
TW (1) TWI546927B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI816784B (zh) * 2018-06-26 2023-10-01 南韓商愛思開海力士有限公司 具有電磁帶隙結構的封裝基板和使用此封裝基板的半導體封裝

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613942B2 (en) * 2015-06-08 2017-04-04 Qualcomm Incorporated Interposer for a package-on-package structure
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US10483211B2 (en) 2016-02-22 2019-11-19 Mediatek Inc. Fan-out package structure and method for forming the same
TWI620287B (zh) * 2017-03-21 2018-04-01 矽品精密工業股份有限公司 封裝結構及其製法
CN110462855A (zh) * 2017-03-31 2019-11-15 3M创新有限公司 包括固体半导体管芯的电子装置
US10985109B2 (en) * 2018-12-27 2021-04-20 STATS ChipPAC Pte. Ltd. Shielded semiconductor packages with open terminals and methods of making via two-step process
US20230326821A1 (en) * 2022-04-08 2023-10-12 Nxp B.V. Five-side mold protection for semiconductor packages

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
US6787918B1 (en) * 2000-06-02 2004-09-07 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
JP4996193B2 (ja) * 2006-10-06 2012-08-08 ルネサスエレクトロニクス株式会社 配線基板、半導体パッケージ
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
TWI338941B (en) * 2007-08-22 2011-03-11 Unimicron Technology Corp Semiconductor package structure
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US7618846B1 (en) * 2008-06-16 2009-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the device
US8183678B2 (en) * 2009-08-04 2012-05-22 Amkor Technology Korea, Inc. Semiconductor device having an interposer
FR2953064B1 (fr) * 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
US8497575B2 (en) * 2010-02-22 2013-07-30 Stats Chippac Ltd. Semiconductor packaging system with an aligned interconnect and method of manufacture thereof
JP5590985B2 (ja) * 2010-06-21 2014-09-17 新光電気工業株式会社 半導体装置及びその製造方法
EP2587450B1 (en) * 2011-10-27 2016-08-31 Nordson Corporation Method and apparatus for generating a three-dimensional model of a region of interest using an imaging system
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI816784B (zh) * 2018-06-26 2023-10-01 南韓商愛思開海力士有限公司 具有電磁帶隙結構的封裝基板和使用此封裝基板的半導體封裝

Also Published As

Publication number Publication date
US20150303172A1 (en) 2015-10-22
EP2937900A3 (en) 2016-01-06
HK1215894A1 (zh) 2016-09-23
CN105261595A (zh) 2016-01-20
TWI546927B (zh) 2016-08-21
EP2937900A2 (en) 2015-10-28
CN204696098U (zh) 2015-10-07

Similar Documents

Publication Publication Date Title
TWI546927B (zh) 用於半導體封裝件的重構技術
KR101938949B1 (ko) 패키지 온 패키지 아키텍처 및 그 제조 방법
TWI437683B (zh) 具有穿透本體之傳導通孔的已封裝的積體電路裝置及其製造方法
US9876002B2 (en) Microelectronic package with stacked microelectronic units and method for manufacture thereof
US20070122940A1 (en) Method for packaging a semiconductor device
US9281284B2 (en) System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
TWI553809B (zh) 封裝基板結構
US10242966B1 (en) Thin bonded interposer package
JP2002158312A (ja) ３次元実装用半導体パッケージ、その製造方法、および半導体装置
KR20080053241A (ko) 멀티―칩 패키지 구조 및 그 제조 방법
KR101299852B1 (ko) 비대칭적으로 배열된 다이 및 몰딩을 포함하는 멀티패키지 모듈
US10109572B2 (en) Method for fabricating package structure
KR101478508B1 (ko) 웨이퍼 레벨의 팬 아웃 패키지 및 그 제조 방법
TW201624661A (zh) 封裝結構及其製法
KR100991623B1 (ko) 반도체 디바이스 및 그 제조 방법
KR101653563B1 (ko) 적층형 반도체 패키지 및 이의 제조 방법
US10784224B2 (en) Semiconductor devices with underfill control features, and associated systems and methods
US20140167276A1 (en) Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
US20150348929A1 (en) Package structure and fabrication method thereof
KR101502428B1 (ko) 반도체 패키지 및 이의 제조 방법
TW201330224A (zh) 內嵌封裝體之封裝模組及其製造方法
KR20170124769A (ko) 전자 소자 모듈 및 그 제조 방법
KR101678969B1 (ko) 유전체 부재에 단자를 구비하는 마이크로전자 패키지
JP2014026997A (ja) 半導体装置
KR20150092632A (ko) 반도체 다이 내장 3d 패키지 및 그 제조방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees