TWI437683B - 具有穿透本體之傳導通孔的已封裝的積體電路裝置及其製造方法 - Google Patents

具有穿透本體之傳導通孔的已封裝的積體電路裝置及其製造方法 Download PDF

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TWI437683B
TWI437683B TW97130125A TW97130125A TWI437683B TW I437683 B TWI437683 B TW I437683B TW 97130125 A TW97130125 A TW 97130125A TW 97130125 A TW97130125 A TW 97130125A TW I437683 B TWI437683 B TW I437683B
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sub
integration
integrated circuit
circuit die
conductive
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TW97130125A
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TW200915525A (en
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Tongbi Jiang
Yong Poo Chia
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Micron Technology Inc
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Description

具有穿透本體之傳導通孔的已封裝的積體電路裝置及其製造方法
本文所揭示之此主題大體係針對封裝積體電路裝置之領域，且更特定言之，係針對具有穿透本體之傳導通孔的已封裝的積體電路裝置及其各種製造方法。
積體電路技術使用電裝置(例如，電晶體、電阻器、電容器，等等)以規劃巨大功能電路陣列。此等電路之複雜性要求使用不斷增加之數目的鏈接電裝置，使得電路可執行其所意欲功能。隨著電晶體之數目增加，積體電路尺寸縮小。半導體工業中之一挑戰為開發用於電連接及封裝在相同及/或不同晶圓或晶片上所製造之電路裝置的改良方法。一般而言，在半導體工業中需要建構在矽晶片/晶粒上佔據更小表面面積之電晶體。
在半導體裝置總成之製造中，最通常將單一半導體晶粒併入於每一密封式封裝中。使用許多不同封裝式樣，包括雙列直插式封裝(dual inline package,DIP)、交叉引腳封裝(zig-zag inline package,ZIP)、小型J型彎管(small outline J-bend,SOJ)、薄型小型封裝(thin small outline package,TSOP)、塑膠帶引線晶片載體(plastic leaded chip carrier,PLCC)、小型積體電路(small outline integrated circuit,SOIC)、塑膠四方扁平封裝(plastic quad flat pack,PQFP)及互相交叉引線框(interdigitated leadframe,IDF)。一些半導體裝置總成在密封之前連接至諸如電路板之基板。製造者 經受恆定壓力來減小已封裝的積體電路裝置之尺寸且增加封裝積體電路裝置時之封裝密度。
在一些情況下，已將已封裝的積體電路裝置堆疊於彼此之頂部上，以努力節省標地空間(plot space)。用於將堆疊式已封裝的積體電路裝置彼此傳導地耦接之先前技術通常涉及形成焊球或導線結合以建立此連接。所需要的是用於將堆疊式已封裝的積體電路裝置彼此傳導地耦接之新式且改良之技術。
本文所揭示之此主題大體係針對一種積體電路裝置，其包含：一第一子集成及一第二子集成，其個別地具有一前側及一後側，該等第一子集成及第二子集成之該等後側面向彼此，該等第一子集成及第二子集成個別地具有：一囊封材料；一埋置於該囊封材料中之積體電路晶粒，該積體電路晶粒具有一主動面，該主動面通常齊平於該第一子集成或第二子集成之該前側及埋置於該囊封材料中之一後表面；一傳導線，其在該等個別第一子集成及第二子集成之該前側上及在該積體電路晶粒之該主動面上；一黏著材料，其位於該等第一子集成及第二子集成之該等後側之該囊封材料之間且直接接觸該等第一子集成及第二子集成之該等後側之該囊封材料；及一傳導通孔，其自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前 側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
本文所揭示之此主題大體係針對一種半導體裝置封裝，其包含：一第一半導體結構；一靠近該第一半導體結構之第二半導體結構；一傳導結構，其位於該等第一半導體結構及第二半導體結構兩者之間且直接接觸該等第一半導體結構及第二半導體結構兩者；其中該等個別第一半導體結構及第二半導體結構包括：一第一子集成及一第二子集成，其個別地具有一前側及一後側，該等第一子集成及第二子集成之後側面向彼此，該等第一子集成及第二子集成個別地具有：一囊封材料；一埋置於該囊封材料中之積體電路晶粒，該積體電路晶粒具有一主動面，該主動面通常齊平於該第一子集成或第二子集成之該前側及埋置於該囊封材料中之一後表面；一傳導線，其在該等個別第一子集成及第二子集成之該前側上及在該積體電路晶粒之該主動面上；一黏著材料，其位於該等第一子集成及第二子集成之該等後側之該囊封材料之間且直接接觸該等第一子集成及第二子集成之該等後側之該囊封材料；及一傳導通孔，其自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
本文所揭示之此主題大體係針對一種製造一半導體裝置之方法，其包含：以一第一囊封劑囊封一第一積體電路晶粒至一第一子集成內，該第一子集成具有一第一前側及一第一後側，該第一積體電路晶粒具有一第一主動面，該第一主動面通常齊平於該第一前側及一埋置於該第一囊封劑中之第一後表面；以一第二囊封劑囊封一第二積體電路晶粒至一第二子集成內，該第二子集成具有一第二前側及一第二後側，該第二積體電路晶粒具有一第二主動面，該第二主動面通常齊平於該第二前側及一埋置於該第二囊封劑中之第二後表面；以一黏著材料附著該第一子集成至該第二子集成，該等第一子集成及第二子集成之該等第一後側及第二後側面向彼此；在該等個別第一子集成及第二子集成之該等個別第一前側及第二前側形成一傳導線；及形成一傳導通孔，該傳導通孔自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
可藉由參考以下結合隨附圖式而進行之描述來理解本主題，在隨附圖式中，相同參考數字識別相同元件。
下文描述本主題之說明性實施例。為了清楚起見，本說明書中並未描述實際實施例之所有特徵。當然，應瞭解，在任何此實際實施例之開發中，必須作出眾多實施例特定 決策以達成開發者之特定目標，諸如，順應系統相關及商業相關約束，其將自一實施例至另一實施例變化。此外，應瞭解，此開發努力可能為複雜且耗時的，但對於具有本揭示案之益處的一般熟習此項技術者而言將不過為常規任務。
雖然將圖式所示之各種區域及結構描繪為具有極精確之銳利組態及輪廓，但熟習此項技術者認識到，實際上，此等區域及結構不如圖式中所指示的一樣精確。另外，圖式中所描繪之各種特徵及摻雜區域的相對尺寸與已製造裝置上之該等特徵或區域的尺寸相比可被誇示或減小。然而，包括所附圖式以描述且解釋本文所揭示之主題之說明性實例。
圖1描繪如本文所描述之已封裝的積體電路裝置100之一說明性實施例。已封裝的積體電路裝置100包含積體電路晶粒12，其具有複數個結合襯墊14、傳導線路16(有時被稱為再分配層(RDL))，及延伸穿過囊封材料(例如，封膠材料)本體20之至少一傳導互連18(有時被稱為傳導通孔)。傳導通孔18界定穿過本體20之厚度(亦即，在本體20之前部13與後部15之間)的傳導流動路徑。可使用多種已知技術及結構而將傳導通孔18與積體電路晶粒12彼此傳導地耦接。在所描繪實例中，傳導線路16將傳導通孔18傳導地耦接至積體電路晶粒12。根據已知處理技術而將複數個示意性地描繪之焊球24形成於已封裝的積體電路裝置100上。可使用焊球24或其他類似連接以將已封裝的積體電路裝置 100傳導地耦接至另一結構(例如，印刷電路板)。在圖1中，晶粒12埋置於囊封材料本體20中。如本文中所使用，當據說一或多個晶粒12埋置於囊封材料本體中時，應理解，僅晶粒12之本體之部分需要定位於囊封材料中。不要求囊封材料環繞晶粒12之本體之所有側，但可視特定應用而在需要時使用該組態。
圖2描繪如本文所描述之已封裝的積體電路裝置200之一說明性實施例。已封裝的積體電路裝置200包含埋置於單一囊封材料(例如，封膠材料)本體20中之複數個積體電路晶粒12(展示兩個)。在本文所描繪之說明性實例中，晶粒12中之每一者具有相同實體尺寸。然而，熟習此項技術者在完成閱讀本申請案之後應理解，不要求晶粒12為相同實體尺寸，亦不要求其必須執行相同功能。圖2所示之晶粒12中之每一者具有複數個結合襯墊14、傳導線路16(有時被稱為再分配層(RDL))，及延伸穿過囊封材料本體20之至少一傳導互連18(有時被稱為傳導通孔)。由於裝置200包含複數個積體電路晶粒12，故其可被視作多晶片模組(MCM)。如在圖1中，根據已知處理技術而將複數個示意性地描繪之焊球24形成於已封裝的積體電路裝置200上。可使用焊球24或其他類似連接以將已封裝的積體電路裝置200傳導地耦接至另一結構(例如，印刷電路板)。
在所描繪實施例中，圖2中之傳導通孔18中之每一者延伸穿過本體12之厚度。可使用多種已知技術及結構中之任一者來建立傳導通孔18與埋置式積體電路晶粒12之間的傳 導耦接。在圖2所示之實例中，傳導通孔18中之至少一者藉由一或多個線路16而傳導地耦接至積體電路晶粒12中之一者，而傳導通孔18中之另一者亦藉由一或多個線路16而傳導地耦接至其他積體電路晶粒12。
熟習此項技術者在完成閱讀本申請案之後將認識到，本文所揭示之方法及技術可應用於事實上任何類型之可形成於晶粒12上的積體電路裝置。另外，示意性地描繪之結合襯墊14、傳導線路16及穿透本體之傳導互連18之組態及位置可視特定應用而變化。
圖3至圖5為複數個堆疊式且已封裝的積體電路裝置之示意性橫截面圖。在圖3所描繪之說明性實例中，堆疊式封裝300包含複數個個別埋置式晶粒10A-10D。在圖3所描繪之說明性實例中，僅描繪四個說明性個別埋置式晶粒10A-10D。如上文所闡述，應理解，在參考埋置式晶粒或個別埋置式晶粒時，結構僅需要包含至少一積體電路晶粒，其中晶粒本體之一部分定位於囊封材料本體20中。然而，熟習此項技術者在完成閱讀本申請案之後將認識到，堆疊式封裝300中個別埋置式晶粒10之數目可視特定應用而變化，亦即，此堆疊300內個別埋置式晶粒10之數目可多於或少於圖3所描繪之說明性四個。
圖3中之說明性個別埋置式晶粒10A-10D中之每一者包含積體電路晶粒12、複數個結合襯墊14、傳導線路16(有時被稱為再分配層(RDL))、延伸穿過囊封材料本體20之複數個傳導互連18(有時被稱為傳導通孔)。複數個傳導結構 22提供於鄰近個別埋置式晶粒10之間以在各種埋置式晶粒10A-10D之間提供電傳導路徑。根據已知處理技術而將複數個示意性地描繪之焊球24形成於已封裝的晶粒10D上。可使用焊球24或其他類似連接以將堆疊式封裝300傳導地耦接至另一結構(例如，印刷電路板)。
熟習此項技術者在完成閱讀本申請案之後將認識到，本文所揭示之方法及技術可應用於事實上任何類型之可形成於晶粒12上且封裝於堆疊式組態中的積體電路裝置。另外，圖3所示之示意性地描繪之結合襯墊14、傳導互連18及傳導結構22之組態及位置可視特定應用而變化。在圖3所描繪之實施例中，所有已封裝的晶粒被定向，其中埋置式晶粒10之前側13面向鄰近埋置式晶粒10之後側15。
圖4描繪堆疊式已封裝的裝置400之另一說明性實施例。類似於圖3所示之實施例，圖4中之實施例包含四個說明性個別埋置式晶粒10A-10D。在圖4中，個別埋置式晶粒10A-10D被裝配為群組10E及10F(在將此等群組裝配成圖4所示之結構之前)。第一群組10E包含個別埋置式晶粒10A及10B，而第二群組10F包含個別埋置式晶粒10C及10D。複數個傳導互連或通孔32延伸穿過包含第一群組10E之複數個晶粒10之本體20，而複數個傳導互連或通孔34延伸穿過包含第二群組10F之複數個晶粒10之本體20。
複數個傳導結構22在兩個群組10E與10F之間提供電傳導路徑。每一群組內之個別埋置式晶粒10可使用黏著材料28而彼此固定。注意，在圖4所描繪之說明性實例中，鄰近 埋置式晶粒10之後側15經定位成面向彼此。熟習此項技術者在完成閱讀本申請案之後將認識到，可如圖4所描繪而堆疊之群組(例如，群組10E及10F)之數目可視特定應用而變化，亦即，多於或少於圖4所描繪之說明性兩個群組之群組可被裝配成最終堆疊式封裝400。類似地，每一群組內個別地埋置之晶粒10之數目可大於圖4中所描繪的說明性兩個群組10E及10F。
圖3及圖4所描繪之結構可在必要時進行組合。舉例而言，圖5描繪說明性堆疊式已封裝的裝置500，其中底部兩個埋置式晶粒10A-10B被封裝為群組10E，而上部兩個埋置式晶粒10C-10D如圖3所描繪而被封裝。因此，易於顯而易見的是，本文所揭示之方法及裝置提供極大靈活性，因為其係關於創建堆疊式已封裝的裝置以藉此減小標地空間消耗且改良封裝密度。此外，在圖3至圖5中，個別埋置式晶粒10中之每一者被描繪為具有埋置於其中之單一積體電路晶粒12。根據本揭示案之一態樣，類似於圖2所描繪之多晶片實施例，個別埋置式晶粒10可包含複數個個別積體電路晶粒12。亦即，本文所揭示之方法及裝置可用於包含單一或多個積體電路晶粒12之個別埋置式晶粒10。為了易於參考，以下描述將參考包含單一積體電路晶粒12之個別埋置式晶粒10，但方法可容易地應用於在個別埋置式晶粒之單一囊封材料本體20中埋置複數個積體電路晶粒12。
圖6A至圖6H描繪形成本文所揭示之裝置之一說明性方法。在圖6A中，將複數個已知良好積體電路晶粒12置放成 前側13向下位於說明性犧牲結構30上方。在一說明性實例中，犧牲結構30可為膜框，其中分割帶跨越膜框而定位。結構30在其稍後將被移除之意義上為犧牲的。在圖6B中，將囊封材料(例如，封膠)本體20形成於積體電路晶粒12周圍及結構30上方，亦即，將積體電路晶粒12埋置於本體20中。可執行傳統成形技術(例如，射出成形)以形成囊封材料本體20。其後，如圖6C所示，可移除犧牲結構30。在本文所描述之說明性實例中，歸因於使用黏著帶作為結構30之一部分，結構30可簡單地被剝離。
緊接著，如圖6D所示，根據傳統技術而將傳導線路16形成於積體電路晶粒12及本體12之前側13上方。當然，傳導線路16可具有任何所要組態，且其可由任何所要材料製成。接著，如圖6E所指示，如所指示而將複數個開口或通孔17形成穿過本體20。可藉由多種已知技術(例如，雷射鑽孔、蝕刻，等等)來形成開口17。在一些應用中，作為形成開口17之過程之一部分，可形成遮罩層(未圖示)。開口17可為任何所要形狀或組態。注意，在本文所描繪之說明性實例中，自埋置式晶粒10之本體20之後側15朝向前側13形成開口17。亦注意，在此特定實例中，開口17曝露但不延伸穿過形成於埋置式晶粒10之前側13上之傳導互連16。其後，如圖6F所示，以傳導材料(例如，銅、鋁、銀，等等)來填充開口17以形成傳導互連18。視特定應用而定，可使用多種已知技術(例如，電鍍、沈積，等等)中之任一者而在開口17中形成傳導材料，且可使用多種不同 傳導材料。
在圖6G中，使用已知技術而在埋置式晶粒10A-10B上形成複數個傳導結構22。在一些情況下，作為形成傳導互連18之過程之一部分，可形成傳導結構22。接著，如圖6H所示，沿切割線37而執行分割或單一化過程以產生說明性個別埋置式晶粒10A及10B。
緊接著，使個別埋置式晶粒10A-10B經受多種測試以確認其對於其所意欲應用之可接受性。一旦埋置式晶粒10A-10B已成功地通過該等測試，其即準備好運送至顧客。在其他應用中，經測試之埋置式晶粒10A-10B可被裝配成如本文所描繪之堆疊式已封裝的裝置300、400、500。在圖3所描繪之實例中，如圖3所描繪而定位複數個個別埋置式晶粒10，且執行回焊過程以在個別埋置式晶粒(例如，晶粒10A)上之傳導結構22與鄰近埋置式晶粒(例如，晶粒10B)上之傳導互連18之間建立電連接。可使用傳統技術而在說明性晶粒10上形成說明性焊球24。可在過程流程期間在任何所要點處形成焊球24。舉例而言，可在如圖3所描繪而裝配所有埋置式晶粒10A-10D之後形成焊球24。或者，可在如圖3所描繪而將個別埋置式晶粒10D與其他個別埋置式晶粒進行裝配之前在個別埋置式晶粒10D上方形成焊球24。
圖7A至圖7I描繪形成本文所揭示之裝置之另一說明性方法。圖7A至圖7D所描繪之步驟與先前關於圖6A至圖6D所描述之步驟相同。因此，將不重複圖7A至圖7D之詳細論 述。在圖7E中，使用黏著材料28而將圖7D所描繪之複數個結構彼此固定。其後，在圖7F中，將複數個開口或通孔31形成穿過圖7E所描繪之組合結構之本體20。可藉由多種已知技術(例如，雷射鑽孔、蝕刻，等等)來形成開口31。在一些應用中，作為形成開口31之過程之一部分，可形成遮罩層(未圖示)。開口31可為任何所要形狀或組態。注意，在本文所描繪之說明性實例中，開口31延伸穿過形成於個別結構中之每一者之前側13上的傳導互連16。其後，如圖7G所示，以傳導材料(例如，銅、鋁、銀，等等)來填充開口31以形成穿透本體之傳導通孔32。視特定應用而定，可使用多種已知技術(例如，電鍍、沈積，等等)中之任一者而在開口31中形成傳導材料，且可使用多種不同傳導材料。
在圖7H中，使用已知技術而在圖7G所描繪之結構上形成複數個傳導結構22。在一些情況下，作為形成傳導互連32之過程之一部分，可形成傳導結構22。緊接著，如圖7I所示，沿切割線37而執行分割或單一化過程以產生個別埋置式晶粒之說明性群組10E及10F。
緊接著，使埋置式晶粒群組10E-10F經受多種測試以確認其對於其所意欲應用之可接受性。一旦群組10E-10F已成功地通過該等測試，其即準備好運送至顧客。在一些應用中，可如本文所描述而將埋置式晶粒群組10E-10F裝配成堆疊式已封裝的裝置。在圖4所描繪之實例中，如圖4所描繪而定位埋置式晶粒群組10E及10F，且執行回焊過程以 在第一群組10E上之傳導結構22與鄰近群組10F上之傳導通孔32之間建立電連接。可使用傳統技術而在群組10F中之說明性個別埋置式晶粒上形成說明性焊球24。可在過程流程期間在任何所要點處形成焊球24。舉例而言，可在如圖4所描繪而裝配兩個說明性群組10E-10F之後形成焊球24。或者，可在如圖4所描繪而將兩個群組裝配於一起之前在群組10F中之個別埋置式晶粒中的一者上方形成焊球24。
熟習此項技術者在完成閱讀本申請案之後將認識到，本揭示案可提供用於封裝個別晶粒且提供堆疊式已封裝的積體電路裝置之極有效之方式。可在多個晶粒上單次執行本文所執行之許多處理，其與在個別晶粒上一次一個地執行此等操作相反。舉例而言，儘管圖6A至圖6H及圖7A至圖7I中描繪兩個說明性晶粒12，但視所使用之處理工具之處理能力而定，可在任何所要數目之晶粒上執行本文所描述之處理步驟。簡言之，可使用晶圓級處理技術來增加封裝操作之效率，亦即，可在多個晶粒上同時執行處理操作。
10A‧‧‧個別埋置式晶粒
10B‧‧‧個別埋置式晶粒
10C‧‧‧個別埋置式晶粒
10D‧‧‧個別埋置式晶粒
10E‧‧‧第一群組
10F‧‧‧第二群組
12‧‧‧晶粒
13‧‧‧前部/前側
14‧‧‧結合襯墊
15‧‧‧後部/後側
16‧‧‧傳導線路
17‧‧‧開口或通孔
18‧‧‧傳導互連
20‧‧‧本體
22‧‧‧傳導結構
24‧‧‧焊球
28‧‧‧黏著材料
30‧‧‧犧牲結構
31‧‧‧開口或通孔
32‧‧‧傳導通孔
34‧‧‧傳導互連或通孔
37‧‧‧切割線
100‧‧‧已封裝的積體電路裝置
200‧‧‧已封裝的積體電路裝置
300‧‧‧堆疊式封裝
400‧‧‧堆疊式已封裝的裝置
500‧‧‧堆疊式已封裝的裝置
圖1為如本文所描述之具有複數個傳導穿透本體通孔之說明性已封裝的積體電路晶粒之示意性描繪；圖2為如本文所描述之具有複數個傳導穿透本體通孔之包含多個晶粒之說明性已封裝的積體電路之示意性描繪；圖3為本文所揭示之說明性堆疊式已封裝的裝置之示意性橫截面圖；圖4為本文所揭示之另一說明性堆疊式已封裝的裝置之 示意性橫截面圖；圖5為本文所揭示之又一說明性堆疊式已封裝的裝置之示意性橫截面圖；圖6A至圖6H示意性地描繪形成本文所揭示之堆疊式已封裝的裝置之一說明性方法；且圖7A至圖7I示意性地描繪形成本文所揭示之堆疊式已封裝的裝置之另一說明性方法。
儘管本文所揭示之主題可允許各種修改及替代形式，但其特定實施例已在圖式中以實例加以展示且在本文中加以詳細地描述。然而，應理解，本文中特定實施例之描述不意欲將本發明限制於所揭示之特定形式，而相反，本發明將涵蓋屬於由所附申請專利範圍所界定之本發明之精神及範疇內的所有修改、均等物及替代例。
12‧‧‧晶粒
13‧‧‧前部/前側
14‧‧‧結合襯墊
15‧‧‧後部/後側
16‧‧‧傳導線路
18‧‧‧傳導互連
20‧‧‧本體
24‧‧‧焊球
100‧‧‧已封裝的積體電路裝置

Claims (22)

  1. 一種積體電路裝置，其包含：一第一子集成及一第二子集成，其個別地具有一前側及一後側，該等第一子集成及第二子集成之該等後側面向彼此，該等第一子集成及第二子集成個別地具有：一囊封材料；一埋置於該囊封材料中之積體電路晶粒，該積體電路晶粒具有一主動面，該主動面通常齊平於該第一子集成或第二子集成之該前側及埋置於該囊封材料中之一後表面；一傳導線，其在該等個別第一子集成及第二子集成之該前側上及在該積體電路晶粒之該主動面上；一黏著材料，其位於該等第一子集成及第二子集成之該等後側之該囊封材料之間且直接接觸該等第一子集成及第二子集成之該等後側之該囊封材料；及一傳導通孔，其自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
  2. 如請求項1之積體電路裝置，其中該傳導通孔在該等第一子集成及第二子集成之該等傳導線之間延伸。
  3. 如請求項1之積體電路裝置，其中該第一子集成及該第二子集成垂直地堆疊於彼此上方。
  4. 如請求項1之積體電路裝置，其中該第一子集成中之該積體電路晶粒之該主動面與該第二子集成中之該積體電 路晶粒之該主動面不面向彼此。
  5. 如請求項1之積體電路裝置，其中該等第一子集成及該第二子集成之每一者包含一單一積體電路晶粒。
  6. 如請求項1之積體電路裝置，其中該等第一子集成及該第二子集成之每一者包含複數個積體電路晶粒。
  7. 如請求項1之積體電路裝置，其中該第一子集成中之該積體電路晶粒之該後表面與在該等第一子集成及第二子集成之間之該黏著材料間隔開。
  8. 如請求項1之積體電路裝置，其中該傳導線係連續的。
  9. 一種半導體裝置封裝，其包含：一第一半導體結構；一靠近該第一半導體結構之第二半導體結構；一傳導結構，其位於該等第一半導體結構及第二半導體結構兩者之間且直接接觸該等第一半導體結構及第二半導體結構兩者；其中該等個別第一半導體結構及第二半導體結構包括：一第一子集成及一第二子集成，其個別地具有一前側及一後側，該等第一子集成及第二子集成之後側面向彼此，該等第一子集成及第二子集成個別地具有：一囊封材料；一埋置於該囊封材料中之積體電路晶粒，該積體電路晶粒具有一主動面，該主動面通常齊平於該第一子集成或第二子集成之該前側及埋置於該囊封材料中之一後表 面；一傳導線，其在該等個別第一子集成及第二子集成之該前側上及在該積體電路晶粒之該主動面上；一黏著材料，其位於該等第一子集成及第二子集成之該等後側之該囊封材料之間且直接接觸該等第一子集成及第二子集成之該等後側之該囊封材料；及一傳導通孔，其自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
  10. 如請求項9之半導體裝置封裝，其中該傳導結構係位於(1)該第一半導體結構之該第二子集成之該傳導線及(2)該第二半導體結構之該第一子集成之該傳導線之間且直接接觸(1)該第一半導體結構之該第二子集成之該傳導線及(2)該第二半導體結構之該第一子集成之該傳導線。
  11. 如請求項9之半導體裝置封裝，其中該傳導結構係位於(1)該第一半導體結構之該第二子集成之該傳導線及(2)該第二半導體結構之該第一子集成之該傳導線之間且直接接觸(1)該第一半導體結構之該第二子集成之該傳導線及(2)該第二半導體結構之該第一子集成之該傳導線，且其中該半導體裝置封裝更包括一附著於該第一半導體結構之該第一子集成之該傳導線之焊球。
  12. 如請求項9之半導體裝置封裝，其中該傳導通孔在該等第一半導體結構及第二半導體結構兩者中個別地延伸於該第一子集成之該傳導線及該第二子集成之該傳導線之 間。
  13. 如請求項9之半導體裝置封裝，其中在該等第一半導體結構及第二半導體結構兩者中，該第一子集成中之該積體電路晶粒之該主動面與該第二子集成中之該積體電路晶粒之該主動面不面向彼此。
  14. 如請求項9之半導體裝置封裝，其中在該等個別第一半導體結構及第二半導體結構中，該等第一子集成及第二子集成之每一者包含一單一積體電路晶粒。
  15. 如請求項9之半導體裝置封裝，其中在該等個別第一半導體結構及第二半導體結構中，該等第一子集成及第二子集成之每一者包含複數個積體電路晶粒。
  16. 如請求項9之半導體裝置封裝，其中在該等第一子集成及第二子集成中之該積體電路晶粒之該等後側表面與在該等個別第一半導體結構及第二半導體結構中之該黏著材料係個別地間隔開。
  17. 一種製造一半導體裝置之方法，其包含：以一第一囊封劑囊封一第一積體電路晶粒至一第一子集成內，該第一子集成具有一第一前側及一第一後側，該第一積體電路晶粒具有一第一主動面，該第一主動面通常齊平於該第一前側及一埋置於該第一囊封劑中之第一後表面；以一第二囊封劑囊封一第二積體電路晶粒至一第二子集成內，該第二子集成具有一第二前側及一第二後側，該第二積體電路晶粒具有一第二主動面，該第二主動面 通常齊平於該第二前側及一埋置於該第二囊封劑中之第二後表面；以一黏著材料附著該第一子集成至該第二子集成，該等第一子集成及第二子集成之該等第一後側及第二後側面向彼此；在該等個別第一子集成及第二子集成之該等個別第一前側及第二前側形成一傳導線；及形成一傳導通孔，該傳導通孔自該第一子集成之該前側延伸穿過該黏著材料至該第二子集成之該前側，該傳導通孔係直接接觸該等第一子集成及第二子集成兩者之該等傳導線。
  18. 如請求項17之方法，其中形成該傳導通孔包括在該第一囊封劑、該第二囊封劑及該黏著材料中形成一開口及以一傳導材料填充該開口。
  19. 如請求項17之方法，其中囊封一第一積體電路晶粒及囊封一第二積體電路晶粒包括以一囊封劑囊封該等第一積體電路晶粒及第二積體電路晶粒兩者及單一化該等已囊封之第一積體電路晶粒及第二積體電路晶粒以形成該等第一子集成及第二子集成。
  20. 如請求項17之方法，其中：該方法更包括將該等第一積體電路晶粒及第二積體電路晶粒置放在一具有該等第一主動面及第二主動面之犧牲結構上，該等第一主動面及第二主動面直接接觸該犧牲結構； 囊封一第一積體電路晶粒及囊封一第二積體電路晶粒包括當該等第一積體電路晶粒及第二積體電路晶粒在該犧牲結構上時，以一囊封劑囊封該等第一積體電路晶粒及第二積體電路晶粒兩者；此後自該等第一積體電路晶粒及第二積體電路晶粒移除該犧牲結構，及單一化該等已囊封之第一積體電路晶粒及第二積體電路晶粒以形成該等第一子集成及第二子集成。
  21. 如請求項17之方法，其中：該方法更包括將該等第一積體電路晶粒及第二積體電路晶粒置放在一具有該等第一主動面及第二主動面之犧牲結構上，該等第一主動面及第二主動面直接接觸該犧牲結構，該犧牲結構包括一膜框及一分割帶之至少一者；囊封一第一積體電路晶粒及囊封一第二積體電路晶粒包括當該等第一積體電路晶粒及第二積體電路晶粒在該犧牲結構上時，以一囊封劑囊封該等第一積體電路晶粒及第二積體電路晶粒兩者；此後自該等第一積體電路晶粒及第二積體電路晶粒移除該犧牲結構，及單一化該等已囊封之第一積體電路晶粒及第二積體電路晶粒以形成該等第一子集成及第二子集成。
  22. 如請求項17之方法，其中：該方法更包括將該等第一積體電路晶粒及第二積體電 路晶粒置放在一具有該等第一主動面及第二主動面之犧牲結構上，該等第一主動面及第二主動面直接接觸該犧牲結構；囊封一第一積體電路晶粒及囊封一第二積體電路晶粒包括當該等第一積體電路晶粒及第二積體電路晶粒在該犧牲結構上時，以一囊封劑囊封該等第一積體電路晶粒及第二積體電路晶粒兩者；此後自該等第一積體電路晶粒及第二積體電路晶粒移除該犧牲結構，及單一化該等已囊封之第一積體電路晶粒及第二積體電路晶粒以形成該等第一子集成及第二子集成；形成該傳導通孔包括在該第一囊封劑、該第二囊封劑及該黏著材料中形成一開口及以一傳導材料填充該開口。
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US11594525B2 (en) 2023-02-28
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