US20170374748A1 - Package structure and manufacturing method thereof - Google Patents
Package structure and manufacturing method thereof Download PDFInfo
- Publication number
- US20170374748A1 US20170374748A1 US15/701,435 US201715701435A US2017374748A1 US 20170374748 A1 US20170374748 A1 US 20170374748A1 US 201715701435 A US201715701435 A US 201715701435A US 2017374748 A1 US2017374748 A1 US 2017374748A1
- Authority
- US
- United States
- Prior art keywords
- layer
- resins
- circuit layer
- composite
- sealant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000010410 layer Substances 0.000 claims abstract description 280
- 239000002131 composite material Substances 0.000 claims abstract description 67
- 229910010272 inorganic material Inorganic materials 0.000 claims abstract description 57
- 239000011147 inorganic material Substances 0.000 claims abstract description 57
- 239000011368 organic material Substances 0.000 claims abstract description 57
- 239000000615 nonconductor Substances 0.000 claims abstract description 56
- 239000000565 sealant Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000011241 protective layer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 41
- 229920005989 resin Polymers 0.000 claims description 36
- 239000011347 resin Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 239000002861 polymer material Substances 0.000 claims description 18
- 229910010293 ceramic material Inorganic materials 0.000 claims description 13
- -1 vinyl phenyl Chemical group 0.000 claims description 11
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 10
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 6
- 125000003903 2-propenyl group Chemical group [H]C([*])([H])C([H])=C([H])[H] 0.000 claims description 5
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 5
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 5
- CERQOIWHTDAKMF-UHFFFAOYSA-M Methacrylate Chemical compound CC(=C)C([O-])=O CERQOIWHTDAKMF-UHFFFAOYSA-M 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 5
- 239000004721 Polyphenylene oxide Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 229920000058 polyacrylate Polymers 0.000 claims description 5
- 229920006122 polyamide resin Polymers 0.000 claims description 5
- 229920000570 polyether Polymers 0.000 claims description 5
- 229920005672 polyolefin resin Polymers 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present disclosure relates to a package structure and a manufacturing method thereof.
- one type of semiconductor devices allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate.
- This semiconductor device may desirably reduce the overall size and improve the electrical functionality thereof.
- An aspect of the disclosure is to provide a package structure and a manufacturing method thereof to solve the foregoing problems.
- a package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer.
- the composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer.
- the sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material.
- the chip is embedded in the sealant, and the chip has electrode pads. The electrode pads are exposed from the sealant.
- the circuit layer structure is formed on the sealant and the chip.
- the circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes.
- the circuit layer is located on the dielectric layer and extends into the conductive blind holes.
- the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes.
- the insulating protective layer is formed on the circuit layer structure.
- the insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
- the chip has a chip bottom surface exposed from the sealant.
- the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
- the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
- the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
- the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
- a method of manufacturing package structures includes the following steps: providing a carrier, in which the carrier includes a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers; disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers; bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, in which the chip embedded substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant; forming a circuit layer structure on each of the chip embedded substrates, in which the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrical
- each of the sealant has a sealant bottom surface
- each of the chips has a chip bottom surface.
- the step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material includes the following steps: grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.
- the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
- the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
- the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
- the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
- the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
- the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping, thereby improving not only the process yield, but also the reliability of the package structure.
- FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure according to one embodiment of the disclosure
- FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure according to another embodiment of the disclosure.
- FIG. 3 is a cross-sectional view illustrating the package structure obtained by the manufacturing method according to FIG. 2A to FIG. 2B .
- FIG. 1A to FIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure 18 according to one embodiment of the disclosure.
- a carrier 10 is provided.
- Carrier 10 includes a supporting layer 100 having opposite two surfaces 100 A and 100 B, a release layer 102 disposed on each of the two surfaces 100 A and 100 B, and a metal layer 104 disposed on each of the release layers 102 .
- the material of the supporting layer 100 may be organic polymer material such as bismaleimide triazine (BT).
- supporting layer 100 may be a copper clad laminate (CCL) (not shown) with a dielectric material (such as prepreg) formed on the opposite two surfaces 100 A and 100 B.
- the release layer 102 may be a release film.
- a copper foil bonded with a release layer as provided by companies such as Mitsui, Nippon-Denk, Furukawa or Olin can be used to provide the release layer 102 .
- the thickness of the metal layer 104 is in the range of about 1 ⁇ m to 10 ⁇ m, and the material of the metal layer 104 may be copper.
- additional metal layer may exist between each of the opposite two surfaces 100 A and 100 B of supporting layer 100 and each release layer 102 .
- the thickness of the additional metal layer may be in the range of about 5 ⁇ m to 40 ⁇ m, and the material of the additional metal layer may be the same as or different from that of the metal layer 104 , such as copper.
- a composite layer of a non-conductor inorganic material and an organic material 106 is disposed on each of the metal layers 104 .
- the material of the composite layer of the non-conductor inorganic material and the organic material 106 of this embodiment is a composite material composed of a ceramic material and a polymer material, for example.
- the ceramic material includes zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof
- the polymer material includes epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
- the ceramic material may be ceramic layers or ceramic powders, but the ceramic material of this embodiment is not limited thereto.
- the polymer material can be impregnated in the ceramic powders using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 , so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic powders and the polymer material.
- the polymer material is a photosensitive resin composition including such as an epoxy-based resin and an imide-based resin, for example
- the composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104 by hot pressing or vacuum dipping and then irradiating with ultraviolet light and heating, for example.
- the polymer material can be impregnated in the ceramic layers using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 , so as to manufacture the composite layer of the non-conductor inorganic material and the organic material 106 composed of a composite material formed of the ceramic layers and the polymer material.
- the manufacturing method of the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment is not limited thereto. Other methods capable of forming the composite material from the polymer material and the ceramic material are suitable.
- the composite layer of the non-conductor inorganic material and the organic material 106 includes a composite composition of an organic matter and an inorganic matter (e.g., a composite composition of the polymer material and the ceramic layers).
- the ceramic layers of the composite layer of the non-conductor inorganic material and the organic material 106 has a microscopic laminated structure in a sheet-shape, a brick-shape, or a combination thereof arrangement. The arrangement suppresses the conduction of transverse rupture forces, thereby significantly improving its hardness.
- the material is strong and has flexibility, which is able to increase ceramic strength and improve ceramic brittleness, and with excellent toughness at the same time.
- the composite layer of the non-conductor inorganic material and the organic material 106 may be an imitation nacreous layer.
- a Young's modulus of the composite layer of the non-conductor inorganic material and the organic material 106 is between 20 GPa and 100 GPa, for example.
- the composite layer of the non-conductor inorganic material and the organic material 106 of the embodiment has an excellent hardness, such that a structural strength of the package structure can be effectively enhanced.
- a chip embedded substrate 12 is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106 .
- the chip embedded substrate 12 includes a plurality of chips 120 and a sealant 122 .
- the chips 120 are embedded in the sealant 122 , and each of the chips 120 has a plurality of electrode pads 120 P.
- the electrode pads 120 P are exposed from the sealant 122 .
- an adhesive layer may be used to bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106 .
- the adhesive layer can be adhered to a substrate bottom surface 12 S of the chip embedded substrate 12 first, and then bond the chip embedded substrate 12 on the composite layer of the non-conductor inorganic material and the organic material 106 .
- the adhesive layer can include thermal grease with high heat dissipation or high temperature resistance, but the disclosure is not limited thereto.
- a circuit layer structure 14 is formed on each of the chip embedded substrates 12 .
- the circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer.
- Each dielectric layer has a plurality of conductive blind holes.
- Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes.
- the bottommost circuit layer is electrically connected to the electrode pads 120 P through the conductive blind holes.
- a basic unit of the circuit layer structure 14 is consisted of at least one dielectric layer and at least one circuit layer.
- a person having ordinary skill in the art may make proper modification to the number of layers of the dielectric layer and the circuit layer according to actual needs.
- the circuit layer structure 14 will be specify in the case of including two dielectric layers (first dielectric layer 108 and second dielectric layer 208 ) and two circuit layers (first circuit layer 110 and second circuit layer 210 ) in the following descriptions.
- a first dielectric layer 108 is formed on each of the chip embedded substrates 12 .
- the first dielectric layer 108 has a plurality of first conductive blind holes 108 H.
- the material of the first dielectric layer 108 may include resin and glass fibers.
- the resin may be novolak resin, epoxy resin, polyimide resin, or polytetrafluoroethylene.
- the material of the first dielectric layer 108 may include photo-imageable dielectric (PID).
- the first dielectric layer 108 may be formed by lamination.
- the first conductive blind holes 108 H can be formed by performing a laser ablation process to the first dielectric layer 108 , or using PID as the material of the first dielectric layer 108 so as to form the first conductive blind holes 108 H by photolithography process, but not limited thereto.
- a first circuit layer 110 is formed on each of the first dielectric layers 108 .
- the first circuit layer 110 extends into the first conductive blind holes 108 H, such that the first circuit layer 110 is electrically connected to the electrode pads 120 P through the first conductive blind holes 108 H.
- the first circuit layer 110 may be formed by the following steps: forming a photoresist layer (not shown) such as a dry film on the first dielectric layer 108 ; performing a photolithography process to patterning the photoresist layer, so as to expose parts of the first dielectric layer 108 ; and performing an electroplating process and removing the photoresist layer to form the first circuit layer 110 .
- the material of the first circuit layer 110 may be copper.
- a seed layer may be formed on the first dielectric layer 108 before forming the first circuit layer 110 .
- the seed layer may have a single layer structure or a multi-layer structure consisted of sub-layers having different materials, such as a metal layer consisted of a titanium layer and a copper layer located on the titanium layer.
- the method of forming the seed layer may include, but not limited to, physical methods such as titanium and copper sputtering, or chemical methods such as chemical palladium and copper plating, and copper electroplating.
- a second dielectric layer 208 is formed on each of the first dielectric layers 108 and each of the first circuit layers 110 .
- the second dielectric layer 208 has a plurality of second conductive blind holes 208 H.
- a second circuit layer 210 is formed on each of the second dielectric layers 208 .
- the second circuit layer 210 extends into the second conductive blind holes 208 H, such that the second circuit layer 210 is electrically connected to the first circuit layer 110 through second conductive blind holes 208 H.
- the circuit layer structure 14 is formed on each of the chip embedded substrates 12 .
- the circuit layer structure 14 includes the first dielectric layer 108 , the first circuit layer 110 , the second dielectric layer 208 , and the second circuit layer 210 .
- the first dielectric layer 108 has a plurality of the first conductive blind holes 108 H, and the first circuit layer 110 is electrically connected to the electrode pads 120 P through the first conductive blind holes 108 H.
- the second dielectric layer 208 has a plurality of the second conductive blind holes 208 H, and the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive blind holes 208 H.
- the circuit layer structure 14 includes at least one dielectric layer (first dielectric layer 108 and second dielectric layer 208 ) and at least one circuit layer (first circuit layer 110 and second circuit layer 210 ).
- Each dielectric layer has a plurality of conductive blind holes (first conductive blind holes 108 H and second conductive blind holes 208 H).
- Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes.
- the bottommost circuit layer (first circuit layer 110 ) is electrically connected to the electrode pads 120 P through the conductive blind holes (first conductive blind holes 108 H).
- the second dielectric layer 208 , the second circuit layer 210 , and the second conductive blind holes 208 H may be similar to those of the first dielectric layer 108 , the first circuit layer 110 , and the first conductive blind holes 108 H mentioned above respectively, and therefor they are not to be repeated here again.
- a seed layer may also be formed on the second dielectric layer 208 before forming the second circuit layer 210 as mentioned above, and therefore it is not to be repeated here again.
- FIG. 1E An insulating protective layer 112 is formed on each of the circuit layer structures 14 .
- the insulating protective layer 112 has a plurality of openings 112 O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112 O. Specifically, as shown in FIG. 1E , parts of the surface of the outermost second circuit layer 210 of the circuit layer structure 14 are exposed in the openings 112 O.
- the material of the insulating protective layer 112 may be solder resist material or resin material such as epoxy resin. In other embodiments, the material of the insulating protective layer 112 may also be the same as above-mentioned material of the first dielectric layer 108 or second dielectric layer 208 .
- the insulating protective layer 112 may be formed by laminating, printing, or coating.
- this embodiment provides the same processes on the opposite two surfaces 100 A and 100 B of the supporting layer 100 respectively at the same time to form up-down symmetrical two package substrates 16 , so as to prevent the supporting layer 100 from warping phenomenon, and improve the reliability of the overall package structure.
- each of the package substrates 16 is cut to obtain a plurality of package structures 18 .
- the two package substrates 16 manufactured through FIG. 1A to FIG. 1F can produce 2N package structures 18 , and thereby the process yield can be improved significantly.
- the package structure 18 includes the metal layer 104 , the composite layer of the non-conductor inorganic material and the organic material 106 , the sealant 122 , the chip 120 , the circuit layer structure 14 , and the insulating protective layer 112 .
- the composite layer of the non-conductor inorganic material and the organic material 106 is disposed on the metal layer 104 .
- the sealant 122 is bonded on the composite layer of the non-conductor inorganic material and the organic material 106 .
- the chip 120 is embedded in the sealant 122 .
- the chip 120 has a plurality of electrode pads 120 P, and the electrode pads 120 P are exposed from the sealant 122 .
- the circuit layer structure 14 is formed on the sealant 122 and the chip 120 .
- the circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads 120 P through the conductive blind holes.
- An insulating protective layer 112 is formed on the circuit layer structure 14 .
- the insulating protective layer 112 has a plurality of openings 112 O, so as to expose parts of the surface of the circuit layer structure 14 in the openings 112 O.
- the package substrate 16 is formed on the composite layer of the non-conductor inorganic material and the organic material 106 . That is, the composite layer of the non-conductor inorganic material and the organic material 106 can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
- the overall structural strength of the package structure 18 and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material 106 , so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure 18 .
- the package structure 18 has the metal layer 104 in the bottom, the heat generated by the chip 120 can be dissipated by the metal layer 104 to achieve an effect of heat dissipation.
- FIG. 2A to FIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure 18 A according to another embodiment of the disclosure.
- FIG. 3 is a cross-sectional view illustrating the package structure 18 A obtained by the manufacturing method according to FIG. 2A to FIG. 2B .
- the method of manufacturing package structure 18 A according to this embodiment is similar to the method of manufacturing the package structure 18 as mentioned above, and the difference is that in this embodiment, the step of bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106 further includes the following sub-step: grinding a sealant bottom surface 122 S to expose a chip bottom surface 120 S.
- a sealant bottom surface 122 S is ground to expose a chip bottom surface 120 S, so as to form a ground chip embedded substrate 12 A before bonding the chip embedded substrate 12 on each of the composite layers of the non-conductor inorganic material and the organic material 106 .
- the method of grinding the sealant bottom surface 122 S may be chemical-mechanical polishing (CMP).
- the ground chip embedded substrate 12 A is bonded on each of the composite layers of the non-conductor inorganic material and the organic material 106 . That is, when the ground chip embedded substrate 12 A is bonded on the composite layer of the non-conductor inorganic material and the organic material 106 , the chip bottom surface 120 S is exposed from the sealant 122 .
- an adhesive layer (not shown) may be used herein to bond the ground chip embedded substrate 12 A on each of the composite layers of the non-conductor inorganic material and the organic material 106 as above-mentioned embodiment, and therefore it is not to be repeated here again.
- the package structure 18 A as shown in FIG. 3 is accordingly obtained.
- the chip bottom surface 120 S is exposed from the sealant 122 , the heat generated by the chip 120 can be dissipated by the metal layer 104 more effectively thereby to further improve the effect of heat dissipation.
- the thickness of the package structure 18 A is also reduced, which is beneficial to the miniaturization of products.
- the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material.
- the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
- This application is a continuation-in-part of U.S. application Ser. No. 15/391,861, filed Dec. 28, 2016, now pending, which is a continuation-in-part of U.S. application Ser. No. 14/602,656, filed Jan. 22, 2015, now pending, which is a divisional of U.S. application Ser. No. 13/604,968, filed Sep. 6, 2012, now patented as U.S. Pat. No. 8,946,564. The prior U.S. application Ser. No. 15/391,861 claims priority to Taiwan Application serial number 105133848, filed Oct. 20, 2016. The prior U.S. application Ser. No. 13/604,968 claims priority to Taiwan Application serial number 100139667, filed Oct. 31, 2011. This application also claims priority to Taiwan Application Serial Number 106123710, filed Jul. 14, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- The present disclosure relates to a package structure and a manufacturing method thereof.
- As the technology of semiconductor packaging advances, there have been various types of packages for semiconductor devices developed besides the conventional wire bonding semiconductor packaging technique. For example, one type of semiconductor devices allows a semiconductor chip having an integrated circuit (IC) to be embedded in and electrically integrated with a package substrate. This semiconductor device may desirably reduce the overall size and improve the electrical functionality thereof.
- In order to satisfy the demands of shortening the length of conductive wires, reducing structure thickness, and responding to the trends of high-frequency and miniaturization, a method of processing a chip embedded substrate on a coreless carrier has been developed. However, since the coreless carrier lacks the support of a hard core board, it typically results in an insufficient strength and warpage of the overall structure may easily be caused.
- An aspect of the disclosure is to provide a package structure and a manufacturing method thereof to solve the foregoing problems.
- To achieve the foregoing purpose, according to one embodiment of the disclosure, a package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The electrode pads are exposed from the sealant. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The circuit layer is located on the dielectric layer and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
- In one or more embodiments of the disclosure, the chip has a chip bottom surface exposed from the sealant.
- In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
- In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
- In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
- According to another embodiment of the disclosure, a method of manufacturing package structures includes the following steps: providing a carrier, in which the carrier includes a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers; disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers; bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, in which the chip embedded substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant; forming a circuit layer structure on each of the chip embedded substrates, in which the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; forming an insulating protective layer on each of the circuit layer structures, in which the insulating protective layer has a plurality of openings, so as to expose parts of the surface of the circuit layer structure in the openings; removing the supporting layer and the release layers to form two package substrates; and cutting each of the package substrates to obtain a plurality of package structures.
- In one or more embodiments of the disclosure, each of the sealant has a sealant bottom surface, and each of the chips has a chip bottom surface. The step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material includes the following steps: grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.
- In one or more embodiments of the disclosure, the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
- In one or more embodiments of the disclosure, the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof.
- In one or more embodiments of the disclosure, the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer.
- Based on the above, the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping, thereby improving not only the process yield, but also the reliability of the package structure.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
- The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
-
FIG. 1A toFIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of a package structure according to one embodiment of the disclosure; -
FIG. 2A toFIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of a package structure according to another embodiment of the disclosure; and -
FIG. 3 is a cross-sectional view illustrating the package structure obtained by the manufacturing method according toFIG. 2A toFIG. 2B . - Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1A toFIG. 1G are cross-sectional views illustrating the steps in a manufacturing method of apackage structure 18 according to one embodiment of the disclosure. As shown inFIG. 1A , a carrier 10 is provided. Carrier 10 includes a supportinglayer 100 having opposite twosurfaces release layer 102 disposed on each of the twosurfaces metal layer 104 disposed on each of the release layers 102. In some embodiments, the material of the supportinglayer 100 may be organic polymer material such as bismaleimide triazine (BT). In some embodiments, supportinglayer 100 may be a copper clad laminate (CCL) (not shown) with a dielectric material (such as prepreg) formed on the opposite twosurfaces release layer 102 may be a release film. In other embodiments, a copper foil bonded with a release layer as provided by companies such as Mitsui, Nippon-Denk, Furukawa or Olin can be used to provide therelease layer 102. In some embodiments, the thickness of themetal layer 104 is in the range of about 1 μm to 10 μm, and the material of themetal layer 104 may be copper. - In some embodiments, additional metal layer may exist between each of the opposite two
surfaces layer 100 and eachrelease layer 102. The thickness of the additional metal layer may be in the range of about 5 μm to 40 μm, and the material of the additional metal layer may be the same as or different from that of themetal layer 104, such as copper. - As shown in
FIG. 1B , a composite layer of a non-conductor inorganic material and anorganic material 106 is disposed on each of the metal layers 104. - For example, the material of the composite layer of the non-conductor inorganic material and the
organic material 106 of this embodiment is a composite material composed of a ceramic material and a polymer material, for example. The ceramic material includes zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material includes epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof. The ceramic material may be ceramic layers or ceramic powders, but the ceramic material of this embodiment is not limited thereto. - In the embodiment of the ceramic powders, the polymer material can be impregnated in the ceramic powders using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the
organic material 106, so as to manufacture the composite layer of the non-conductor inorganic material and theorganic material 106 composed of a composite material formed of the ceramic powders and the polymer material. In the embodiment that the polymer material is a photosensitive resin composition including such as an epoxy-based resin and an imide-based resin, for example, the composite layer of the non-conductor inorganic material and theorganic material 106 is disposed on themetal layer 104 by hot pressing or vacuum dipping and then irradiating with ultraviolet light and heating, for example. - In the embodiment of the ceramic layers, the polymer material can be impregnated in the ceramic layers using a vacuum dipping technique in the manufacturing method of the composite layer of the non-conductor inorganic material and the
organic material 106, so as to manufacture the composite layer of the non-conductor inorganic material and theorganic material 106 composed of a composite material formed of the ceramic layers and the polymer material. However, the manufacturing method of the composite layer of the non-conductor inorganic material and theorganic material 106 of the embodiment is not limited thereto. Other methods capable of forming the composite material from the polymer material and the ceramic material are suitable. In the embodiment of the ceramic layers, more specifically, the composite layer of the non-conductor inorganic material and theorganic material 106 includes a composite composition of an organic matter and an inorganic matter (e.g., a composite composition of the polymer material and the ceramic layers). Based on the adhesion of the organic matter to the inorganic matter, the ceramic layers of the composite layer of the non-conductor inorganic material and theorganic material 106 has a microscopic laminated structure in a sheet-shape, a brick-shape, or a combination thereof arrangement. The arrangement suppresses the conduction of transverse rupture forces, thereby significantly improving its hardness. Therefore, the material is strong and has flexibility, which is able to increase ceramic strength and improve ceramic brittleness, and with excellent toughness at the same time. The composite layer of the non-conductor inorganic material and theorganic material 106 may be an imitation nacreous layer. - In some embodiments, a Young's modulus of the composite layer of the non-conductor inorganic material and the
organic material 106 is between 20 GPa and 100 GPa, for example. Compared with a commonly used dielectric layer (with a Young's modulus not more than 10 GPa) and an encapsulating material (with a Young's modulus not more than 20 GPa), the composite layer of the non-conductor inorganic material and theorganic material 106 of the embodiment has an excellent hardness, such that a structural strength of the package structure can be effectively enhanced. - As shown in
FIG. 1C , a chip embeddedsubstrate 12 is bonded on each of the composite layers of the non-conductor inorganic material and theorganic material 106. The chip embeddedsubstrate 12 includes a plurality ofchips 120 and asealant 122. Thechips 120 are embedded in thesealant 122, and each of thechips 120 has a plurality ofelectrode pads 120P. Theelectrode pads 120P are exposed from thesealant 122. - In some embodiments, an adhesive layer (not shown) may be used to bond the chip embedded
substrate 12 on the composite layer of the non-conductor inorganic material and theorganic material 106. Specifically, the adhesive layer can be adhered to asubstrate bottom surface 12S of the chip embeddedsubstrate 12 first, and then bond the chip embeddedsubstrate 12 on the composite layer of the non-conductor inorganic material and theorganic material 106. The adhesive layer can include thermal grease with high heat dissipation or high temperature resistance, but the disclosure is not limited thereto. - As shown in
FIG. 1D toFIG. 1E , acircuit layer structure 14 is formed on each of the chip embeddedsubstrates 12. Thecircuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to theelectrode pads 120P through the conductive blind holes. - A basic unit of the
circuit layer structure 14 is consisted of at least one dielectric layer and at least one circuit layer. A person having ordinary skill in the art may make proper modification to the number of layers of the dielectric layer and the circuit layer according to actual needs. In this embodiment, thecircuit layer structure 14 will be specify in the case of including two dielectric layers (firstdielectric layer 108 and second dielectric layer 208) and two circuit layers (first circuit layer 110 and second circuit layer 210) in the following descriptions. - As shown in
FIG. 1D , a firstdielectric layer 108 is formed on each of the chip embeddedsubstrates 12. Thefirst dielectric layer 108 has a plurality of first conductiveblind holes 108H. In some embodiments, the material of thefirst dielectric layer 108 may include resin and glass fibers. The resin may be novolak resin, epoxy resin, polyimide resin, or polytetrafluoroethylene. In other embodiments, the material of thefirst dielectric layer 108 may include photo-imageable dielectric (PID). In some embodiments, thefirst dielectric layer 108 may be formed by lamination. In some embodiments, the first conductiveblind holes 108H can be formed by performing a laser ablation process to thefirst dielectric layer 108, or using PID as the material of thefirst dielectric layer 108 so as to form the first conductiveblind holes 108H by photolithography process, but not limited thereto. - Please continue to refer to
FIG. 1D . Afirst circuit layer 110 is formed on each of the first dielectric layers 108. Thefirst circuit layer 110 extends into the first conductiveblind holes 108H, such that thefirst circuit layer 110 is electrically connected to theelectrode pads 120P through the first conductiveblind holes 108H. In some embodiments, thefirst circuit layer 110 may be formed by the following steps: forming a photoresist layer (not shown) such as a dry film on thefirst dielectric layer 108; performing a photolithography process to patterning the photoresist layer, so as to expose parts of thefirst dielectric layer 108; and performing an electroplating process and removing the photoresist layer to form thefirst circuit layer 110. In some embodiment, the material of thefirst circuit layer 110 may be copper. - In some embodiment, a seed layer may be formed on the
first dielectric layer 108 before forming thefirst circuit layer 110. The seed layer may have a single layer structure or a multi-layer structure consisted of sub-layers having different materials, such as a metal layer consisted of a titanium layer and a copper layer located on the titanium layer. The method of forming the seed layer may include, but not limited to, physical methods such as titanium and copper sputtering, or chemical methods such as chemical palladium and copper plating, and copper electroplating. - As shown in
FIG. 1E , asecond dielectric layer 208 is formed on each of the firstdielectric layers 108 and each of the first circuit layers 110. Thesecond dielectric layer 208 has a plurality of second conductiveblind holes 208H. Asecond circuit layer 210 is formed on each of the second dielectric layers 208. Thesecond circuit layer 210 extends into the second conductiveblind holes 208H, such that thesecond circuit layer 210 is electrically connected to thefirst circuit layer 110 through second conductiveblind holes 208H. - Accordingly, the
circuit layer structure 14 is formed on each of the chip embeddedsubstrates 12. Thecircuit layer structure 14 includes thefirst dielectric layer 108, thefirst circuit layer 110, thesecond dielectric layer 208, and thesecond circuit layer 210. Thefirst dielectric layer 108 has a plurality of the first conductiveblind holes 108H, and thefirst circuit layer 110 is electrically connected to theelectrode pads 120P through the first conductiveblind holes 108H. Thesecond dielectric layer 208 has a plurality of the second conductiveblind holes 208H, and thesecond circuit layer 210 is electrically connected to thefirst circuit layer 110 through the second conductiveblind holes 208H. That is, thecircuit layer structure 14 includes at least one dielectric layer (firstdielectric layer 108 and second dielectric layer 208) and at least one circuit layer (first circuit layer 110 and second circuit layer 210). Each dielectric layer has a plurality of conductive blind holes (first conductiveblind holes 108H and second conductiveblind holes 208H). Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer (first circuit layer 110) is electrically connected to theelectrode pads 120P through the conductive blind holes (first conductiveblind holes 108H). - Details about the forming methods and the materials of the
second dielectric layer 208, thesecond circuit layer 210, and the second conductiveblind holes 208H may be similar to those of thefirst dielectric layer 108, thefirst circuit layer 110, and the first conductiveblind holes 108H mentioned above respectively, and therefor they are not to be repeated here again. Moreover, a seed layer may also be formed on thesecond dielectric layer 208 before forming thesecond circuit layer 210 as mentioned above, and therefore it is not to be repeated here again. - Reference is made to
FIG. 1E . An insulatingprotective layer 112 is formed on each of thecircuit layer structures 14. The insulatingprotective layer 112 has a plurality of openings 112O, so as to expose parts of the surface of thecircuit layer structure 14 in the openings 112O. Specifically, as shown inFIG. 1E , parts of the surface of the outermostsecond circuit layer 210 of thecircuit layer structure 14 are exposed in the openings 112O. - In some embodiments, the material of the insulating
protective layer 112 may be solder resist material or resin material such as epoxy resin. In other embodiments, the material of the insulatingprotective layer 112 may also be the same as above-mentioned material of thefirst dielectric layer 108 or seconddielectric layer 208. The insulatingprotective layer 112 may be formed by laminating, printing, or coating. - As shown on
FIG. 1F , the supportinglayer 100 and the release layers 102 are removed to form twopackage substrates 16. Therefore, compared to conventional one-side manufacturing method, which easily causes the warpage because of its structural asymmetry, this embodiment provides the same processes on the opposite twosurfaces layer 100 respectively at the same time to form up-down symmetrical twopackage substrates 16, so as to prevent the supportinglayer 100 from warping phenomenon, and improve the reliability of the overall package structure. - Lastly, as shown in
FIG. 1G , each of the package substrates 16 is cut to obtain a plurality ofpackage structures 18. Thus, if eachpackage substrate 16 can produceN package structures 18, the twopackage substrates 16 manufactured throughFIG. 1A toFIG. 1F can produce2N package structures 18, and thereby the process yield can be improved significantly. - Accordingly, the
package structure 18 according to this embodiment is obtained. Thepackage structure 18 includes themetal layer 104, the composite layer of the non-conductor inorganic material and theorganic material 106, thesealant 122, thechip 120, thecircuit layer structure 14, and the insulatingprotective layer 112. The composite layer of the non-conductor inorganic material and theorganic material 106 is disposed on themetal layer 104. Thesealant 122 is bonded on the composite layer of the non-conductor inorganic material and theorganic material 106. Thechip 120 is embedded in thesealant 122. Thechip 120 has a plurality ofelectrode pads 120P, and theelectrode pads 120P are exposed from thesealant 122. Thecircuit layer structure 14 is formed on thesealant 122 and thechip 120. Thecircuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. Each dielectric layer has a plurality of conductive blind holes. Each circuit layer is located on each dielectric layer respectively, and extends into the conductive blind holes. The bottommost circuit layer is electrically connected to theelectrode pads 120P through the conductive blind holes. An insulatingprotective layer 112 is formed on thecircuit layer structure 14. The insulatingprotective layer 112 has a plurality of openings 112O, so as to expose parts of the surface of thecircuit layer structure 14 in the openings 112O. - According to the
package structure 18 and the manufacturing method thereof provided in the disclosure, thepackage substrate 16 is formed on the composite layer of the non-conductor inorganic material and theorganic material 106. That is, the composite layer of the non-conductor inorganic material and theorganic material 106 can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of thepackage structure 18 and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and theorganic material 106, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of thepackage structure 18. - Moreover, since the
package structure 18 has themetal layer 104 in the bottom, the heat generated by thechip 120 can be dissipated by themetal layer 104 to achieve an effect of heat dissipation. -
FIG. 2A toFIG. 2B are cross-sectional views illustrating some steps in a manufacturing method of apackage structure 18A according to another embodiment of the disclosure.FIG. 3 is a cross-sectional view illustrating thepackage structure 18A obtained by the manufacturing method according toFIG. 2A toFIG. 2B . The method ofmanufacturing package structure 18A according to this embodiment is similar to the method of manufacturing thepackage structure 18 as mentioned above, and the difference is that in this embodiment, the step of bonding the chip embeddedsubstrate 12 on each of the composite layers of the non-conductor inorganic material and theorganic material 106 further includes the following sub-step: grinding asealant bottom surface 122S to expose achip bottom surface 120S. - Please refer to
FIG. 2A andFIG. 1C at the same time. The difference between this embodiment and the step shown inFIG. 1C is that asealant bottom surface 122S is ground to expose achip bottom surface 120S, so as to form a ground chip embeddedsubstrate 12A before bonding the chip embeddedsubstrate 12 on each of the composite layers of the non-conductor inorganic material and theorganic material 106. In some embodiment, the method of grinding thesealant bottom surface 122S may be chemical-mechanical polishing (CMP). - As shown in
FIG. 2B , the ground chip embeddedsubstrate 12A is bonded on each of the composite layers of the non-conductor inorganic material and theorganic material 106. That is, when the ground chip embeddedsubstrate 12A is bonded on the composite layer of the non-conductor inorganic material and theorganic material 106, thechip bottom surface 120S is exposed from thesealant 122. - In some embodiments, an adhesive layer (not shown) may be used herein to bond the ground chip embedded
substrate 12A on each of the composite layers of the non-conductor inorganic material and theorganic material 106 as above-mentioned embodiment, and therefore it is not to be repeated here again. - Then, continue the steps in
FIG. 1D toFIG. 1G , and thepackage structure 18A as shown inFIG. 3 is accordingly obtained. In this embodiment, since thechip bottom surface 120S is exposed from thesealant 122, the heat generated by thechip 120 can be dissipated by themetal layer 104 more effectively thereby to further improve the effect of heat dissipation. Moreover, the thickness of thepackage structure 18A is also reduced, which is beneficial to the miniaturization of products. - According to the foregoing recitations of the embodiments of the disclosure, it can be seen that the package structure and the manufacturing method thereof of the disclosure form the package substrate on the composite layer of the non-conductor inorganic material and the organic material. That is, the composite layer of the non-conductor inorganic material and the organic material can be regarded as a strengthened layer, which has a higher hardness compared with a normal dielectric layer and encapsulating material. Thus, the overall structural strength of the package structure and the manufacturing method thereof of the disclosure can be enhanced through the composite layer of the non-conductor inorganic material and the organic material, so as to prevent the carrier from warping phenomenon, thereby improving not only the process yield, but also the reliability of the package structure.
- Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
Claims (10)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/701,435 US20170374748A1 (en) | 2011-10-31 | 2017-09-11 | Package structure and manufacturing method thereof |
US16/379,816 US11445617B2 (en) | 2011-10-31 | 2019-04-10 | Package structure and manufacturing method thereof |
US16/672,512 US20200068721A1 (en) | 2011-10-31 | 2019-11-03 | Package structure and manufacturing method thereof |
US17/194,323 US11895780B2 (en) | 2011-10-31 | 2021-03-08 | Manufacturing method of package structure |
US17/818,006 US20220375919A1 (en) | 2011-10-31 | 2022-08-08 | Manufacturing method of package structure |
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100139667 | 2011-10-31 | ||
TW100139667A TWI476888B (en) | 2011-10-31 | 2011-10-31 | Package substrate having embedded via hole medium layer and fabrication method thereof |
US13/604,968 US8946564B2 (en) | 2011-10-31 | 2012-09-06 | Packaging substrate having embedded through-via interposer and method of fabricating the same |
US14/602,656 US9781843B2 (en) | 2011-10-31 | 2015-01-22 | Method of fabricating packaging substrate having embedded through-via interposer |
TW105133848 | 2016-10-20 | ||
TW105133848A TWI637663B (en) | 2016-10-20 | 2016-10-20 | Circuit board and manufacturing method thereof |
US15/391,861 US11127664B2 (en) | 2011-10-31 | 2016-12-28 | Circuit board and manufacturing method thereof |
TW103123710 | 2017-07-14 | ||
US15/701,435 US20170374748A1 (en) | 2011-10-31 | 2017-09-11 | Package structure and manufacturing method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/391,861 Continuation-In-Part US11127664B2 (en) | 2011-10-31 | 2016-12-28 | Circuit board and manufacturing method thereof |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/379,816 Continuation-In-Part US11445617B2 (en) | 2011-10-31 | 2019-04-10 | Package structure and manufacturing method thereof |
US16/672,512 Continuation-In-Part US20200068721A1 (en) | 2011-10-31 | 2019-11-03 | Package structure and manufacturing method thereof |
US17/194,323 Division US11895780B2 (en) | 2011-10-31 | 2021-03-08 | Manufacturing method of package structure |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170374748A1 true US20170374748A1 (en) | 2017-12-28 |
Family
ID=60675125
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/701,435 Abandoned US20170374748A1 (en) | 2011-10-31 | 2017-09-11 | Package structure and manufacturing method thereof |
US17/194,323 Active 2033-09-09 US11895780B2 (en) | 2011-10-31 | 2021-03-08 | Manufacturing method of package structure |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/194,323 Active 2033-09-09 US11895780B2 (en) | 2011-10-31 | 2021-03-08 | Manufacturing method of package structure |
Country Status (1)
Country | Link |
---|---|
US (2) | US20170374748A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200163223A1 (en) * | 2018-11-20 | 2020-05-21 | AT&S (Chongqing) Company Limited | Method of Manufacturing a Component Carrier Using a Separation Component, the Component Carrier, and a Semifinished Product |
US10930525B2 (en) * | 2018-11-08 | 2021-02-23 | Samsung Electronics Co., Ltd. | Carrier substrate and method of manufacturing semiconductor package using the carrier substrate |
US20220272828A1 (en) * | 2021-02-10 | 2022-08-25 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Heat Removal Architecture for Stack-Type Component Carrier With Embedded Component |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080151518A1 (en) * | 2006-12-22 | 2008-06-26 | Phoenix Precision Technology Corporation | Circuit board structure with embedded electronic components |
US20090301766A1 (en) * | 2008-06-04 | 2009-12-10 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including electronic component embedded therein and method of manufacturing the same |
US20090324658A1 (en) * | 2006-06-28 | 2009-12-31 | Hakuto Co., Ltd. | Cosmetic and Method for Production Thereof |
US20110157775A1 (en) * | 2009-12-30 | 2011-06-30 | Industrial Technology Research Institute | Decoupling device |
US20120227627A1 (en) * | 2011-03-11 | 2012-09-13 | Cqv Co., Ltd. | Nacreous pigment with high chroma and multiple colors and method of preparing the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2263792A (en) | 1936-07-28 | 1941-11-25 | Button Corp Of America | Molded article and method of producing same |
US3681374A (en) | 1970-08-11 | 1972-08-01 | Asahi Chemical Ind | Synthetic nacreous triazole crystals and method for production thereof |
TWI263313B (en) | 2005-08-15 | 2006-10-01 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board |
TWI276192B (en) | 2005-10-18 | 2007-03-11 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board and method for fabricating the same |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
KR20100068281A (en) | 2007-10-16 | 2010-06-22 | 스미토모 베이클리트 컴퍼니 리미티드 | Substrate with semiconductor element mounted thereon |
TWI393233B (en) * | 2009-08-18 | 2013-04-11 | Unimicron Technology Corp | Coreless package substrate and method of forming the same |
JP5427305B1 (en) | 2013-02-19 | 2014-02-26 | 株式会社フジクラ | Component-embedded substrate, manufacturing method thereof, and mounting body |
JP2016213372A (en) * | 2015-05-12 | 2016-12-15 | 日立化成株式会社 | Semiconductor device and method of manufacturing the same |
-
2017
- 2017-09-11 US US15/701,435 patent/US20170374748A1/en not_active Abandoned
-
2021
- 2021-03-08 US US17/194,323 patent/US11895780B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090324658A1 (en) * | 2006-06-28 | 2009-12-31 | Hakuto Co., Ltd. | Cosmetic and Method for Production Thereof |
US20080151518A1 (en) * | 2006-12-22 | 2008-06-26 | Phoenix Precision Technology Corporation | Circuit board structure with embedded electronic components |
US20090301766A1 (en) * | 2008-06-04 | 2009-12-10 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board including electronic component embedded therein and method of manufacturing the same |
US20110157775A1 (en) * | 2009-12-30 | 2011-06-30 | Industrial Technology Research Institute | Decoupling device |
US20120227627A1 (en) * | 2011-03-11 | 2012-09-13 | Cqv Co., Ltd. | Nacreous pigment with high chroma and multiple colors and method of preparing the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10930525B2 (en) * | 2018-11-08 | 2021-02-23 | Samsung Electronics Co., Ltd. | Carrier substrate and method of manufacturing semiconductor package using the carrier substrate |
US20200163223A1 (en) * | 2018-11-20 | 2020-05-21 | AT&S (Chongqing) Company Limited | Method of Manufacturing a Component Carrier Using a Separation Component, the Component Carrier, and a Semifinished Product |
US20220272828A1 (en) * | 2021-02-10 | 2022-08-25 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Heat Removal Architecture for Stack-Type Component Carrier With Embedded Component |
Also Published As
Publication number | Publication date |
---|---|
US20210195761A1 (en) | 2021-06-24 |
US11895780B2 (en) | 2024-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11895780B2 (en) | Manufacturing method of package structure | |
US8975150B2 (en) | Semiconductor device manufacturing method | |
US11127664B2 (en) | Circuit board and manufacturing method thereof | |
US10880988B2 (en) | Highly thermally conductive dielectric structure for heat spreading in component carrier | |
US8704100B2 (en) | Heat dissipating substrate and method of manufacturing the same | |
TWI670814B (en) | Single layer coreless substrate | |
US7663249B2 (en) | Embedded chip package structure | |
TW201301466A (en) | Bumpless build-up layer package warpage reduction | |
JP2006173605A (en) | Packaged electronic device and its manufacturing method | |
US20220375919A1 (en) | Manufacturing method of package structure | |
US11160165B2 (en) | Component carrier with through hole extending through multiple dielectric layers | |
US20060193108A1 (en) | Circuit device and manufacturing method thereof | |
US10978417B2 (en) | Wiring structure and method for manufacturing the same | |
TWI621224B (en) | Package structure and manufacturing method thereof | |
JP3841079B2 (en) | Wiring substrate, semiconductor package, substrate insulating film, and method of manufacturing wiring substrate | |
US10897823B2 (en) | Circuit board, package structure and method of manufacturing the same | |
TWI663693B (en) | Package structure and manufacturing method thereof | |
CN109273426B (en) | Package structure and method for manufacturing the same | |
JP5411174B2 (en) | Circuit board and manufacturing method thereof | |
JP2011146545A (en) | Method of manufacturing wiring board | |
KR20150043135A (en) | printed circuit board which includes metal layer and semiconductor package including the same | |
JP4457943B2 (en) | Wiring board and method for manufacturing wiring board | |
JP2007116198A (en) | Semiconductor device | |
US20200068721A1 (en) | Package structure and manufacturing method thereof | |
TWI713185B (en) | Package structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNIMICRON TECHNOLOGY CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, KAI-MING;LIN, CHEN-HAO;TSAI, WANG-HSIANG;AND OTHERS;REEL/FRAME:043566/0655 Effective date: 20170904 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |