CN110034106A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN110034106A
CN110034106A CN201811423753.8A CN201811423753A CN110034106A CN 110034106 A CN110034106 A CN 110034106A CN 201811423753 A CN201811423753 A CN 201811423753A CN 110034106 A CN110034106 A CN 110034106A
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China
Prior art keywords
crystal grain
link block
line structure
conductive
protective layer
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CN201811423753.8A
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CN110034106B (zh
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张简上煜
徐宏欣
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种封装结构包括重布线路结构、晶粒、至少一连接模块、第一绝缘密封体、堆叠晶片以及第二绝缘密封体。晶粒配置并电性连接至重布线路结构。连接模块配置于重布线路结构上。连接模块具有保护层以及多个导电条。多个导电条嵌入保护层中。保护层包括对应于多个导电条的多个开口。第一绝缘密封体密封晶粒与连接模块。堆叠晶片配置于第一绝缘密封体与晶粒上。堆叠晶片电性连接至连接模块。第二绝缘密封体密封堆叠晶片。另提供一种封装结构的制造方法。

Description

封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，尤其涉及一种具有连接模块(connecting module)的封装结构及其制造方法。
背景技术
在近年来的半导体封装技术的研究中已经开始关注于发展具有小体积、重量轻、高密度以及低制造成本的产品。对于多功能半导体封装而言，已经使用一种用于堆叠晶片的技术，以提供封装具有较大的存储或执行数据的容量。在对具有改进期望特征的多功能电子元件的需求快速增加下，实为本领域的技术人员的一大挑战。
发明内容
本发明提供一种封装结构及其制造方法，可以在较低的制造成本下有效地减少封装结构的高度。
本发明的封装结构包括重布线路结构、晶粒、至少一连接模块、第一绝缘密封体、堆叠晶片以及第二绝缘密封体。晶粒配置并电性连接至重布线路结构。连接模块配置于重布线路结构上。连接模块具有保护层以及多个导电条。多个导电条嵌入保护层中。保护层包括对应于多个导电条的多个开口。第一绝缘密封体密封晶粒与连接模块。堆叠晶片配置于第一绝缘密封体与晶粒上。堆叠晶片电性连接至连接模块。第二绝缘密封体密封堆叠晶片。
在本发明的一实施例中，前述的封装结构还包括底胶，配置于重布线路结构与晶粒之间。
本发明提供一种封装结构的制造方法。制造方法至少包括以下步骤。提供载板。形成重布线路结构于载板上。配置多个晶粒以及多个连接模块于重布线路结构上。每一连接模块具有保护层以及嵌入保护层的多个导电条。形成第一绝缘密封体，以密封多个晶粒与多个连接模块。从重布线路结构上移除载板。形成多个开口于多个连接模块的保护层中。多个开口对应至多个导电条。配置堆叠晶片于多个晶粒与相对于重布线路结构的第一绝缘密封体上。堆叠晶片电性连接至多个连接模块。通过第二绝缘密封体密封堆叠晶片。
在本发明的一实施例中，前述的制造方法还包括形成多个导电端子于相对于多个晶粒与多个连接模块的重布线路结构上。
在本发明的一实施例中，前述的制造方法还包括执行切割制程。
在本发明的一实施例中，前述的制造方法还包括形成底胶于重布线路结构与多个晶粒之间。
基于上述，容易预先制造的连接模块可以作为封装结构内的垂直连接特征。由于连接模块的厚度小，进而可以有效地缩小封装结构的尺寸。此外，连接模块的使用可以导致在传统封装结构中免除额外的载板或较厚的铜柱，进而降低制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1K是依据本发明一些实施例的封装结构的制造方法的剖面示意图。
图2A至图2D是图1C中的连接模块依据本发明各种实施例的上视示意图。
图3是依据本发明一些替代实施例的封装结构的剖面示意图。
附图标记说明：
10、20：封装结构；
100：载板；
102：离型层；
200：重布线路结构；
202：介电层；
204：导电图案；
206：导通孔；
300：晶粒；
300a：主动面；
300b：背面；
302：半导体基板；
304：导电接垫；
306：钝化层；
308：导电连接器；
308a：导电栓塞；
308b、510：导电凸块；
400：底胶；
500：连接模块；
502：导电条；
504：阻障层；
506：导电帽；
508：保护层；
508a、610a、910a：顶面；
610：第一绝缘密封体；
612：绝缘材料；
620：第二绝缘密封体；
710：堆叠晶片；
720：导线；
800：导电端子；
910：虚设晶粒；
920：黏着层；
C：空穴；
L：长度；
OP1、OP2：开口；
W：宽度。
具体实施方式
下文将会附加标号以对本发明较佳实施例进行详细描述，并以附图说明。在可能的情况下，相同或相似的构件在附图中将以相同的标号显示。
图1A至图1K是依据本发明一些实施例的封装结构10的制造方法的剖面示意图。请参照图1A，提供具有离型层102形成于其上的载板100。载板100可以是玻璃基板或玻璃支撑板。然而，本发明不限于此。其他合适的基板材料也可以被使用，只要所述材料能够承载在其之上所形成的封装结构且能够承受后续的制程即可。离型层102可以包括光热转换(light to heat conversion,LTHC)材料、环氧树脂(epoxy resin)、无机材料、有机聚合物材料或其他适宜的黏着材料。然而，本发明不限于此。在一些替代实施例中，可以使用其他适宜的离型层。
请参照图1B，于载板100上形成重布线路结构200。重布线路结构200可以包括至少一介电层202、多个导电图案204以及多个导通孔206。可以通过适宜的制造技术如旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition,CVD)、电浆辅助化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)或其他类似者，以形成介电层202。介电层202可以由氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)或其他类似者等的非有机或有机介电材料所制成。可以通过溅镀、蒸镀、化学镀(electro-less plating)或电镀来形成导电图案204以及导通孔206。导电图案204以及导通孔206嵌入介电层202中。介电层202与导电图案204可以交替形成。导通孔206穿过介电层202，以与导电图案204相互电性连接。导电图案204与导通孔206可以由铜、铝、镍、金、银、锡、上述的组合、铜/镍/金的复合结构，或其他适宜的导电材料所组成。
在图1B的示例性实施例中，重布线路结构200包括四个介电层202，然而，本发明对于介电层202的数量并不加以限制，并且可以基于电路的设计而进行调整。最上介电层202可以具有多个开口OP1，多个开口OP1暴露出最上导电图案204，以于后续的制程中进行电性连接。最下介电层202暴露出部分的最下导电图案204，使得最下导电图案204可以经由导通孔206与其他导电图案204进行内连线。
请参照图1C，于重布线路结构200上配置多个晶粒300以及多个连接模块500。晶粒300可以包括数字晶粒、模拟晶粒或混合信号晶粒。举例而言，晶粒300可以是特殊应用集成电路(Application-Specific Integrated Circuit,ASIC)晶粒、逻辑晶粒，或其他适宜的晶粒。每一晶粒300包括半导体基板302、多个导电接垫304、钝化层306以及多个导电连接器308。在一些实施例中，半导体基板302可以是具有主动元件(如晶体管或其他类似者)的硅基板，以及可以选择性地形成被动元件(如电阻、电容、电感或其他类似者)于其中。导电接垫304分布于半导体基板302上。导电接垫304可以包括铝接垫、铜接垫或其他适宜的金属接垫。于半导体基板302上形成钝化层306，以部分覆盖每一导电接垫304。换句话说，钝化层306具有多个接触开口，暴露出每一导电接垫304的至少一部分。钝化层306可以是氧化硅层、氮化硅层、氮氧化硅层或是由其他适宜的聚合物材料或介电材料所形成的介电层。于导电接垫304上配置导电连接器308。举例而言，导电连接器308可以部分地配置于钝化层306的接触开口中，以提供与导电接垫304的电性连接。在一些实施例中，每一导电连接器308可以包括导电栓塞308a与配置于导电栓塞308a上的导电凸块308b。可以于导电接垫304上电镀导电栓塞308a。电镀制程是，举例而言，电镀、化学镀、浸镀(immersion plating)或其他类似者。导电栓塞308a可以包括铜、铜合金或其他类似者。导电凸块308b可以由铜、镍、锡、银、上述的组合所制成。在一些实施例中，可以省略导电栓塞308a。换句话说，导电连接器308可以包括C2(晶片连接)凸块或C4(控制塌陷高度晶片连接)凸块。
在一些实施例中，每一晶粒300具有主动面300a以及相对于主动面300a的背面300b。如图1C所示，以面朝下的方式配置晶粒300，使得晶粒300的主动面300a面向重布线路结构200。晶粒300可以经由覆晶(flip-chip)接合电性连接至重布线路结构200。举例而言，可以于介电层202的部分开口OP1中配置晶粒300的导电连接器308，以与重布线路结构200的导电图案204直接接触。这样，可以实现晶粒300与重布线路结构200之间的电性连接。重布线路结构200可以被用于将电路信号重新分布至晶粒300，或从晶粒300将电路信号重新分布出去，且可以在比晶粒300更宽的区域中扩展。因此，在一些实施例中，重布线路结构200可以被称为是扇出式(fan-out)重布线路结构。
在一些实施例中，于重布线路结构200与晶粒300之间形成底胶400，以将导电连接器308与最上导电接垫204之间的耦合处保护且隔离。在一些实施例中，底胶400填充至最上介电层202的开口OP1中。底胶400可以通过毛细填充胶(capillary underfill filling,CUF)的方式形成，且底胶400可以包括聚合物材料、树脂或二氧化硅添加物。
在图1C的示例性实施例中，配置连接模块500以围绕晶粒300。每一连接模块500包括多个导电条502、多个阻障层504、多个导电帽506以及保护层508。导电条502可以形成圆柱形的形状。然而，本发明不限于此。在一些替代性实施例中，导电条502可以使用多边形柱或其他适宜的形状。导电条502的材料包括铜、铝、镍、锡、金、银、或上述的合金、或其他类似者。于导电条502上对应配置导电帽506，以进一步提升连接模块500与其他随后形成元件之间的电性连接与导线接合能力。在一些实施例中，导电帽506的材料与导电条502的材料不同。举例而言，导电帽506可以包括金或其他具有优异电性连接能力以及良好导线接合能力的金属材料。在一些实施例中，阻障层504可以包括镍、焊料、银或其他适宜的导电材料。每一阻障层504夹于导电帽506与导电条502之间，以防止导电帽506与导电条502之间的原子扩散。举例而言，当导电条502、阻障层504以及导电帽506分别由铜、镍以及金所制成时，由镍所形成的阻障层504可以防止导电条502中的铜原子从导电条502扩散至导电帽506中。导电帽506被铜污染后会导致导电帽506容易氧化，进而导致导线接合能力变差。然而，通过阻障层504的辅助，可以充分防止上述不利的影响。在一些实施例中，如果导电条502已经具有充分的导线接合能力接合随后形成的元件，则可以省略导电帽506以及阻障层504。
在图1C的示例性实施例中，导电条502、阻障层504以及导电帽506嵌入保护层508中。换句话说，保护层508保护导电条502、阻障层504以及导电帽506免受外部元件的影响。保护层508的材料可以包括聚合物、环氧树脂、模塑化合物或其他适宜的介电材料。
在一些实施例中，每一连接模块500可以还包括多个导电凸块510。于导电条502上对应配置导电凸块510。于导电条502远离导电帽506的那一面上配置导电凸块510。导电凸块510可以包括焊球或其他类似者。可以于重布线路结构200另一部分的开口OP1中配置导电凸块510，以于连接模块500与重布线路结构200之间形成电性连接。导电凸块510可以夹于导电条502与重布线路结构200之间。
在一些实施例中，预先制造连接模块500在其放置于重布线路结构200上之前。在一些实施例中，可以通过晶粒接合器(die bonder)、晶片分拣机(chip sorter)或表面黏着技术(Surface Mount Technology,SMT)机器于重布线路结构200上取放(pick-and-place)连接模块500。每一连接模块500中的导电条502的数量可以基于设计需求而进行调整。下面将结合图2A至图2D来讨论连接模块500的配置。
图2A至图2D是图1C中的连接模块500依据本发明各种实施例的上视示意图。请参照图2A，从上视图看，每一连接模块500可以呈现矩形形状。在一些实施例中，连接模块500具有5毫米(millimeter,mm)至15毫米的长度L，以及1.5毫米至2毫米的宽度W。如图2A所示，导电帽506分布于保护层508中，使得导电帽506之间的距离最小化，并同时维持导电帽506之间有效的电性隔离。当连接模块500为矩形时，可以于重布线路结构200上取放多个连接模块500，以围绕每一晶粒300的四个边。
请参照图2B，从上视图看，每一连接模块500可以呈现正方形形状。在一些实施例中，连接模块500的每一边的长度L的范围可以在5毫米至15毫米之间。当连接模块500为正方形时，可以于重布线路结构200上取放多个连接模块500，以围绕每一晶粒300的四个边。
请参照图2C，从上视图看，每一连接模块500可以是环形。换句话说，可以通过连接模块500包围空穴C，以容纳晶粒300。在一些实施例中，空穴C可以容纳一个或多个晶粒300。也就是说，可以于重布线路结构200上取放多个连接模块500，以围绕不同晶粒300。
请参照图2D，每一连接模块500可以包围多个空穴C。在一些实施例中，每一空穴C可以容纳一个或多个晶粒300。也就是说，可以于重布线路结构200上取放一个连接模块500，以围绕多个晶粒300，从而实现批次量产(batch production)。
请回头参照图1D，于重布线路结构200上形成绝缘材料612，以密封晶粒300、底胶400以及连接模块500。绝缘材料612的材料可以与连接模块500的保护层508的材料不同。举例而言，绝缘材料612可以包括通过模塑制程形成的模塑化合物或绝缘材料如环氧树脂、硅基树脂(silicone)或其他适宜的树脂。
请参照图1E，在形成绝缘材料612后，从重布线路结构200上移除离型层102以及载板100。如上面所提到，离型层102可以是光热转换层。在暴露于UV激光下，离型层102与载板100可以从重布线路结构200的最下介电层202与最下导电图案204上被剥离分开。在一些实施例中，在移除离型层102与载板100后，对传统的导线接合组件而言，如图1E所示的结构可以被切割成条状。
请参照图1F，减少绝缘材料612的厚度，以形成第一绝缘密封体610。可以移除部分的绝缘材料612，以暴露出连接模块500的保护层508，以及可以选择性地暴露出晶粒300的背面300b。同时，通过保护层508仍然良好地保护着导电帽506。在一些实施例中，可以通过平坦化制程移除绝缘材料612。平坦化制程包括，举例而言，化学机械研磨制程(chemical-mechanical polishing,CMP)、机械研磨制程(mechanical grinding process)、蚀刻或其他适宜的制程。在一些实施例中，在暴露出连接模块500的保护层508以及晶粒300的背面300b后，连接模块500、绝缘材料612以及晶粒300可以进一步进行研磨，以减少随后形成的封装结构10的整体厚度。在平坦化制程后，于重布线路结构200上配置第一绝缘密封体610，以侧向密封晶粒300以及连接模块500。在一些实施例中，保护层508的顶面508a、第一绝缘密封体610的顶面610a以及晶粒300的背面300b相互实质上共面(coplanar)。如上面所提到，由于第一绝缘密封体610与连接模块500的保护层508由不同材料所制成，因此，这两层被视为是两个不同的层。换句话说，可以于两个构件之间看见清楚的介面。应注意的是，在一些替代性实施例中，可以在如图1E所示的剥离制程前，执行薄化制程。
请参照图1G，于连接模块500的保护层508中形成多个开口OP2。在一些实施例中，通过激光钻孔制程(laser drilling process)形成开口OP2。举例而言，可以部分地移除位于导电帽506正上方的保护层508以形成开口OP2。换句话说，开口OP2的所在位置对应于导电帽506、阻障层504以及导电条502的所在位置。每一开口OP2暴露出连接模块500的每一导电帽506的至少一部分。
请参照图1H，于晶粒300以及相对于重布线路结构200的第一绝缘密封体610上配置堆叠晶片710。可以于晶粒300的背面300b以及第一绝缘密封体610的顶面610a放置堆叠晶片710。在一些实施例中，可以由多个晶片彼此相互堆叠构成堆叠晶片710。晶片可以包括具有非易失性存储器(non-volatile memory)的存储晶片，如NAND型快速存储器(NANDflash)。然而，本发明不限于此。在一些替代性实施例中，堆叠晶片710的晶片可以是能够执行其他功能的晶片，如逻辑功能、运算功能或其他类似者。在堆叠晶片710中，可以于两相邻晶片之间看见晶片黏着层，以增强这些两相邻的晶片之间的黏着力。
堆叠晶片710可以经由多条导线720电性连接至连接模块500的导电帽506。举例而言，在于晶粒300以及第一绝缘密封体610上配置堆叠晶片710后，可以经由打线接合制程形成多条导线720。导线720的一端连接至堆叠晶片710的至少一晶片。另一方面，导线720的另一端延伸至保护层508的开口OP2中，以连接至导电帽506。导线720的材料可以包括金、铝或其他适宜的导电材料。在一些实施例中，导线720的材料与导电帽506的材料相同。
请参照图1I，于第一绝缘密封体610与连接模块500上形成第二绝缘密封体620，以密封堆叠晶片710以及导线720。第二绝缘密封体620的材料可以与第一绝缘密封体610的材料相同或不同。举例而言，第二绝缘密封体620的材料可以包括环氧树脂、模塑化合物或其他适宜的绝缘材料。在一些实施例中，第二绝缘密封体620的材料可以为湿气吸收率较低的材料。可以通过压缩成型(compression molding)、转注成型(transfer molding)或其他适宜的密封制程形成第二绝缘密封体620。如图1I所示，第二绝缘密封体620填充至连接模块500的保护层508的开口OP2中，以保护导线720位于开口OP2中的线段。第二绝缘密封体620提供给堆叠晶片710与导线720物理支撑、机械保护以及电性和环境隔离。换句话说，堆叠晶片710与导线720嵌入第二绝缘密封体620中。
请参照图1J，于相对于晶粒300与连接模块500的重布线路结构200上形成多个导电端子800。在一些实施例中，于重布线路结构200的最下导电图案204上配置导电端子800。换句话说，重布线路结构200的最下导电图案204可以被称为凸块底金属(under-ballmetallization,UBM)图案。可以通过植球制程(ball placement process)以和/或回焊制程(reflow process)形成导电端子800。导电端子800可以为导电凸块，如焊球。然而，本发明不限于此。在一些替代性实施例中，导电端子800可以基于设计需求而使用其他可能的形式或形状。举例而言，导电端子800可以使用导电柱或导电栓塞(conductive posts)的形式。
请参照图1K，在形成导电端子800后，进行切割(singulation)制程，以获得多个封装结构10。切割制程包括，举例而言，以旋切刀(rotating blade)或激光束切割。
通过使用容易预先制造的连接模块500作为封装结构10内的垂直连接特征，由于连接模块500的厚度小，进而可以有效地缩小封装结构10的尺寸。此外，连接模块500的使用可以导致在传统封装结构中免除额外的载板或较厚的铜柱，进而降低制造成本。
图3是依据本发明一些替代实施例的封装结构20的剖面示意图。请参照图3，图3中的封装结构20类似于图1K中的封装结构10，因此采用相同的标号来表示近似的元件，且详细内容于此不加以赘述。图3的封装结构20与图1K的封装结构10差别在于：封装结构20还包括于晶粒300与连接模块500之间配置多个虚设晶粒910。可以在形成第一绝缘密封体610之前，于重布线路结构200上配置虚设晶粒910。可以通过取放制程(pick-and-placeprocess)于重布线路结构200上放置虚设晶粒910。如图3所示，第一绝缘密封体610的顶面610a、虚设晶粒910的顶面910a、晶粒300的背面300b以及保护层508的顶面508a相互实质上共面。
在一些实施例中，虚设晶粒910为电性浮接(electrically floating)。虚设晶粒910可以与重布线路结构200、晶粒300、连接模块500以及堆叠晶片710电性绝缘。在一些实施例中，虚设晶粒910可以没有主动元件。换句话说，虚设晶粒910可以不对封装结构20的运作做出贡献。
在一些实施例中，可以经由黏着层920，将每一虚设晶粒910黏着至重布线路结构200上。举例而言，可以于虚设晶粒910与重布线路结构200之间配置黏着层920。黏着层920可以保护重布线路结构200免于由于放置虚设晶粒910而导致的压痕，且可以最小化在重布线路结构200上的虚设晶粒910的位移。在一些实施例中，黏着层920可以包括晶粒黏着膜(die attach film,DAF)或其他类似的材料。
在一些实施例中，若晶粒300的尺寸小于堆叠晶片710，则虚设晶粒910可以作为隔板。也就是说，可以使用虚设晶粒910，以提供堆叠晶片710额外的物理支撑。应注意的是，虽然图3示出的为两个虚设晶粒910，本发明不限于此。可以基于堆叠晶片710与晶粒300的尺寸而调整虚设晶粒910的数量。
综上所述，容易预先制造的连接模块可以作为封装结构内的垂直连接特征。由于连接模块的厚度小，进而可以有效地缩小封装结构的尺寸。此外，连接模块的使用可以导致在传统封装结构中免除额外的载板或较厚的铜柱，进而降低制造成本。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视所附的权利要求所界定者为准。

Claims (10)

1.一种封装结构，包括：
重布线路结构；
晶粒，配置并电性连接至所述重布线路结构；
至少一连接模块，配置于所述重布线路结构上，所述连接模块具有保护层以及多个导电条，其中所述多个导电条嵌入所述保护层中，且所述保护层包括对应于所述多个导电条的多个开口；
第一绝缘密封体，密封所述晶粒与所述连接模块；
堆叠晶片，配置于所述第一绝缘密封体与所述晶粒上，其中所述堆叠晶片电性连接至所述连接模块；以及
第二绝缘密封体，密封所述堆叠晶片。
2.根据权利要求1所述的封装结构，还包括多个导电端子，配置于相对于所述晶粒与所述连接模块的所述重布线路结构上。
3.根据权利要求1所述的封装结构，还包括多条导线，嵌入所述第二绝缘密封体中，其中所述堆叠晶片经由所述多条导线电性连接至所述连接模块，且所述多条导线延伸至所述保护层的所述多个开口中。
4.根据权利要求1所述的封装结构，还包括多个虚设晶粒，配置于所述晶粒与所述连接模块之间。
5.根据权利要求1所述的封装结构，其中：
所述保护层的材料与所述第一绝缘密封体的材料不同；
所述连接模块还包括多个导电凸块，夹于所述多个导电条与所述重布线路结构之间；
所述连接模块还包括多个导电帽，对应配置于所述多个导电条上，且所述保护层的所述多个开口暴露出每一所述导电帽的至少一部分；
所述多个导电条的材料与所述多个导电帽的材料不同；或
所述第二绝缘密封体填充至所述保护层的所述多个开口中。
6.一种封装结构的制造方法，包括：
提供载板；
形成重布线路结构于所述载板上；
配置多个晶粒以及多个连接模块于所述重布线路结构上，每一所述连接模块具有保护层以及多个导电条，其中所述多个导电条嵌入所述保护层中；
形成第一绝缘密封体，以密封所述多个晶粒与所述多个连接模块；
从所述重布线路结构上移除所述载板；
形成多个开口于所述多个连接模块的所述保护层中，其中所述多个开口对应至所述多个导电条；
配置堆叠晶片于所述多个晶粒与相对于所述重布线路结构的所述第一绝缘密封体上，其中所述堆叠晶片电性连接至所述多个连接模块；以及
通过第二绝缘密封体密封所述堆叠晶片。
7.根据权利要求6所述的制造方法，还包括形成多条导线嵌入所述第二绝缘密封体中，其中所述堆叠晶片经由所述多条导线电性连接至所述多个连接模块，且所述多条导线延伸至所述保护层的所述多个开口中。
8.根据权利要求6所述的制造方法，还包括放置多个虚设晶粒于所述多个晶粒与所述多个连接模块之间。
9.根据权利要求6所述的制造方法，其中所述晶粒具有主动面以及相对于主动面的背面，所述晶粒包括多个导电连接器位于所述主动面，且所述第一绝缘密封体的形成步骤包括：
形成绝缘材料于所述重布线路结构上，以覆盖所述多个晶粒与所述多个连接模块；以及
移除部分的所述绝缘材料，以暴露出所述多个连接模块的所述保护层与所述多个晶粒的所述背面。
10.根据权利要求6所述的制造方法，其中：
所述多个晶粒经由覆晶接合电性连接至所述重布线路结构；
每一所述连接模块还包括多个导电凸块，且所述多个连接模块经由取放制程配置于所述重布线路结构上，使得所述多个导电凸块与所述重布线路结构直接接触；或
每一所述连接模块还包括多个导电帽，对应配置于所述多个导电条上，且所述保护层的所述多个开口暴露出每一所述导电帽的至少一部分。
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