JP6835798B2 - パッケージ構造体及びパッケージ構造体の製造方法 - Google Patents

パッケージ構造体及びパッケージ構造体の製造方法 Download PDF

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JP6835798B2
JP6835798B2 JP2018214495A JP2018214495A JP6835798B2 JP 6835798 B2 JP6835798 B2 JP 6835798B2 JP 2018214495 A JP2018214495 A JP 2018214495A JP 2018214495 A JP2018214495 A JP 2018214495A JP 6835798 B2 JP6835798 B2 JP 6835798B2
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conductive
die
package structure
connection module
structure according
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JP2019096874A (ja
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上▲ユ▼ 張簡
上▲ユ▼ 張簡
宏欣 徐
宏欣 徐
南君 林
南君 林
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力成科技股▲分▼有限公司
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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
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Description

本開示は一般に、パッケージ構造体及びパッケージ構造体の製造方法に関するものであり、特に、接続モジュールを有するパッケージ構造体及びパッケージ構造体の製造方法に関するものである。
近年の半導体パッケージ技術の開発では、より小さな体積で、より軽量で、集積レベルが高く、製造コストが低い製品の輸送に着目されてきた。多機能半導体パッケージに対して、チップを積層する技術を用いて、データを保存し処理する容量がより大きなパッケージが提供されている。所望機能を増やすことが当該分野における研究者にとって挑戦となり、多機能電子部品に対する需要が急速に高まってきた。
本開示は、パッケージ構造体の高さが効果的に低くなり、パッケージ構造体の製造コストがより低くなる、パッケージ構造体及びパッケージ構造体の製造方法を提供する。
本開示は、再分配構造体と、ダイと、少なくとも１つの接続モジュールと、第１絶縁カプセル材と、チップ積層体と、第２絶縁カプセル材と、を含むパッケージ構造体を提供する。ダイは、再分配構造体上に配置され、再分配構造体に電気的に接続される。接続モジュールは、再分配構造体上に配置される。接続モジュールは、保護層と、保護層に埋め込まれる複数の導電バーとを含む。第１絶縁カプセル材は、ダイ及び接続モジュールをカプセル化する。チップ積層体は、第１絶縁カプセル材及びダイの上に配置される。チップ積層体は、接続モジュールに電気的に接続される。第２絶縁カプセル材は、チップ積層体をカプセル化する。
本開示は、パッケージ構造体の製造方法を提供する。本方法は、少なくとも以下のステップを含む。キャリアを提供する。複数のダイ及び複数の接続モジュールをキャリア上に配置する。接続モジュールのそれぞれは保護層と保護層に埋め込まれる複数の導電バーとを含む。第１絶縁カプセル材をキャリア上に形成してダイ及び接続モジュールをカプセル化する。再分配構造体を、ダイ、接続モジュール及び第１絶縁カプセル材の上に形成する。キャリアを、ダイ、接続モジュール及び第１絶縁カプセル材から除去する。開口部は導電バーに対応する。チップ積層体を、ダイ及び第１絶縁カプセル材の、再分配構造体とは反対側に配置する。チップ積層体は接続モジュールに電気的に接続される。チップ積層体を第２絶縁カプセル材によってカプセル化する。
上記記載に基づいて、すぐに利用できる、前もって製造された接続モジュールは、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。接続モジュールの厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、接続モジュールの適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
上記記載をよりわかりやすくするため、添付の図面とともにいくつかの実施形態を以下詳細に説明する。
本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。
本発明を更に理解するために図面を添付する。添付の図面をこの明細書に組み込んで、当該明細書の一部を構成する。図面は、本発明の実施形態を示し、本開示が表す原理を本明細書と共に説明するのに役立つ。図面全体にわたって、同一の又は類似する符号は、同一の又は類似する構成要素を指す。
これから、本発明の好ましい実施形態に詳細に言及する。本発明の実施例は、添付の図面に図示されている。可能な限り、同一又は類似の部分に言及するために同一の参照番号を図面及び明細書で使用する。
図１Ａから図１Ｊは、本開示のある実施形態に従うパッケージ構造体１０の製造方法を示す模式断面図である。図１Ａを参照して、その上に剥離層１０２が形成される、キャリア１００が提供される。キャリア１００をガラス基板又はガラス支持板とすることができる。しかしながら、これらの構成は本開示を限定すると解釈されるものではない。その上のパッケージ構造体を構造的に支持しながら続いて起こるプロセスに耐え得る限り、他の適切な基板材料を適合し得る。剥離層１０２は、光熱変換（ＬＴＨＣ）材料、エポキシ樹脂、無機材料、有機高分子材料又は他の適切な接着材を含み得る。しかしながら、本開示はこれらの構成に限定されるものではなく、ある代替的実施形態では、他の適切な剥離層を使用することができる。
図１Ｂを参照して、複数のダイ２００及び複数の接続モジュール３００を、剥離層１０２及びキャリア１００の上に配置する。ダイ２００は、デジタルダイ、アナログダイ又は混合信号ダイを含み得る。例えば、ダイ２００を、特定用途向け集積回路（ＡＳＩＣ）ダイ、論理ダイ又は他の適切なダイとすることができる。それぞれのダイ２００は、半導体基板２０２と、複数の導電パッド２０４と、不活性化層２０６と、複数の導電コネクタ２０８とを含む。ある実施形態では、半導体基板２０２を、その中に形成される能動素子（例えばトランジスタ等）及び任意に受動素子（例えば抵抗器、コンデンサ又はインダクタ等）を含む、シリコン基板とすることができる。導電パッド２０４は、半導体基板２０２にわたって分布する。導電パッド２０４は、アルミニウムパッド、銅パッド又は他の適切な金属パッドを含むことができる。不活性化層２０６は、半導体基板２０２にわたって形成されて、各接続パッド２０４を部分的に被覆する。言い換えれば、不活性化層２０６は、各接続パッド２０４の少なくとも一部をあらわにする複数のコンタクト開口部を有する。不活性化層２０６を、シリコン酸化層、シリコン窒化層、シリコン酸窒化層若しくは高分子材料で形成される誘電層、又は他の適切な誘電材料とすることができる。導電コネクタ２０８は、導電パッド２０４上に配置される。例えば、導電コネクタ２０８は、不活性化層２０６のコンタクト開口部内へ延在して、導電パッド２０４と電気的に接続することができる。ある実施形態では、導電ポスト２０８ａを導電パッド２０４上にメッキすることができる。メッキプロセスは例えば、電気メッキ、無電解メッキ又は浸漬メッキ等である。導電コネクタ２０８は、導電ポスト、導電ピラー又は導電バンプの形状をとることができる。導電コネクタ２０８の材料は、銅、アルミニウム、スズ、金、銀若しくはこれらの合金又は他の適切な導電材料を含む。
ある実施形態では、各ダイ２００は、有効面２００ａと、有効面２００ａの反対側の裏面２００ｂとを有する。図１Ｂに示すように、ダイ２００は、表を上にして配置される。言い換えれば、ダイ２００の有効面２００ａは、キャリア１００から離れる方向を向く一方、ダイ２００の裏面２００ｂはキャリア１００の方を向く。ある実施形態では、接着層４００を通じてダイ２００をキャリア１００に取付けることができる。例えば、接着層４００がダイ２００の半導体基板２０２と剥離層１０２との間に挟まれるように、接着層４００をダイ２００の裏面２００ｂ上に配置することができる。接着層４００は、ダイ２００と剥離層１０２との間の接着性を一時的に高めて、ダイが変位することを妨げることができる。ある実施形態では、接着層４００をドライフィルムとすることができ、接着層４００をラミネーションプロセスによって剥離層１０２に接着することができる。あるいは、接着層４００の溶液（液体型）を剥離層１０２上にコーティングプロセスによって覆うことができる。続いて、溶液を乾燥させ硬化させて、接着層４００の固体層を形成する。接着層４００をＢステージ状材料で製造することができる。例えば、接着層４００は、ダイアタッチフィルム（ＤＡＦ）を構成する樹脂を含むことができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、接着性を有する他の材料を接着層４００用の材料として適合させることができる。ある実施形態では、接着層４００は省略可能である。接着層４００を利用していないときに、ダイ２００を剥離層１０２上に直接取付けることができる。
図１Ｂに示すように、接続モジュール３００を少なくとも１つのダイ２００の外周に沿って配置する。それぞれの接続モジュール３００は、複数の導電バー３０２と、複数のバリア層３０４と、複数の導電キャップ３０６と、保護層３０８とを含む。導電バー３０２を円柱状カラムとして成形することができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電バー３０２は多角柱状又は他の適切な形状をとることができる。導電ポストバー３０２の材料は、銅、アルミニウム、ニッケル、スズ、金、銀又はこれらの合金等を含む。導電キャップ３０６は、導電バー３０２上に対応して配置される。導電キャップ３０６は、導電バー３０２上に配置されて、接続モジュール３００の続いて形成される他の要素との電気的接続性及びワイヤボンディング性を更に高める。ある実施形態では、導電キャップ３０６の材料は、導電バー３０２の材料とは異なる。例えば、導電キャップ３０６は、金、又は電気伝導性に優れワイヤボンディング性が良好な他の金属材料を含むことができる。いくつかの実施形態では、バリア層３０４は、ニッケル、はんだ、銀又は他の適切な導電材料を含むことができる。それぞれのバリア層３０４が、導電キャップ３０６と導電バー３０２との間に挟まれて、導電キャップ３０６と導電バー３０２との間の原子の拡散を妨げる。例えば、導電バー３０２、バリア層３０４及び導電キャップ３０６がそれぞれ、銅、ニッケル及び金で製造されるときには、ニッケルで製造されるバリア層３０４は、導電バー３０２の銅原子が導電キャップ３０６に拡散することを妨げることができる。導電キャップ３０６が銅で汚染されると、導電キャップ３０６が酸化しやすくなり、そのためワイヤボンディング性が悪化する。しかしながら、バリア層３０４によって、上述した悪影響を十分に抑えることができる。ある実施形態では、導電バー３０２が後に形成される構成要素と既に十分なワイヤボンディング性を有しているときに、導電キャップ３０６及びバリア層３０４を省略することができる。
図１Ｂに示すように、導電バー３０２、バリア層３０４及び導電キャップ３０６は、保護層３０８に埋め込まれる。しかしながら、保護層３０８は、それぞれの導電バー３０２の少なくとも一部と、それぞれの導電キャップ３０６の少なくとも一部とを露出させる。例えば、保護層３０８は、導電バー３０２、バリア層３０４及び導電キャップ３０６を横方向にカプセル化することができる。その一方で、保護層３０８は、導電バー３０２の表面３０２ａを露出させることができる。ある実施形態では、導電バー３０２の表面３０２ａは、保護層３０８の第１面３０８ａに対して実質的に同一平面上に存在することができる。同様に、保護層３０８は、導電キャップ３０６の表面３０６ｂも露出させる。すなわち、導電キャップ３０６の表面３０６ｂは、保護層３０８の第２面３０８ｂ（保護層３０８の第１面３０８ａとは反対側の面）に対して実質的に同一平面上に存在する。なお、図１Ｂに表す構成は、単なる例示的イラストレーションとして役立つものであり、本開示はこの構成に限定されるものではない。ある代替的実施形態では、保護層３０８は、導電バー３０２があらわにならないように、導電バー３０２の表面３０２ａを覆うことができる。言い換えれば、保護層３０８の第１面３０８ａの高さが導電バー３０２の上面３０２ａの高さよりも高くなるように、保護層３０８の第１面３０８ａを位置付けることができる。ある実施形態では、保護層３０８の材料は、ポリマー、エポキシ、成形コンパウンド又は他の適切な誘電材料を含む。
ある実施形態では、接続モジュール３００をキャリア１００上に設置する前に、接続モジュール３００を前もって製造する。ある実施形態では、つまみ上げ配置プロセスによって、接続モジュール３００をキャリア１００上に設置することができる。例えば、ダイボンダ、チップソータ又はＳＭＴ（表面実装技術）機械によって、接続モジュール３００をつまみ上げてキャリア１００及び剥離層１０２の上に配置する。図１Ｂに示すように、導電キャップ３０６がキャリア１００に面するように、接続モジュール３００を設置する。すなわち、接続モジュール３００は、導電キャップ３０６が導電バー３０２よりもキャリア１００に近くなるように設置される。各接続モジュール３００内の導電バー３０２の数は、設計要件によって変わり得る。平面視（図示せず）で、保護層３０８内に導電バー３０２を分布させて、導電バー同士の電気的絶縁を効果的に維持しながら、導電バー３０２同士の距離を最小化する。ある実施形態では、接続モジュール３００を、平面視で正方形状、矩形状、リング形状又は他の幾何学的形状とすることができる。
図１Ｃを参照して、絶縁材５１２をキャリア１００及び剥離層１０２の上に形成して、ダイ２００及び接続モジュール３００を覆う。言い換えれば、絶縁材５１２は、ダイ２００及び接続モジュール３００をカプセル化する。ある実施形態では、絶縁材５１２の材料を、接続モジュール３００の保護層３０８の材料とは異なる材料とすることができる。例えば、絶縁材５１２は、成形プロセスによって形成される成形コンパウンド、又はエポキシ、シリコーン若しくは他の適切な樹脂等の絶縁材を含むことができる。ある実施形態では、ダイ２００及び接続モジュール３００があらわにならないように、絶縁材５１２をオーバーモールドプロセスによって成形する。例えば、図１Ｃに示すように、絶縁材５１２の上面５１２ａの高さが、保護層３０８の第１面３０８ａの高さ、導電バー３０２の表面３０２ａの高さ及び導電コネクタ２０８の上面２０８ａの高さよりも高くなるように、絶縁材５１２の上面５１２ａを位置付ける。
図１Ｄを参照して、絶縁材５１２の厚さを薄くして、第１絶縁カプセル材５１０を形成する。例えば、ダイ２００の導電コネクタ２０８と接続モジュール３００の導電バー３０２との両方が露出するまで、絶縁材５１２の一部を除去する。ある実施形態では、平坦化プロセスによって絶縁材５１２を除去することができる。平坦化プロセスは例えば、化学機械研磨（ＣＭＰ）、機械的研磨、エッチング又は他の適切なプロセスを含む。ある実施形態では、平坦化プロセスにおいて、接続モジュール３００、絶縁材５１２及びダイ２００を更に研磨して、後に形成するパッケージ構造体１０の全厚を薄くすることができる。平坦化プロセス後、第１絶縁カプセル材５１０をキャリア１００及び剥離層１０２の上に形成して、ダイ２００及び接続モジュール３００を横方向にカプセル化する。ある実施形態では、保護層３０８の第１面３０８ａと、第１絶縁カプセル材５１０の第１面５１０ａと、導電バー３０２の表面３０２ａと、導電コネクタ２０８の上面２０８ａとは実質的に互いに同一平面上に存在する。上述したように、第１絶縁カプセル材５１０及び接続モジュール３００の保護層３０８は、異なる材料で製造されるため、第１絶縁カプセル材５１０及び保護層３０８は２つの別個の層として考えられる。言い換えれば、第１絶縁カプセル材５１０と保護層３０８との間には、はっきりした境界面が見られ得る。
図１Ｅを参照して、ダイ２００、接続モジュール３００及び第１絶縁カプセル材５１０の上に再分配構造体６００を形成する。再分配構造体６００は、少なくとも一層の誘電層６０２と、複数の導電パターン６０４と、複数の導電ビア６０６とを含み得る。スピンオンコーティング、化学蒸着（ＣＶＤ）又はプラズマＣＶＤ（ＰＥＣＶＤ）等の適切な製造技術で誘電層６０２を形成することができる。誘電層６０２を、シリコン酸化物、シリコン窒化物、炭化珪素、オキシ窒化ケイ素、ポリイミド又はベンゾシクロブテン（ＢＣＢ）等の、無機又は有機誘電材料で製造することができる。他方では、導電パターン６０４及び導電ビア６０６を、スパッタリング、エバポレーション、無電解メッキ又は電気メッキによって形成することができる。導電パターン６０４及び導電ビア６０６は、誘電層６０２に埋め込まれる。誘電層６０２及び導電パターン６０４を交互に積層することができる。導電ビア６０６は、誘電層６０２を貫通し、導電パターン６０４を互いに電気的に接続する。導電パターン６０４及び導電ビア６０６を、銅、アルミニウム、ニッケル、金、銀、スズ若しくはこれらの組み合わせ、銅／ニッケル／金の複合構造又は他の適切な導電材料で製造し得る。
図１Ｅに示すように、再分配層６００は４つの誘電層６０２を含む。しかしながら、誘電層６０２の数は限定されず、回路設計に基づいて誘電層の数を調節することができる。底部誘電層６０２は、接続モジュール３００の導電バー３０２とダイ２００の導電コネクタ２０８とを部分的に露出させる複数のコンタクト開口部６０２ａを有し得る。コンタクト開口部６０２ａに配置される導電ビア６０６を、接続モジュール３００の導電バー３０２及びダイ２００の導電コネクタ２０８と直接接触させることができる。言い換えれば、ダイ２００の導電コネクタ２０８は、再分配構造体６００と直接接触して、ダイ２００と再分配構造体６００との間を電気的に接続する。また同様に、接続モジュール３００の導電バー３０２は、再分配構造体６００と直接接触して、接続モジュール３００と再分配構造体６００との間を電気的に接続する。導電ビア６０６を通じて底部導電パターン６０４を他の導電パターン６０４（例えば中間部導電パターン６０４）に電気的に接続できるように、中間部誘電層６０２は底部導電パターン６０４の一部を露出させる。上部誘電層６０２は、中間部導電パターン６０４の一部を露出させる複数のコンタクト開口部６０２ｂを有する。上部導電ビア６０６は、コンタクト開口部６０２ｂ内へ延在して、上部導電パターン６０４と中間部導電パターン６０４との間を電気的に接続することができる。他方では、上部導電パターン６０４を、後のプロセスで電気的に接続するために、上部誘電層６０２上に配置する。ある実施形態では、上部導電パターン６０４を、アンダーバンプ金属メタライゼーション（ＵＢＭ）パターンと呼ぶことができる。
ある実施形態では、再分配構造体６００を使用して、ダイ２００への又はダイ２００からの電気信号の経路を変えることができ、再分配構造体６００は、ダイ２００よりも広い領域に拡張することができる。したがって、ある実施形態では、再分配構造体６００を「ファンアウト再分配構造体」と呼ぶことができる。
図１Ｆを参照して、剥離層１０２及びキャリア１００をダイ２００、接続モジュール３００、接着層４００及び第１絶縁カプセル材５１０から除去する。上述したように、剥離層１０２をＬＴＨＣ層とすることができる。紫外レーザ光線を露光した後に、剥離層１０２及びキャリア１００を、接続モジュール３００の導電キャップ３０６及び保護層３０８、接着層４００並びに第１絶縁カプセル材５１０から剥がして分離することができる。キャリア１００及び剥離層１０２を除去すると、保護層３０８の第２面３０８ｂ、導電キャップ３０６の面３０６ｂ及び第１絶縁カプセル材５１０の第２面５１０ｂ（第１絶縁カプセル材５１０の第１面５１０ａとは反対側の面）が露出する。図１Ｆに示すように、導電キャップ３０６の面３０６ｂ、保護層３０８の第２面３０８ｂ及び第１絶縁カプセル材５１０の第２面５１０ｂは実質的に、互いに同一平面上に存在する。
図１Ｇを参照して、図１Ｆに示す構造体の上下をひっくり返して、ダイ２００、接続モジュール３００及び第１絶縁カプセル材５１０が再分配構造体６００の上／上方に配置されることを表す。その後、チップ積層体７１０を、ダイ２００及び第１絶縁カプセル材５１０の再分配構造体６００とは反対側に配置する。例えば、チップ積層体７１０を、接着層４００及び第１絶縁カプセル材５１０の第２面５１０ｂの上に設置することができる。すなわち、接着層４００をチップ積層体７１０とダイ２００の裏面２００ｂとの間に挟む。ある実施形態では、チップ積層体７１０を、互いに積層される複数のチップによって構成することができる。チップは、ＮＡＮＤフラッシュ等の不揮発性メモリーを有するメモリチップを含み得る。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、チップ積層体７１０のチップを、論理機能又は演算機能等の他の機能を実施できるチップとすることができる。チップ積層体７１０の隣接する２つのチップ間に、これら２つのチップ間の付着性を高めるためのチップ装着層が見られ得る。
チップ積層体７００を、複数の導電線７２０によって、接続モジュール３００の導電キャップ３０６に電気的に接続することができる。例えば、チップ積層体７１０を接着層４００及び第１絶縁カプセル材５１０の上に配置した後に、複数の導電線７２０をワイヤボンディングプロセスによって形成することができる。導電線７２０の一端部は、チップ積層体７１０の少なくとも１つのチップに接続される。他方では、導電線７２０の他端部は、導電キャップ３０６の面３０６ｂと接続される。導電線７２０の材料は、金、アルミニウム又は他の適切な導電材料を含み得る。ある実施形態では、導電線７２０の材料は、導電キャップ３０６の材料と同じである。
図１Ｈを参照して、第２絶縁カプセル材５２０を、第１絶縁カプセル材５１０及び接続モジュール３００の上に形成して、チップ積層体７１０及び導電線７２０をカプセル化する。第２絶縁カプセル材５２０の材料を、第１絶縁カプセル材５１０と同じ材料とすることができ、又は第１絶縁カプセル材５１０とは異なる材料とすることができる。例えば、第２絶縁カプセル材５２０の材料は、エポキシ、成形コンパウンド又は他の適切な絶縁材を含むことができる。ある実施形態では、第２絶縁カプセル材５２０の材料の吸湿度を低くすることができる。第２絶縁カプセル材５２０を、圧縮成形、トランスファー成型又は他のカプセル化プロセスによって形成することができる。第２絶縁カプセル材５２０は、チップ積層体７１０及び導電線７２０に対して、物理的支持、機械的保護並びに電気的絶縁及び環境的分離をもたらす。言い換えれば、チップ積層体７１０及び導電線７２０は、第２絶縁カプセル材５２０に埋め込まれる。
図１Ｉを参照して、複数の導電端子８００が、再分配構造体６００のダイ２００及び接続モジュール３００とは反対側に形成される。ある実施形態では、導電端子８００は、再分配構造体６００のＵＢＭパターン（図１Ｉに表す底部導電パターン６０４）上に配置される。導電端子８００を、ボール載置プロセス及び／又はリフロープロセスによって形成することができる。導電端子８００を、はんだボール等の導電バンプとすることができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電端子８００は、設計要件に基づいて他の可能な形態及び形状をとることができる。例えば、導電端子８００は、導電ピラー又は導電ポストの形状をとることができる。
図１Ｊを参照して、導電端子８００を形成した後に、シンギュレーションプロセスを行って、複数のパッケージ構造体１０を得る。シンギュレーションプロセスは例えば、回転ブレード又はレーザ光線を用いた切断を含む。
上記記載に基づいて、すぐに利用できる、前もって製造された接続モジュールは、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。接続モジュールの厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、接続モジュールの適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
本発明の範囲又は精神から離れることなく、本明細書で開示される実施形態及び概念に対して様々な変更及び変形を加えることができることが、当業者にとって明らかであろう。前述したことを考慮して、本発明の変更又は変形は、特許請求の範囲及び特許請求の範囲の均等物に該当するときには、本開示に含まれることを意図する。
本開示は、パッケージ構造体及びパッケージ構造体の製造方法を提供する。パッケージ構造体を、電気製品で利用することができる。本開示の小型化されるパッケージ構造体を利用することで、電気製品のサイズを十分に減少させることができる。
１０：パッケージ構造体
１００：キャリア
１０２：剥離層
２００：ダイ
２００ａ：有効面
２００ｂ：裏面
２０２：半導体基板
２０４：導電パッド
２０６：不活性化層
２０８：導電コネクタ
２０８ａ、５１２ａ：上面
３００：接続モジュール
３０２：導電バー
３０２ａ，３０６ｂ：表面
３０４：バリア層
３０６：導電キャップ
３０８：保護層
３０８ａ、５１０ａ：第１面
３０８ｂ、５１０ｂ：第２面
４００：接着層
５１０：第１絶縁カプセル材
５１２：絶縁材
５２０：第２絶縁カプセル材
６００：再分配構造体
６０２：誘電層
６０２ａ、６０２ｂ：コンタクト開口部
６０４：導電パターン
６０６：導電ビア
７１０：チップ積層体
７２０：導電線
８００：導電端子

Claims (17)

  1. 再分配構造体と、
    前記再分配構造体上に配置され、前記再分配構造体に電気的に接続されるダイと、
    前記再分配構造体上に配置され、保護層及び前記保護層に埋め込まれる複数の導電バーを含む少なくとも１つの、平面視で正方形状または矩形状の接続モジュールと、
    前記ダイ及び前記接続モジュールをカプセル化する第１絶縁カプセル材と、
    前記第１絶縁カプセル材及び前記ダイの上に配置され、前記接続モジュールに電気的に接続されるチップ積層体と、
    前記チップ積層体をカプセル化する第２絶縁カプセル材と、
    を備え、
    前記接続モジュールは、導電バー上に対応して配置される複数の導電キャップを更に備え、
    前記保護層は、それぞれの導電キャップの少なくとも一部を露出させ、
    前記導電キャップの表面と、前記保護層の表面と、前記第１絶縁カプセル材の表面とは、実質的に同一平面上に存在する、パッケージ構造体。
  2. 前記再分配構造体の前記ダイ及び前記接続モジュールとは反対側に配置される複数の導電端子を更に備える、請求項１に記載のパッケージ構造体。
  3. 前記ダイは有効面及び前記有効面とは反対側の裏面とを有し、前記ダイは前記有効面上に位置付けられる複数の導電コネクタを備え、前記導電コネクタは前記再分配構造体と直接接触する、請求項１に記載のパッケージ構造体。
  4. 前記ダイの前記裏面と前記チップ積層体との間に挟まれる接着層を更に含む、請求項３に記載のパッケージ構造体。
  5. 前記保護層の材料が前記第１絶縁カプセル材の材料とは異なる、請求項１に記載のパッケージ構造体。
  6. 前記第２絶縁カプセル材に埋め込まれる複数の導電線を更に備え、
    前記チップ積層体は前記導電線を通じて前記接続モジュールに電気的に接続される、請求項１に記載のパッケージ構造体。
  7. 前記導電キャップの材料は金を含む、請求項１に記載のパッケージ構造体。
  8. 前記導電バーの材料は、前記導電キャップの材料とは異なる、請求項１に記載のパッケージ構造体。
  9. キャリアを提供するキャリア提供ステップと、
    複数のダイ及び複数の平面視で正方形状または矩形状の接続モジュールを前記キャリア上に配置する配置ステップと、
    第１絶縁カプセル材を前記キャリア上に形成して前記ダイ及び前記接続モジュールをカプセル化する第１絶縁カプセル材形成ステップと、
    前記ダイ、前記接続モジュール及び前記第１絶縁カプセル材の上に再分配構造体を形成する再分配構造体形成ステップと、
    前記キャリアを、前記ダイ、前記接続モジュール及び前記第１絶縁カプセル材から除去する除去ステップと、
    前記接続モジュールに電気的に接続されるチップ積層体を、前記ダイ及び前記第１絶縁カプセル材の、前記再分配構造体とは反対側に配置するチップ積層体配置ステップと、
    前記チップ積層体を第２絶縁カプセル材によってカプセル化するチップ積層体カプセル化ステップと、
    を含む、パッケージ構造体の製造方法であり、
    前記接続モジュールのそれぞれは保護層と、前記保護層に埋め込まれる複数の導電バーとを含み、
    前記ダイは、有効面と前記有効面とは反対側の裏面とを有し、
    前記ダイは、前記有効面上に位置付けられる複数の導電コネクタを備え、
    前記第１絶縁カプセル材形成ステップは、絶縁材をキャリア上に形成して前記ダイ及び前記接続モジュールを被覆するステップと、前記絶縁材の一部を除去して前記ダイの前記導電コネクタ及び前記接続モジュールの前記導電バーを露出させるステップと、を含む、パッケージ構造体の製造方法。
  10. 複数の導電端子を前記再分配構造体の前記ダイ及び前記接続モジュールとは反対側に形成するステップを更に含む、請求項９に記載のパッケージ構造体の製造方法。
  11. 前記第２絶縁カプセル材に埋め込まれる複数の導電線を形成するステップを更に含み、
    前記チップ積層体は前記導電線を通じて前記接続モジュールに電気的に接続される、請求項９に記載のパッケージ構造体の製造方法。
  12. シンギュレーションプロセスを行うステップを更に備える、請求項９に記載のパッケージ構造体の製造方法。
  13. 前記保護層の材料は、前記第１絶縁カプセル材の材料とは異なる、請求項９に記載のパッケージ構造体の製造方法。
  14. 前記接続モジュールはつまみ上げ配置プロセスによって前記キャリア上に配置される、請求項９に記載のパッケージ構造体の製造方法。
  15. それぞれの接続モジュールは前記導電バー上に対応して配置される複数の導電キャップを更に備え、前記保護層はそれぞれの導電キャップの少なくとも一部を露出させる、請求項９に記載のパッケージ構造体の製造方法。
  16. 前記導電キャップが前記キャリアに面するように、前記接続モジュールは前記キャリア上に配置される、請求項１５に記載のパッケージ構造体の製造方法。
  17. 前記導電キャップの材料は金を含む、請求項１５に記載のパッケージ構造体の製造方法。
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