JP6835798B2 - パッケージ構造体及びパッケージ構造体の製造方法 - Google Patents

パッケージ構造体及びパッケージ構造体の製造方法 Download PDF

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JP6835798B2
JP6835798B2 JP2018214495A JP2018214495A JP6835798B2 JP 6835798 B2 JP6835798 B2 JP 6835798B2 JP 2018214495 A JP2018214495 A JP 2018214495A JP 2018214495 A JP2018214495 A JP 2018214495A JP 6835798 B2 JP6835798 B2 JP 6835798B2
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conductive
die
package structure
connection module
structure according
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JP2019096874A (ja
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上▲ユ▼ 張簡
上▲ユ▼ 張簡
宏欣 徐
宏欣 徐
南君 林
南君 林
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力成科技股▲分▼有限公司
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Description

本開示は一般に、パッケージ構造体及びパッケージ構造体の製造方法に関するものであり、特に、接続モジュールを有するパッケージ構造体及びパッケージ構造体の製造方法に関するものである。
近年の半導体パッケージ技術の開発では、より小さな体積で、より軽量で、集積レベルが高く、製造コストが低い製品の輸送に着目されてきた。多機能半導体パッケージに対して、チップを積層する技術を用いて、データを保存し処理する容量がより大きなパッケージが提供されている。所望機能を増やすことが当該分野における研究者にとって挑戦となり、多機能電子部品に対する需要が急速に高まってきた。
本開示は、パッケージ構造体の高さが効果的に低くなり、パッケージ構造体の製造コストがより低くなる、パッケージ構造体及びパッケージ構造体の製造方法を提供する。
本開示は、再分配構造体と、ダイと、少なくとも1つの接続モジュールと、第1絶縁カプセル材と、チップ積層体と、第2絶縁カプセル材と、を含むパッケージ構造体を提供する。ダイは、再分配構造体上に配置され、再分配構造体に電気的に接続される。接続モジュールは、再分配構造体上に配置される。接続モジュールは、保護層と、保護層に埋め込まれる複数の導電バーとを含む。第1絶縁カプセル材は、ダイ及び接続モジュールをカプセル化する。チップ積層体は、第1絶縁カプセル材及びダイの上に配置される。チップ積層体は、接続モジュールに電気的に接続される。第2絶縁カプセル材は、チップ積層体をカプセル化する。
本開示は、パッケージ構造体の製造方法を提供する。本方法は、少なくとも以下のステップを含む。キャリアを提供する。複数のダイ及び複数の接続モジュールをキャリア上に配置する。接続モジュールのそれぞれは保護層と保護層に埋め込まれる複数の導電バーとを含む。第1絶縁カプセル材をキャリア上に形成してダイ及び接続モジュールをカプセル化する。再分配構造体を、ダイ、接続モジュール及び第1絶縁カプセル材の上に形成する。キャリアを、ダイ、接続モジュール及び第1絶縁カプセル材から除去する。開口部は導電バーに対応する。チップ積層体を、ダイ及び第1絶縁カプセル材の、再分配構造体とは反対側に配置する。チップ積層体は接続モジュールに電気的に接続される。チップ積層体を第2絶縁カプセル材によってカプセル化する。
上記記載に基づいて、すぐに利用できる、前もって製造された接続モジュールは、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。接続モジュールの厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、接続モジュールの適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
上記記載をよりわかりやすくするため、添付の図面とともにいくつかの実施形態を以下詳細に説明する。
本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。
本発明を更に理解するために図面を添付する。添付の図面をこの明細書に組み込んで、当該明細書の一部を構成する。図面は、本発明の実施形態を示し、本開示が表す原理を本明細書と共に説明するのに役立つ。図面全体にわたって、同一の又は類似する符号は、同一の又は類似する構成要素を指す。
これから、本発明の好ましい実施形態に詳細に言及する。本発明の実施例は、添付の図面に図示されている。可能な限り、同一又は類似の部分に言及するために同一の参照番号を図面及び明細書で使用する。
図1Aから図1Jは、本開示のある実施形態に従うパッケージ構造体10の製造方法を示す模式断面図である。図1Aを参照して、その上に剥離層102が形成される、キャリア100が提供される。キャリア100をガラス基板又はガラス支持板とすることができる。しかしながら、これらの構成は本開示を限定すると解釈されるものではない。その上のパッケージ構造体を構造的に支持しながら続いて起こるプロセスに耐え得る限り、他の適切な基板材料を適合し得る。剥離層102は、光熱変換(LTHC)材料、エポキシ樹脂、無機材料、有機高分子材料又は他の適切な接着材を含み得る。しかしながら、本開示はこれらの構成に限定されるものではなく、ある代替的実施形態では、他の適切な剥離層を使用することができる。
図1Bを参照して、複数のダイ200及び複数の接続モジュール300を、剥離層102及びキャリア100の上に配置する。ダイ200は、デジタルダイ、アナログダイ又は混合信号ダイを含み得る。例えば、ダイ200を、特定用途向け集積回路(ASIC)ダイ、論理ダイ又は他の適切なダイとすることができる。それぞれのダイ200は、半導体基板202と、複数の導電パッド204と、不活性化層206と、複数の導電コネクタ208とを含む。ある実施形態では、半導体基板202を、その中に形成される能動素子(例えばトランジスタ等)及び任意に受動素子(例えば抵抗器、コンデンサ又はインダクタ等)を含む、シリコン基板とすることができる。導電パッド204は、半導体基板202にわたって分布する。導電パッド204は、アルミニウムパッド、銅パッド又は他の適切な金属パッドを含むことができる。不活性化層206は、半導体基板202にわたって形成されて、各接続パッド204を部分的に被覆する。言い換えれば、不活性化層206は、各接続パッド204の少なくとも一部をあらわにする複数のコンタクト開口部を有する。不活性化層206を、シリコン酸化層、シリコン窒化層、シリコン酸窒化層若しくは高分子材料で形成される誘電層、又は他の適切な誘電材料とすることができる。導電コネクタ208は、導電パッド204上に配置される。例えば、導電コネクタ208は、不活性化層206のコンタクト開口部内へ延在して、導電パッド204と電気的に接続することができる。ある実施形態では、導電ポスト208aを導電パッド204上にメッキすることができる。メッキプロセスは例えば、電気メッキ、無電解メッキ又は浸漬メッキ等である。導電コネクタ208は、導電ポスト、導電ピラー又は導電バンプの形状をとることができる。導電コネクタ208の材料は、銅、アルミニウム、スズ、金、銀若しくはこれらの合金又は他の適切な導電材料を含む。
ある実施形態では、各ダイ200は、有効面200aと、有効面200aの反対側の裏面200bとを有する。図1Bに示すように、ダイ200は、表を上にして配置される。言い換えれば、ダイ200の有効面200aは、キャリア100から離れる方向を向く一方、ダイ200の裏面200bはキャリア100の方を向く。ある実施形態では、接着層400を通じてダイ200をキャリア100に取付けることができる。例えば、接着層400がダイ200の半導体基板202と剥離層102との間に挟まれるように、接着層400をダイ200の裏面200b上に配置することができる。接着層400は、ダイ200と剥離層102との間の接着性を一時的に高めて、ダイが変位することを妨げることができる。ある実施形態では、接着層400をドライフィルムとすることができ、接着層400をラミネーションプロセスによって剥離層102に接着することができる。あるいは、接着層400の溶液(液体型)を剥離層102上にコーティングプロセスによって覆うことができる。続いて、溶液を乾燥させ硬化させて、接着層400の固体層を形成する。接着層400をBステージ状材料で製造することができる。例えば、接着層400は、ダイアタッチフィルム(DAF)を構成する樹脂を含むことができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、接着性を有する他の材料を接着層400用の材料として適合させることができる。ある実施形態では、接着層400は省略可能である。接着層400を利用していないときに、ダイ200を剥離層102上に直接取付けることができる。
図1Bに示すように、接続モジュール300を少なくとも1つのダイ200の外周に沿って配置する。それぞれの接続モジュール300は、複数の導電バー302と、複数のバリア層304と、複数の導電キャップ306と、保護層308とを含む。導電バー302を円柱状カラムとして成形することができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電バー302は多角柱状又は他の適切な形状をとることができる。導電ポストバー302の材料は、銅、アルミニウム、ニッケル、スズ、金、銀又はこれらの合金等を含む。導電キャップ306は、導電バー302上に対応して配置される。導電キャップ306は、導電バー302上に配置されて、接続モジュール300の続いて形成される他の要素との電気的接続性及びワイヤボンディング性を更に高める。ある実施形態では、導電キャップ306の材料は、導電バー302の材料とは異なる。例えば、導電キャップ306は、金、又は電気伝導性に優れワイヤボンディング性が良好な他の金属材料を含むことができる。いくつかの実施形態では、バリア層304は、ニッケル、はんだ、銀又は他の適切な導電材料を含むことができる。それぞれのバリア層304が、導電キャップ306と導電バー302との間に挟まれて、導電キャップ306と導電バー302との間の原子の拡散を妨げる。例えば、導電バー302、バリア層304及び導電キャップ306がそれぞれ、銅、ニッケル及び金で製造されるときには、ニッケルで製造されるバリア層304は、導電バー302の銅原子が導電キャップ306に拡散することを妨げることができる。導電キャップ306が銅で汚染されると、導電キャップ306が酸化しやすくなり、そのためワイヤボンディング性が悪化する。しかしながら、バリア層304によって、上述した悪影響を十分に抑えることができる。ある実施形態では、導電バー302が後に形成される構成要素と既に十分なワイヤボンディング性を有しているときに、導電キャップ306及びバリア層304を省略することができる。
図1Bに示すように、導電バー302、バリア層304及び導電キャップ306は、保護層308に埋め込まれる。しかしながら、保護層308は、それぞれの導電バー302の少なくとも一部と、それぞれの導電キャップ306の少なくとも一部とを露出させる。例えば、保護層308は、導電バー302、バリア層304及び導電キャップ306を横方向にカプセル化することができる。その一方で、保護層308は、導電バー302の表面302aを露出させることができる。ある実施形態では、導電バー302の表面302aは、保護層308の第1面308aに対して実質的に同一平面上に存在することができる。同様に、保護層308は、導電キャップ306の表面306bも露出させる。すなわち、導電キャップ306の表面306bは、保護層308の第2面308b(保護層308の第1面308aとは反対側の面)に対して実質的に同一平面上に存在する。なお、図1Bに表す構成は、単なる例示的イラストレーションとして役立つものであり、本開示はこの構成に限定されるものではない。ある代替的実施形態では、保護層308は、導電バー302があらわにならないように、導電バー302の表面302aを覆うことができる。言い換えれば、保護層308の第1面308aの高さが導電バー302の上面302aの高さよりも高くなるように、保護層308の第1面308aを位置付けることができる。ある実施形態では、保護層308の材料は、ポリマー、エポキシ、成形コンパウンド又は他の適切な誘電材料を含む。
ある実施形態では、接続モジュール300をキャリア100上に設置する前に、接続モジュール300を前もって製造する。ある実施形態では、つまみ上げ配置プロセスによって、接続モジュール300をキャリア100上に設置することができる。例えば、ダイボンダ、チップソータ又はSMT(表面実装技術)機械によって、接続モジュール300をつまみ上げてキャリア100及び剥離層102の上に配置する。図1Bに示すように、導電キャップ306がキャリア100に面するように、接続モジュール300を設置する。すなわち、接続モジュール300は、導電キャップ306が導電バー302よりもキャリア100に近くなるように設置される。各接続モジュール300内の導電バー302の数は、設計要件によって変わり得る。平面視(図示せず)で、保護層308内に導電バー302を分布させて、導電バー同士の電気的絶縁を効果的に維持しながら、導電バー302同士の距離を最小化する。ある実施形態では、接続モジュール300を、平面視で正方形状、矩形状、リング形状又は他の幾何学的形状とすることができる。
図1Cを参照して、絶縁材512をキャリア100及び剥離層102の上に形成して、ダイ200及び接続モジュール300を覆う。言い換えれば、絶縁材512は、ダイ200及び接続モジュール300をカプセル化する。ある実施形態では、絶縁材512の材料を、接続モジュール300の保護層308の材料とは異なる材料とすることができる。例えば、絶縁材512は、成形プロセスによって形成される成形コンパウンド、又はエポキシ、シリコーン若しくは他の適切な樹脂等の絶縁材を含むことができる。ある実施形態では、ダイ200及び接続モジュール300があらわにならないように、絶縁材512をオーバーモールドプロセスによって成形する。例えば、図1Cに示すように、絶縁材512の上面512aの高さが、保護層308の第1面308aの高さ、導電バー302の表面302aの高さ及び導電コネクタ208の上面208aの高さよりも高くなるように、絶縁材512の上面512aを位置付ける。
図1Dを参照して、絶縁材512の厚さを薄くして、第1絶縁カプセル材510を形成する。例えば、ダイ200の導電コネクタ208と接続モジュール300の導電バー302との両方が露出するまで、絶縁材512の一部を除去する。ある実施形態では、平坦化プロセスによって絶縁材512を除去することができる。平坦化プロセスは例えば、化学機械研磨(CMP)、機械的研磨、エッチング又は他の適切なプロセスを含む。ある実施形態では、平坦化プロセスにおいて、接続モジュール300、絶縁材512及びダイ200を更に研磨して、後に形成するパッケージ構造体10の全厚を薄くすることができる。平坦化プロセス後、第1絶縁カプセル材510をキャリア100及び剥離層102の上に形成して、ダイ200及び接続モジュール300を横方向にカプセル化する。ある実施形態では、保護層308の第1面308aと、第1絶縁カプセル材510の第1面510aと、導電バー302の表面302aと、導電コネクタ208の上面208aとは実質的に互いに同一平面上に存在する。上述したように、第1絶縁カプセル材510及び接続モジュール300の保護層308は、異なる材料で製造されるため、第1絶縁カプセル材510及び保護層308は2つの別個の層として考えられる。言い換えれば、第1絶縁カプセル材510と保護層308との間には、はっきりした境界面が見られ得る。
図1Eを参照して、ダイ200、接続モジュール300及び第1絶縁カプセル材510の上に再分配構造体600を形成する。再分配構造体600は、少なくとも一層の誘電層602と、複数の導電パターン604と、複数の導電ビア606とを含み得る。スピンオンコーティング、化学蒸着(CVD)又はプラズマCVD(PECVD)等の適切な製造技術で誘電層602を形成することができる。誘電層602を、シリコン酸化物、シリコン窒化物、炭化珪素、オキシ窒化ケイ素、ポリイミド又はベンゾシクロブテン(BCB)等の、無機又は有機誘電材料で製造することができる。他方では、導電パターン604及び導電ビア606を、スパッタリング、エバポレーション、無電解メッキ又は電気メッキによって形成することができる。導電パターン604及び導電ビア606は、誘電層602に埋め込まれる。誘電層602及び導電パターン604を交互に積層することができる。導電ビア606は、誘電層602を貫通し、導電パターン604を互いに電気的に接続する。導電パターン604及び導電ビア606を、銅、アルミニウム、ニッケル、金、銀、スズ若しくはこれらの組み合わせ、銅/ニッケル/金の複合構造又は他の適切な導電材料で製造し得る。
図1Eに示すように、再分配層600は4つの誘電層602を含む。しかしながら、誘電層602の数は限定されず、回路設計に基づいて誘電層の数を調節することができる。底部誘電層602は、接続モジュール300の導電バー302とダイ200の導電コネクタ208とを部分的に露出させる複数のコンタクト開口部602aを有し得る。コンタクト開口部602aに配置される導電ビア606を、接続モジュール300の導電バー302及びダイ200の導電コネクタ208と直接接触させることができる。言い換えれば、ダイ200の導電コネクタ208は、再分配構造体600と直接接触して、ダイ200と再分配構造体600との間を電気的に接続する。また同様に、接続モジュール300の導電バー302は、再分配構造体600と直接接触して、接続モジュール300と再分配構造体600との間を電気的に接続する。導電ビア606を通じて底部導電パターン604を他の導電パターン604(例えば中間部導電パターン604)に電気的に接続できるように、中間部誘電層602は底部導電パターン604の一部を露出させる。上部誘電層602は、中間部導電パターン604の一部を露出させる複数のコンタクト開口部602bを有する。上部導電ビア606は、コンタクト開口部602b内へ延在して、上部導電パターン604と中間部導電パターン604との間を電気的に接続することができる。他方では、上部導電パターン604を、後のプロセスで電気的に接続するために、上部誘電層602上に配置する。ある実施形態では、上部導電パターン604を、アンダーバンプ金属メタライゼーション(UBM)パターンと呼ぶことができる。
ある実施形態では、再分配構造体600を使用して、ダイ200への又はダイ200からの電気信号の経路を変えることができ、再分配構造体600は、ダイ200よりも広い領域に拡張することができる。したがって、ある実施形態では、再分配構造体600を「ファンアウト再分配構造体」と呼ぶことができる。
図1Fを参照して、剥離層102及びキャリア100をダイ200、接続モジュール300、接着層400及び第1絶縁カプセル材510から除去する。上述したように、剥離層102をLTHC層とすることができる。紫外レーザ光線を露光した後に、剥離層102及びキャリア100を、接続モジュール300の導電キャップ306及び保護層308、接着層400並びに第1絶縁カプセル材510から剥がして分離することができる。キャリア100及び剥離層102を除去すると、保護層308の第2面308b、導電キャップ306の面306b及び第1絶縁カプセル材510の第2面510b(第1絶縁カプセル材510の第1面510aとは反対側の面)が露出する。図1Fに示すように、導電キャップ306の面306b、保護層308の第2面308b及び第1絶縁カプセル材510の第2面510bは実質的に、互いに同一平面上に存在する。
図1Gを参照して、図1Fに示す構造体の上下をひっくり返して、ダイ200、接続モジュール300及び第1絶縁カプセル材510が再分配構造体600の上/上方に配置されることを表す。その後、チップ積層体710を、ダイ200及び第1絶縁カプセル材510の再分配構造体600とは反対側に配置する。例えば、チップ積層体710を、接着層400及び第1絶縁カプセル材510の第2面510bの上に設置することができる。すなわち、接着層400をチップ積層体710とダイ200の裏面200bとの間に挟む。ある実施形態では、チップ積層体710を、互いに積層される複数のチップによって構成することができる。チップは、NANDフラッシュ等の不揮発性メモリーを有するメモリチップを含み得る。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、チップ積層体710のチップを、論理機能又は演算機能等の他の機能を実施できるチップとすることができる。チップ積層体710の隣接する2つのチップ間に、これら2つのチップ間の付着性を高めるためのチップ装着層が見られ得る。
チップ積層体700を、複数の導電線720によって、接続モジュール300の導電キャップ306に電気的に接続することができる。例えば、チップ積層体710を接着層400及び第1絶縁カプセル材510の上に配置した後に、複数の導電線720をワイヤボンディングプロセスによって形成することができる。導電線720の一端部は、チップ積層体710の少なくとも1つのチップに接続される。他方では、導電線720の他端部は、導電キャップ306の面306bと接続される。導電線720の材料は、金、アルミニウム又は他の適切な導電材料を含み得る。ある実施形態では、導電線720の材料は、導電キャップ306の材料と同じである。
図1Hを参照して、第2絶縁カプセル材520を、第1絶縁カプセル材510及び接続モジュール300の上に形成して、チップ積層体710及び導電線720をカプセル化する。第2絶縁カプセル材520の材料を、第1絶縁カプセル材510と同じ材料とすることができ、又は第1絶縁カプセル材510とは異なる材料とすることができる。例えば、第2絶縁カプセル材520の材料は、エポキシ、成形コンパウンド又は他の適切な絶縁材を含むことができる。ある実施形態では、第2絶縁カプセル材520の材料の吸湿度を低くすることができる。第2絶縁カプセル材520を、圧縮成形、トランスファー成型又は他のカプセル化プロセスによって形成することができる。第2絶縁カプセル材520は、チップ積層体710及び導電線720に対して、物理的支持、機械的保護並びに電気的絶縁及び環境的分離をもたらす。言い換えれば、チップ積層体710及び導電線720は、第2絶縁カプセル材520に埋め込まれる。
図1Iを参照して、複数の導電端子800が、再分配構造体600のダイ200及び接続モジュール300とは反対側に形成される。ある実施形態では、導電端子800は、再分配構造体600のUBMパターン(図1Iに表す底部導電パターン604)上に配置される。導電端子800を、ボール載置プロセス及び/又はリフロープロセスによって形成することができる。導電端子800を、はんだボール等の導電バンプとすることができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電端子800は、設計要件に基づいて他の可能な形態及び形状をとることができる。例えば、導電端子800は、導電ピラー又は導電ポストの形状をとることができる。
図1Jを参照して、導電端子800を形成した後に、シンギュレーションプロセスを行って、複数のパッケージ構造体10を得る。シンギュレーションプロセスは例えば、回転ブレード又はレーザ光線を用いた切断を含む。
上記記載に基づいて、すぐに利用できる、前もって製造された接続モジュールは、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。接続モジュールの厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、接続モジュールの適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
本発明の範囲又は精神から離れることなく、本明細書で開示される実施形態及び概念に対して様々な変更及び変形を加えることができることが、当業者にとって明らかであろう。前述したことを考慮して、本発明の変更又は変形は、特許請求の範囲及び特許請求の範囲の均等物に該当するときには、本開示に含まれることを意図する。
本開示は、パッケージ構造体及びパッケージ構造体の製造方法を提供する。パッケージ構造体を、電気製品で利用することができる。本開示の小型化されるパッケージ構造体を利用することで、電気製品のサイズを十分に減少させることができる。
10:パッケージ構造体
100:キャリア
102:剥離層
200:ダイ
200a:有効面
200b:裏面
202:半導体基板
204:導電パッド
206:不活性化層
208:導電コネクタ
208a、512a:上面
300:接続モジュール
302:導電バー
302a,306b:表面
304:バリア層
306:導電キャップ
308:保護層
308a、510a:第1面
308b、510b:第2面
400:接着層
510:第1絶縁カプセル材
512:絶縁材
520:第2絶縁カプセル材
600:再分配構造体
602:誘電層
602a、602b:コンタクト開口部
604:導電パターン
606:導電ビア
710:チップ積層体
720:導電線
800:導電端子

Claims (17)

  1. 再分配構造体と、
    前記再分配構造体上に配置され、前記再分配構造体に電気的に接続されるダイと、
    前記再分配構造体上に配置され、保護層及び前記保護層に埋め込まれる複数の導電バーを含む少なくとも1つの、平面視で正方形状または矩形状の接続モジュールと、
    前記ダイ及び前記接続モジュールをカプセル化する第1絶縁カプセル材と、
    前記第1絶縁カプセル材及び前記ダイの上に配置され、前記接続モジュールに電気的に接続されるチップ積層体と、
    前記チップ積層体をカプセル化する第2絶縁カプセル材と、
    を備え
    前記接続モジュールは、導電バー上に対応して配置される複数の導電キャップを更に備え、
    前記保護層は、それぞれの導電キャップの少なくとも一部を露出させ、
    前記導電キャップの表面と、前記保護層の表面と、前記第1絶縁カプセル材の表面とは、実質的に同一平面上に存在する、パッケージ構造体。
  2. 前記再分配構造体の前記ダイ及び前記接続モジュールとは反対側に配置される複数の導電端子を更に備える、請求項1に記載のパッケージ構造体。
  3. 前記ダイは有効面及び前記有効面とは反対側の裏面とを有し、前記ダイは前記有効面上に位置付けられる複数の導電コネクタを備え、前記導電コネクタは前記再分配構造体と直接接触する、請求項1に記載のパッケージ構造体。
  4. 前記ダイの前記裏面と前記チップ積層体との間に挟まれる接着層を更に含む、請求項3に記載のパッケージ構造体。
  5. 前記保護層の材料が前記第1絶縁カプセル材の材料とは異なる、請求項1に記載のパッケージ構造体。
  6. 前記第2絶縁カプセル材に埋め込まれる複数の導電線を更に備え、
    前記チップ積層体は前記導電線を通じて前記接続モジュールに電気的に接続される、請求項1に記載のパッケージ構造体。
  7. 前記導電キャップの材料は金を含む、請求項に記載のパッケージ構造体。
  8. 前記導電バーの材料は、前記導電キャップの材料とは異なる、請求項に記載のパッケージ構造体。
  9. キャリアを提供するキャリア提供ステップと、
    複数のダイ及び複数の平面視で正方形状または矩形状の接続モジュールを前記キャリア上に配置する配置ステップと、
    第1絶縁カプセル材を前記キャリア上に形成して前記ダイ及び前記接続モジュールをカプセル化する第1絶縁カプセル材形成ステップと、
    前記ダイ、前記接続モジュール及び前記第1絶縁カプセル材の上に再分配構造体を形成する再分配構造体形成ステップと、
    前記キャリアを、前記ダイ、前記接続モジュール及び前記第1絶縁カプセル材から除去する除去ステップと、
    前記接続モジュールに電気的に接続されるチップ積層体を、前記ダイ及び前記第1絶縁カプセル材の、前記再分配構造体とは反対側に配置するチップ積層体配置ステップと、
    前記チップ積層体を第2絶縁カプセル材によってカプセル化するチップ積層体カプセル化ステップと、
    を含む、パッケージ構造体の製造方法であり、
    前記接続モジュールのそれぞれは保護層と、前記保護層に埋め込まれる複数の導電バーとを含み、
    前記ダイは、有効面と前記有効面とは反対側の裏面とを有し、
    前記ダイは、前記有効面上に位置付けられる複数の導電コネクタを備え、
    前記第1絶縁カプセル材形成ステップは、絶縁材をキャリア上に形成して前記ダイ及び前記接続モジュールを被覆するステップと、前記絶縁材の一部を除去して前記ダイの前記導電コネクタ及び前記接続モジュールの前記導電バーを露出させるステップと、を含む、パッケージ構造体の製造方法。
  10. 複数の導電端子を前記再分配構造体の前記ダイ及び前記接続モジュールとは反対側に形成するステップを更に含む、請求項に記載のパッケージ構造体の製造方法。
  11. 前記第2絶縁カプセル材に埋め込まれる複数の導電線を形成するステップを更に含み、
    前記チップ積層体は前記導電線を通じて前記接続モジュールに電気的に接続される、請求項に記載のパッケージ構造体の製造方法。
  12. シンギュレーションプロセスを行うステップを更に備える、請求項に記載のパッケージ構造体の製造方法。
  13. 前記保護層の材料は、前記第1絶縁カプセル材の材料とは異なる、請求項に記載のパッケージ構造体の製造方法。
  14. 前記接続モジュールはつまみ上げ配置プロセスによって前記キャリア上に配置される、請求項に記載のパッケージ構造体の製造方法。
  15. それぞれの接続モジュールは前記導電バー上に対応して配置される複数の導電キャップを更に備え、前記保護層はそれぞれの導電キャップの少なくとも一部を露出させる、請求項に記載のパッケージ構造体の製造方法。
  16. 前記導電キャップが前記キャリアに面するように、前記接続モジュールは前記キャリア上に配置される、請求項15に記載のパッケージ構造体の製造方法。
  17. 前記導電キャップの材料は金を含む、請求項15に記載のパッケージ構造体の製造方法。
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