TWI691029B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI691029B
TWI691029B TW107141331A TW107141331A TWI691029B TW I691029 B TWI691029 B TW I691029B TW 107141331 A TW107141331 A TW 107141331A TW 107141331 A TW107141331 A TW 107141331A TW I691029 B TWI691029 B TW I691029B
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Taiwan
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conductive
die
protective layer
insulating
sealing body
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TW107141331A
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TW201937667A (zh
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張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Wire Bonding (AREA)

Abstract

一種封裝結構包括重佈線路結構、晶粒、至少一連接模組、第一絕緣密封體、堆疊晶片以及第二絕緣密封體。晶粒配置並電性連接至重佈線路結構。連接模組配置於重佈線路結構上。連接模組包括保護層以及嵌入保護層中的多個導電條。第一絕緣密封體密封晶粒與連接模組。堆疊晶片配置於第一絕緣密封體與晶粒上。堆疊晶片電性連接至連接模組。第二絕緣密封體密封堆疊晶片。另提供一種封裝結構的製造方法。

Description

封裝結構及其製造方法
本發明通常是有關於一種封裝結構及其製造方法，且特別是有關於一種具有連接模組（connecting module）的封裝結構及其製造方法。
在近年來的半導體封裝技術的研究中已經開始關注於發展具有小體積、重量輕、高密度以及低製造成本的產品。對於多功能半導體封裝而言，已經使用一種用於堆疊晶片的技術，以提供封裝具有較大的儲存或執行數據的容量。在對具有改進期望特徵的多功能電子元件的需求快速增加下，實為本領域的技術人員的一大挑戰。
本發明提供一種封裝結構及其製造方法，可以在較低的製造成本下有效地減少封裝結構的高度。
本發明的封裝結構包括重佈線路結構、晶粒、至少一連接模組、第一絕緣密封體、堆疊晶片以及第二絕緣密封體。晶粒配置並電性連接至重佈線路結構。連接模組配置於重佈線路結構上。連接模組包括保護層以及嵌入保護層中的多個導電條。第一絕緣密封體密封晶粒與連接模組。堆疊晶片配置於第一絕緣密封體與晶粒上。堆疊晶片電性連接至連接模組。第二絕緣密封體密封堆疊晶片。
在本發明的一實施例中，前述的封裝結構更包括黏著層。黏著層夾於所述晶粒的背面與堆疊晶片之間。
在本發明的一實施例中，前述的多個導電帽的材料包括金。
本發明提供一種封裝結構的製造方法。製造方法至少包括以下步驟。提供載板。配置多個晶粒以及多個連接模組於載板上。每一所述連接模組包括保護層以及多個嵌入所述保護層中的導電條。於載板上形成第一絕緣密封體，以密封多個晶粒與多個連接模組。於多個晶粒、多個連接模組以及第一絕緣密封體上形成重佈線路結構。從多個晶粒、連接模組以及第一絕緣密封體上移除載板。於多個晶粒與相對於重佈線路結構的第一絕緣密封體上配置堆疊晶片。堆疊晶片電性連接至多個連接模組。藉由第二密封體密封堆疊晶片。
在本發明的一實施例中，前述的製造方法更包括形成多個導電端子於相對於多個晶粒與多個連接模組的重佈線路結構上。
在本發明的一實施例中，前述的製造方法更包括執行切割製程。
基於上述，容易預先製造的連接模組可以作為封裝結構內的垂直連接特徵。由於連接模組的厚度小，進而可以有效地縮小封裝結構的尺寸。此外，連接模組的使用可以導致在傳統封裝結構中免除額外的載板或較厚的銅柱，進而降低製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
下文將會附加標號以對本發明較佳實施例進行詳細描述，並以圖式說明。在可能的情況下，相同或相似的構件在圖式中將以相同的標號顯示。
圖1A至圖1J是依據本發明一些實施例的封裝結構10的製造方法的剖面示意圖。請參照圖1A，提供具有離型層102形成於其上的載板100。載板100可以是玻璃基板或玻璃支撐板。然而，本發明不限於此。其他合適的基板材料也可以被使用，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。離型層102可以包括光熱轉換（light to heat conversion, LTHC）材料、環氧樹脂（epoxy resin）、無機材料、有機聚合物材料或其他適宜的黏著材料。然而，本發明不限於此。在一些替代實施例中，可以使用其他適宜的離型層。
請參照圖1B，於離型層102與載板100上配置多個晶粒200以及多個連接模組300。晶粒200可以包括數位晶粒、類比晶粒或混合訊號晶粒。舉例而言，晶粒200可以是特殊應用積體電路（Application-Specific Integrated Circuit, ASIC）晶粒、邏輯晶粒，或其他適宜的晶粒。每一晶粒200包括半導體基板202、多個導電接墊204、鈍化層206以及多個導電連接器208。在一些實施例中，半導體基板202可以是包括主動元件（如電晶體或其他類似者）的矽基板，以及可以選擇性地形成被動元件（如電阻、電容、電感或其他類似者）於其中。導電接墊204分佈於半導體基板202上。導電接墊204可以包括鋁接墊、銅接墊或其他適宜的金屬接墊。於半導體基板202上形成鈍化層206，以部分覆蓋每一導電接墊204。換句話說，鈍化層206具有多個接觸開口，暴露出每一導電接墊204的至少一部分。鈍化層206可以是氧化矽層、氮化矽層、氮氧化矽層或是由其他適宜的聚合物材料或介電材料所形成的介電層。於導電接墊204上配置導電連接器208。舉例而言，導電連接器208可以延伸至鈍化層206的接觸開口中，以提供與導電接墊204的電性連接。在一些實施例中，可以於導電接墊204上電鍍導電連接器208。電鍍製程是，舉例而言，電鍍、化學鍍、浸鍍（immersion plating）或其他類似者。導電連接器208可以採用導電栓塞（conductive posts）、導電柱或導電凸塊的形式。導電連接器208的材料包括銅、鋁、錫、金、銀、上述之合金或其他適宜的導電材料。
在一些實施例中，每一晶粒200具有主動面200a以及相對於主動面200a的背面200b。如圖1B所示，以面朝上的方式配置晶粒200。換句話說，晶粒200的主動面200a從載板100上遠離，而晶粒200的背面200b面向載板100。在一些實施例中，晶粒200可以經由黏著層400附接在載板100上。舉例而言，可以於晶粒200的背面200b配置黏著層400，使得黏著層400夾於晶粒200的半導體基板202與離型層102之間。黏著層400可以暫時增強晶粒200與離型層102之間的黏著力，以防止晶粒位移。在一些實施例中，黏著層400可以為乾膜，且可以經由層壓製程（lamination process）黏著於離型層102上。或者，可以經由塗佈製程將黏著層400（液體形式）的溶液塗佈至離型層102上。接著，將溶液乾燥或固化，以形成黏著層400的固體層。黏著層400可以由B階（B-stage）材料所製成，舉例而言，黏著層400可以包括由樹脂構成的晶粒黏著膜（die attach film, DAF）。然而，本發明不限於此。在一些替代實施例中，可以使用其他具有黏著特性的材料來作為黏著層400的材料。在一些實施例中，黏著層400為可選的。當未使用黏著層400時，晶粒200可以直接附接於離型層102上。
如圖1B所示，沿至少一晶粒200的周圍配置連接模組300。每一連接模組300包括多個導電條302、多個阻障層304、多個導電帽306以及保護層308。導電條302可以形成圓柱形的形狀。然而，本發明不限於此。在一些替代性實施例中，導電條302可以使用多邊形柱或其他適宜的形狀。導電條302的材料包括銅、鋁、鎳、錫、金、銀、上述之合金、或其他類似者。於導電條302上對應配置導電帽306。於導電條302上配置導電帽306以進一步提升連接模組300與其他隨後形成元件之間的電性連接與導線接合能力。在一些實施例中，導電帽306的材料與導電條302的材料不同。舉例而言，導電帽306可以包括金或其他具有優異電性連接能力以及良好導線接合能力的金屬材料。在一些實施例中，阻障層304可以包括鎳、焊料、銀或其他適宜的導電材料。每一阻障層304夾於導電帽306與導電條302之間，以防止導電帽306與導電條302之間的原子擴散。舉例而言，當導電條302、阻障層304以及導電帽306分別由銅、鎳以及金所製成時，由鎳所形成的阻障層304可以防止導電條302中的銅原子從導電條302擴散至導電帽306中。導電帽306被銅汙染後會導致導電帽306容易氧化，進而導致導線接合能力變差。然而，藉由阻障層304的輔助，可以充分防止上述不利的影響。在一些實施例中，如果導電條302已經具有充分的導線接合能力接合隨後形成的元件，則可以省略導電帽306以及阻障層304。
如圖1B所示，導電條302、阻障層304以及導電帽306嵌入保護層308中。然而，保護層308暴露出每一導電條302的至少一部分以及每一導電帽306的至少一部分。舉例而言，保護層308可以側向密封導電條302、阻障層304以及導電帽306。同時，可以藉由保護層308將導電條302的表面302a暴露出來。在一些實施例中，導電條302的表面302a實質上與保護層308的第一表面308a共面（coplanar）。類似地，可以藉由保護層308將導電帽306的表面306b暴露出來。也就是說，導電帽306的表面306b實質上與保護層308的第二表面308b（保護層308中相對於第一表面308a的表面）共面。應注意的是，圖1B中的配置僅為示例性繪示，而本發明不限於此。在一些替代實施例中，保護層308可以覆蓋導電條302的表面302a，使得導電條302未被暴露出來。換句話說，保護層308的第一表面308a可以位於比導電條302的頂表面302a還要高的高度。在一些實施例中，保護層308的材料包括聚合物、環氧樹脂、模塑化合物或其他適宜的介電材料。
在一些實施例中，預先製造連接模組300，在其放置於載板100上之前。在一些實施例中，可以藉由取放製程（pick-and-place process）將連接模組300放置於載板100上。舉例而言，可以藉由晶粒接合器（die bonder）、晶片分揀機（chip sorter）或表面黏著技術（Surface Mount Technology, SMT）機器於載板100及離型層102上取放（pick-and-place）連接模組300。如圖1B所示，以導電帽306面向載板100的方式放置連接模組300。也就是說，以導電帽306比導電條302更靠近載板100的方式放置連接模組300。每一連接模組300中的導電條302的數量可以依設計需求而調整。從上方來看（未繪示），導電條302分佈於保護層308中，使得導電條302之間的距離最小化，並同時維持導電條302之間有效的電性隔離。在一些實施例中，從上方來看，連接模組300可以呈現正方形形狀、矩形形狀、環形形狀或其他幾何形狀。
請參照圖1C，於載板100與離型層102上形成絕緣材料512，以覆蓋晶粒200與連接模組300。換句話說，絕緣材料512密封晶粒200與連接模組300。在一些實施例中，絕緣材料512的材料可以與連接模組300的保護層308的材料不同。舉例而言，絕緣材料512可以包括藉由模塑製程形成的模塑化合物或絕緣材料如環氧樹脂、矽基樹脂（silicone）或其他適宜的樹脂。在一些實施例中，藉由覆蓋成型製程（over-molding process）形成絕緣材料512，使得晶粒200與連接模組300沒有被暴露出來。舉例而言，如圖1C所示，絕緣材料512的頂表面512a位於比保護層308的第一表面308a、導電條302的表面302a以及導電連接器208的頂表面208a還要高的高度。
請參照圖1D，減少絕緣材料512的厚度，以形成第一絕緣密封體510。舉例而言，移除部分的絕緣材料512直到晶粒200的導電連接器208以及連接模組300的導電條302此兩者被暴露出來。在一些實施例中，可以經由平坦化製程移除絕緣材料512。平坦化製程包括，舉例而言，化學機械研磨製程（chemical-mechanical polishing, CMP）、機械研磨製程（mechanical grinding process）、蝕刻或其他適宜的製程。在一些實施例中，平坦化製程可以更進一步研磨連接模組300、絕緣材料512以及晶粒200，以減少隨後形成的封裝結構10的整體厚度。在平坦化製程後，於載板100與離型層102上形成第一絕緣密封體510，以側向密封晶粒200以及連接模組300。在一些實施例中，保護層308的第一表面308a、第一絕緣密封體510的第一表面510a、導電條302的表面302a以及導電連接器208的頂表面208a相互實質上共面。如上面所提到，由於第一絕緣密封體510與連接模組300的保護層308由不同材料所製成，第一絕緣密封體510與保護層308被視為是兩個不同的層。換句話說，可以於第一絕緣密封體510與保護層308之間看見清楚的介面。
請參照圖1E，於晶粒200、連接模組300以及第一絕緣密封體510上形成重佈線路結構600。重佈線路結構600可以包括至少一介電層602、多個導電圖案604以及多個導通孔606。可以藉由適宜的製造技術如旋轉塗佈（spin-on coating）、化學氣相沉積（chemical vapor deposition, CVD）、電漿輔助化學氣相沉積（plasma-enhanced chemical vapor deposition, PECVD）或其他類似者，以形成介電層602。介電層602可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯（benzocyclobutene, BCB）或其他類似者等的非有機或有機介電材料所製成。另一方面，可以藉由濺鍍、蒸鍍、化學鍍（electro-less plating）或電鍍來形成導電圖案604以及導通孔606。導電圖案604以及導通孔606嵌入介電層602中。介電層602與導電圖案604可以交替堆疊。導通孔606穿過介電層602，以與導電圖案604相互電性連接。導電圖案604與導通孔606可以由銅、鋁、鎳、金、銀、錫、上述之組合、銅/鎳/金之複合結構，或其他適宜的導電材料所組成。
如圖1E所示，重佈線路結構600包括四個介電層602，然而，本發明對於介電層602的數量並不加以限制，並且可以基於電路的設計而進行調整。最下介電層602可以具有多個接觸開口602a。多個接觸開口602a部分暴露出連接模組300的導電條302與晶粒200的導電連接器208。導通孔606配置於接觸開口602a中可以與連接模組300的導電條302以及晶粒200的導電連接器208直接接觸。換句話說，晶粒200的導電連接器208與重佈線路結構600直接接觸，以提供晶粒200與重佈線路結構600之間的電性連接。類似地，連接模組300的導電條302也與重佈線路結構600直接接觸，以提供連接模組300與重佈線路結構600之間的電性連接。中間介電層602暴露出部分的最下導電圖案604，使得最下導電圖案604可以經由導通孔606與其他導電圖案604（舉例而言，中間導電圖案604）電性連接。最上介電層602具有多個接觸開口602b。多個接觸開口602b暴露出部分的中間導電圖案604。最上導通孔606可以延伸至接觸開口602b，以與最上導電圖案604以及中間導電圖案604電性連接。另一方面，為了後續製程中的電性連接，於最上介電層602上配置最上導電圖案604。在一些實施例中，最上導電圖案604可以被稱為凸塊底金屬（under-ball metallization, UBM）圖案。
在一些實施例中，重佈線路結構600可以被用於將電路訊號重新分佈至晶粒200，或從晶粒200將電路訊號重新分佈出去，且可以在比晶粒200更寬的區域中擴展。因此，在一些實施例中，重佈線路結構600可以被稱為是扇出式（fan-out）重佈線路結構。
請參照圖1F，從晶粒200、連接模組300、黏著層400以及第一絕緣密封體510上移除離型層102以及載板100。如上面所提到，離型層102可以是光熱轉換層。在暴露於UV雷射下，離型層102與載板100可以從導電帽306、連接模組300的保護層308、黏著層400以及第一絕緣密封體510上被剝離分開。在移除載板100與離型層102時，暴露出保護層308的第二表面308b、導電帽306的表面306b以及第一絕緣密封體510的第二表面510b（第一絕緣密封體510中相對於第一表面510a的表面）。如圖1F所示，導電帽306的表面306b、保護層308的第二表面308b以及第一絕緣密封體510的第二表面510b實質上相互共面。
請參照圖1G，將圖1F所繪示的結構上下翻轉，使得晶粒200、連接模組300以及第一絕緣密封體510顯示為配置於重佈線路結構600上/上方。之後，於晶粒200及相對於重佈線路結構600的第一絕緣密封體510上配置堆疊晶片710。舉例而言，可以於黏著層400及第一絕緣密封體510的第二表面510b上放置堆疊晶片710。也就是說，黏著層400夾於堆疊晶片710與晶粒200的背面200b之間。在一些實施例中，可以由多個晶片彼此相互堆疊構成堆疊晶片710。晶片可以包括具有非揮發性記憶體（non-volatile memory）的記憶晶片，如NAND型快閃記憶體（NAND flash）。然而，本發明不限於此。在一些替代性實施例中，堆疊晶片710的晶片可以是能夠執行其他功能的晶片，如邏輯功能、運算功能或其他類似者。在堆疊晶片710中，可以於兩相鄰晶片之間看見晶片黏著層，以增強這些兩相鄰的晶片之間的黏著力。
堆疊晶片710可以經由多條導線720電性連接至連接模組300的導電帽306。舉例而言，在於黏著層400、第一絕緣密封體510上配置堆疊晶片710後，可以經由打線接合製程形成多條導線720。導線720的一端連接至堆疊晶片710的至少一晶片。另一方面，導線720的另一端連接至導電帽306的表面306b。導線720的材料可以包括金、鋁或其他適宜的導電材料。在一些實施例中，導線720的材料與導電帽306的材料相同。
請參照圖1H，於第一絕緣密封體510與連接模組300上形成第二絕緣密封體520，以密封堆疊晶片710以及導線720。第二絕緣密封體520的材料可以與第一絕緣密封體510的材料相同或不同。舉例而言，第二絕緣密封體520的材料可以包括環氧樹脂、模塑化合物或其他適宜的絕緣材料。在一些實施例中，第二絕緣密封體520的材料可以為濕氣吸收率較低的材料。可以藉由壓縮成型（compression molding）、轉注成型（transfer molding）或其他適宜的密封製程形成第二絕緣密封體520。第二絕緣密封體520提供給堆疊晶片710與導線720物理支撐、機械保護以及電性和環境隔離。換句話說，堆疊晶片710與導線720嵌入第二絕緣密封體520中。
請參照圖1I，於相對於晶粒200與連接模組300的重佈線路結構600上形成多個導電端子800。在一些實施例中，於重佈線路結構600的UBM圖案（如圖1I所示的最下導電圖案604）上配置導電端子800。可以藉由植球製程（ball placement process）以及/或回焊製程（reflow process）形成導電端子800。導電端子800可以為導電凸塊，如焊球。然而，本發明不限於此。在一些替代性實施例中，導電端子800可以基於設計需求而使用其他可能的形式或形狀。舉例而言，導電端子800可以使用導電柱或導電栓塞的形式。
請參照圖1J，在形成導電端子800後，進行切割（singulation）製程，以獲得多個封裝結構10。切割製程包括，舉例而言，以旋切刀（rotating blade）或雷射光束切割。
綜上所述，容易預先製造的連接模組可以作為封裝結構內的垂直連接特徵。由於連接模組的厚度小，進而可以有效地縮小封裝結構的尺寸。此外，連接模組的使用可以導致在傳統封裝結構中免除額外的載板或較厚的銅柱，進而降低製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧封裝結構100‧‧‧載板102‧‧‧離型層200‧‧‧晶粒200a‧‧‧主動面200b‧‧‧背面202‧‧‧半導體基板204‧‧‧導電接墊206‧‧‧鈍化層208‧‧‧導電連接器208a、302a、306b、308a、308b、512a、510a、510b‧‧‧表面300‧‧‧連接模組302‧‧‧導電條304‧‧‧阻障層306‧‧‧導電帽308‧‧‧保護層400‧‧‧黏著層510‧‧‧第一絕緣密封體512‧‧‧絕緣材料520‧‧‧第二絕緣密封體600‧‧‧重佈線路結構602‧‧‧介電層602a、602b‧‧‧開口604‧‧‧導電圖案606‧‧‧導通孔710‧‧‧堆疊晶片720‧‧‧導線800‧‧‧導電端子
圖1A至圖1J是依據本發明一些實施例的封裝結構的製造方法的剖面示意圖。
200‧‧‧晶粒
300‧‧‧連接模組
302‧‧‧導電條
304‧‧‧阻障層
306‧‧‧導電帽
308‧‧‧保護層
400‧‧‧黏著層
510‧‧‧第一絕緣密封體
520‧‧‧第二絕緣密封體
600‧‧‧重佈線路結構
602‧‧‧介電層
604‧‧‧導電圖案
606‧‧‧導通孔
710‧‧‧堆疊晶片
720‧‧‧導線
800‧‧‧導電端子

Claims (10)

  1. 一種封裝結構，包括：重佈線路結構；晶粒，配置並電性連接至所述重佈線路結構；至少一連接模組，配置於所述重佈線路結構上，其中所述連接模組包括保護層、多個導電帽、多個阻障層以及多個導電條，其中所述多個阻障層介於所述多個導電帽與所述多個導電條之間，所述多個導電條嵌入所述保護層中，其中所述多個導電條的表面與所述保護層的第一表面共面；第一絕緣密封體，密封所述晶粒與所述連接模組；堆疊晶片，配置於所述第一絕緣密封體與所述晶粒上，所述堆疊晶片電性連接至所述連接模組；以及第二絕緣密封體，密封所述堆疊晶片。
  2. 如申請專利範圍第1項所述的封裝結構，更包括多個導電端子，配置於相對於所述晶粒與所述連接模組的所述重佈線路結構上。
  3. 如申請專利範圍第1項所述的封裝結構，更包括多條導線，嵌入所述第二絕緣密封體中，其中所述堆疊晶片經由所述多條導線電性連接至所述連接模組。
  4. 如申請專利範圍第1項所述的封裝結構，其中所述多個導電帽對應配置於所述多個導電條上，且所述保護層暴露出每一所述導電帽的至少一部分，且： 所述多個導電條的材料與所述多個導電帽的材料不同；或所述多個導電帽的表面、所述保護層的表面以及所述第一絕緣密封體的表面實質上共面。
  5. 如申請專利範圍第1項所述的封裝結構，其中：所述晶粒具有主動面以及相對於所述主動面的背面，所述晶粒包括多個導電連接器，位於所述主動面上，且所述多個導電連接器與所述重佈線路結構直接接觸；或所述保護層的材料與所述第一絕緣密封體的材料不同。
  6. 一種封裝結構的製造方法，包括：提供載板；配置多個晶粒以及多個連接模組於所述載板上，其中每一所述連接模組包括保護層、多個導電帽、多個阻障層以及多個導電條，其中所述多個阻障層介於所述多個導電帽與所述多個導電條之間，所述多個導電條嵌入所述保護層中，其中所述多個導電條的表面與所述保護層的第一表面共面；形成第一絕緣密封體於所述載板上，以密封所述多個晶粒與所述多個連接模組；形成重佈線路結構於所述多個晶粒、所述多個連接模組以及所述第一絕緣密封體上；從所述多個晶粒、所述多個連接模組以及所述第一絕緣密封體上移除所述載板； 配置堆疊晶片於所述多個晶粒與相對於所述重佈線路結構的所述第一絕緣密封體上，其中所述堆疊晶片電性連接至所述多個連接模組；以及藉由第二絕緣密封體密封所述堆疊晶片。
  7. 如申請專利範圍第6項所述的製造方法，更包括形成多條導線嵌入所述第二絕緣密封體中，其中所述堆疊晶片經由所述多條導線電性連接至所述多個連接模組。
  8. 如申請專利範圍第6項所述的製造方法，其中所述多個連接模組經由取放製程配置於所述載板上。
  9. 如申請專利範圍第6項所述的製造方法，其中：所述多個導電帽對應配置於所述多個導電條上，且所述保護層暴露出每一所述導電帽的至少一部分；且所述多個連接模組配置於所述載板上，使得所述多個導電帽面向所述載板。
  10. 如申請專利範圍第6項所述的製造方法，其中所述晶粒具有主動面以及相對於所述主動面的背面，所述晶粒包括多個導電連接器位於所述主動面，且所述第一絕緣密封體的形成步驟包括：形成絕緣材料於所述載板上，以覆蓋所述多個晶粒與所述多個連接模組；以及移除部分的所述絕緣材料，以暴露出所述多個晶粒的所述多個導電連接器與所述多個連接模組的所述多個導電條。
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