TW201926588A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201926588A
TW201926588A TW106143154A TW106143154A TW201926588A TW 201926588 A TW201926588 A TW 201926588A TW 106143154 A TW106143154 A TW 106143154A TW 106143154 A TW106143154 A TW 106143154A TW 201926588 A TW201926588 A TW 201926588A
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Taiwan
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electronic component
block
electronic
item
patent application
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TW106143154A
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English (en)
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TWI631676B (zh
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王伯豪
楊志仁
鄭有志
鄭子企
林長甫
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矽品精密工業股份有限公司
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Priority to TW106143154A priority Critical patent/TWI631676B/zh
Priority to CN201711391764.8A priority patent/CN109904122A/zh
Priority to US15/945,308 priority patent/US10354891B2/en
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Publication of TWI631676B publication Critical patent/TWI631676B/zh
Publication of TW201926588A publication Critical patent/TW201926588A/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

一種電子封裝件及其製法，係於承載結構與複數電子元件之間形成如底膠之填充材，且該填充材於兩電子元件之間的間隙中形成有間隔部，其中，該間隔部包含有相分離的第一區塊與第二區塊以作為應力緩衝區，故於後續研磨包覆該些電子元件之封裝層時，能有效避免該電子元件因研磨外力所產生之應力而發生破裂之問題。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術繁多，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊模組。
第1圖係為習知3D IC式半導體封裝件1之剖面示意圖。首先，提供一具有相對之轉接側10a與置晶側10b之矽中介板(Through Silicon interposer，簡稱TSI)10，且該矽中介板10具有複數連通該置晶側10b與轉接側10a之導電矽穿孔(Through-silicon via，簡稱TSV)100，並於該置晶側10b上形成線路結構101以供接置複數具有銲錫凸塊12之半導體元件11，再以填充材13(如底膠)包 覆該些銲錫凸塊12，並形成封裝層14以包覆該半導體元件11，並研磨該封裝層14，以令該半導體元件11之上表面外露出該封裝層14。接著，將該矽中介板10以其轉接側10a透過複數導電元件15設於一封裝基板16上，並使該封裝基板16電性連接該些導電矽穿孔100，再以底膠17包覆該些導電元件15。接著，形成封裝膠體18於該封裝基板16上，以令該封裝膠體18包覆該封裝層14與該矽中介板10。最後，形成複數銲球160於該封裝基板16之下側，以供接置於一電路板19上。
惟，習知半導體封裝件1中，於封裝時，該填充材13因毛細作用而會形成於各該半導體元件11之間的間隙S中，致使該半導體元件11的內部應力增高，故於研磨該封裝層14時，外部的研磨作用力會傳遞至該半導體元件11中，而造成該半導體元件11之應力集中而發生破裂，導致該半導體封裝件1之可靠度不佳。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載結構；第一電子元件與第二電子元件，係間隔設置於該承載結構上，以令該第一電子元件與該第二電子元件之間形成有一間隙；填充材，係形成於該承載結構與該第一電子元件之間及該承載結構與該第二電子元件之間，且令該填充材於該間隙中形成有間隔部， 其中，該間隔部包含有相分離的第一區塊與第二區塊，且該第一區塊係對應鄰近該第一電子元件，而該第二區塊係對應鄰近該第二電子元件；以及封裝層，係形成於該承載結構上，以包覆該第一電子元件與第二電子元件，且令該第一電子元件與第二電子元件之上表面外露出該封裝層。
本發明復提供一種電子封裝件之製法，係包括：將第一電子元件與第二電子元件間隔設置於承載結構上，以令該第一電子元件與該第二電子元件之間形成有一間隙；形成填充材於該承載結構與該第一電子元件之間及該承載結構與該第二電子元件之間，且令該填充材於該間隙中形成有間隔部，其中，該間隔部包含有相分離的第一區塊與第二區塊，且該第一區塊係對應鄰近該第一電子元件，而該第二區塊係對應鄰近該第二電子元件；以及形成封裝層於該承載結構上，以包覆該第一電子元件與第二電子元件，且令該第一電子元件與第二電子元件之上表面外露出該封裝層。
前述之電子封裝件及其製法中，該承載結構電性連接該第一電子元件及第二電子元件。
前述之電子封裝件及其製法中，該第一電子元件與該第二電子元件係為相同或不同類型。
前述之電子封裝件及其製法中，該第一電子元件係包含有封裝材、結合該封裝材之控制晶片及高頻寬記憶體型晶片。例如，該封裝材與封裝層之材質係不相同。
前述之電子封裝件及其製法中，該第二電子元件係為 特殊應用積體電路型半導體晶片。
前述之電子封裝件及其製法中，該第一區塊之厚度係不同於該第二區塊之厚度。
前述之電子封裝件及其製法中，該第一區塊與該第二區塊之至少一者之厚度係大於或等於30微米。
前述之電子封裝件及其製法中，藉由移除該封裝層之部分材質，使該第一電子元件與該第二電子元件之上表面齊平該封裝層之上表面，以令該第一與第二電子元件外露出該封裝層。
前述之電子封裝件及其製法中，該封裝層復形成於該間隙中及該第一區塊與該第二區塊之間。
由上可知，本發明之電子封裝件及其製法中，主要藉由該填充材於該間隙中形成有相分離的第一區塊與第二區塊，以令第一區塊與第二區塊之間的區域作為應力緩衝區，故相較於習知技術，本發明之製法於移除該封裝層之部分材質時，能有效避免該第一及第二電子元件因應力集中而發生破裂之問題。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧轉接側
10b‧‧‧置晶側
100‧‧‧導電矽穿孔
101‧‧‧線路結構
11‧‧‧半導體元件
12‧‧‧銲錫凸塊
13,23‧‧‧填充材
14,24‧‧‧封裝層
15‧‧‧導電元件
16‧‧‧封裝基板
160‧‧‧銲球
17‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧電路板
2‧‧‧電子封裝件
20‧‧‧承載結構
21,31‧‧‧第一電子元件
21a,22a‧‧‧作用面
21b,22b‧‧‧非作用面
21c,22c‧‧‧側面
210,220‧‧‧電極墊
211,221‧‧‧導電凸塊
22‧‧‧第二電子元件
23a‧‧‧間隔部
230‧‧‧凹槽
231‧‧‧第一區塊
232‧‧‧第二區塊
233‧‧‧底部
310‧‧‧封裝材
311‧‧‧控制晶片
312‧‧‧高頻寬記憶體型晶片
9‧‧‧刀具
A‧‧‧水平方向
B‧‧‧應力緩衝區
L,r‧‧‧寬度
S‧‧‧間隙
t1,t2‧‧‧厚度
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2D圖係為本發明之電子封裝件之製法的剖視示意圖；第2C-1圖係為第2C圖的局部放大示意圖；以及第3圖係為第2A圖之另一實施例的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2D圖，係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，於一承載結構20上沿水平方向A上間隔設置至少一第一電子元件21與至少一第二電子元件22，其中，該第一電子元件21與該第二電子元件22之間形成一空間(間隙)S。
於本實施例中，該承載結構20係為半導體基板，其具有複數導電矽穿孔(Through-silicon via，簡稱TSV)，以作為矽中介板(Through Silicon interposer，簡稱TSI)。然而，於其它實施例中，該承載結構20亦可為具有核心層 與線路結構之封裝基板(substrate)或無核心層(coreless)之線路構造，如線路重佈層(redistribution layer，簡稱RDL)。應可理解地，該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(leadframe)，並不限於上述。
再者，該第一電子元件21係為主動元件、被動元件、封裝結構或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係為半導體晶片，係具有相對之作用面21a與非作用面21b，該作用面21a上具有複數電極墊210，並於該些電極墊210上形成導電凸塊211，以令該第一電子元件21以覆晶方式藉由該些導電凸塊211結合及電性連接於該承載結構20上。
又，該第二電子元件22係為主動元件、被動元件、封裝結構或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係為半導體晶片，係具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，並於該些電極墊220上形成導電凸塊221，以令該第二電子元件22以覆晶方式藉由該些導電凸塊221結合及電性連接於該承載結構20上。
於本實施例中，該第一電子元件21與該第二電子元件22係為相同類型的電子元件(即主動元件)，且兩者之內部構造可相同或不相同。
應可理解地，該第一電子元件21與該第二電子元件22亦可為不相同類型的電子元件。如第3圖所示，該第一電子元件31係為封裝結構，且該第二電子元件22係為主動元件。具體地，該第一電子元件31係為包含有封裝材310、控制晶片311及至少一高頻寬記憶體(High Bandwidth Memory，簡稱HBM)型晶片312之封裝模組，且該第二電子元件22係為特殊應用積體電路(Application-specific integrated circuit，簡稱ASIC)型半導體晶片。
如第2B圖所示，形成填充材23於該承載結構20與該第一電子元件21之間及該承載結構20與該第二電子元件22之間，以令該填充材23包覆該些導電凸塊211,221。
於本實施例中，該填充材23係例如為底膠，其復形成於該第一電子元件21與該第二電子元件22之間的間隙S中。具體地，該填充材23因毛細作用而延伸至該第一電子元件21之側面21c與該第二電子元件22之側面22c上，以在該第一電子元件21與該第二電子元件22之間形成一由該填充材23所構成之間隔部23a，且該間隔部23a係於該間隙S中呈塊體，其中，該間隙S之寬度L(即該第一電子元件21與該第二電子元件22之間的間距)係小於或等於150微米(um)，且該間隙S之寬度L(或該間距)越小，該填充材23於該間隙S中之毛細現象越明顯。
如第2C及2C-1圖所示，形成至少一凹槽230於該間隔部23a中，進而令該間隔部23a包含有一底部233及位於該底部233上且相分離(例如位於該底部233之不同側) 之第一區塊231與第二區塊232，其中，該第一區塊231係結合於該第一電子元件21之側面21c上，而該第二區塊232係結合於該第二電子元件22之側面22c上。
於本實施例中，係以例如切割、雷射或蝕刻等方式移除部分填充材23以形成該凹槽230，其中，該切割用之刀具9之切割寬度約為110微米(um)，以產生至少110微米之凹槽230之寬度r。
再者，該第一區塊231之厚度t1係不同於(如大於)該第二區塊232之厚度t2，且該第一區塊231之厚度t1係至少30微米(um)。具體地，若其中一區塊的厚度t1,t2太小(如30um以下)會造成後續製程之封裝層24收縮拉扯，使該填充材23與該電子元件脫離。因此，該第一區塊231之厚度t1與該第二區塊232之厚度t2之至少一者係大於或等於30微米(um)。
如第2D圖所示，形成一封裝層24於該承載結構20上，以包覆該填充材23、該第一電子元件21與該第二電子元件22，且令該第一電子元件21之非作用面21b與該第二電子元件22之非作用面22b外露出該封裝層24。
於本實施例中，該封裝層24係採用壓合(lamination)或模壓(molding)之方式形成於該承載結構20上，且該封裝層24係填滿該間隙S與該凹槽230。
再者，藉由整平製程或薄化製程，使該第一電子元件21之非作用面21b與該第二電子元件22之非作用面22b與該封裝層24之上表面共平面。例如，當形成該封裝層 24於該承載結構20上時，先將該封裝層24覆蓋該第一電子元件21之非作用面21b與該第二電子元件22之非作用面22b，再以研磨或切割方式移除該封裝層24之部分材質(可依需求移除該第一電子元件21之非作用面21b之部分材質與該第二電子元件22之非作用面22b之部分材質)，使該第一電子元件21之非作用面21b與該第二電子元件22之非作用面22b齊平該封裝層24之表面。
又，該封裝層24係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)、模封化合物(molding compound)、光阻材(photoresist)或防銲材(solder mask)。
另外，如第3圖所示，該第一電子元件31之封裝材310係例如為聚醯亞胺(PI)、乾膜、環氧樹脂、模封化合物、光阻材或防銲材，且該封裝材310與封裝層24之材質可相同或不相同。
因此，本發明之製法係藉由該填充材23於該間隙S中延伸出相分離的第一區塊231與第二區塊232(或該間隔部23a形成有該凹槽230)之設計，以令該第一區塊231與第二區塊232之間的區域(或該凹槽230)可作為應力緩衝區B，使該填充材23產生於該第一及第二電子元件21,22的內部之應力得以減少，故相較於習知技術，本發明之製法於移除該封裝層24之部分材質時，即使外部的作用力(研磨或切割所產生之外力)傳遞至該第一電子元件21及第二電子元件22中，仍可分散該第一電子元件21及 第二電子元件22所受之應力，以避免該第一電子元件21及第二電子元件22因應力集中而發生破裂之問題。
另一方面，如第3圖所示，當該封裝材310與該封裝層24之材質不相同時，在製程中因收縮產生應力，使該第一電子元件21與該填充材23易發生剝離之風險，故本發明之製法藉由控制該第一區塊231之厚度t1(如大於或等於30um)，使該第一區塊231能承受應力，以避免該第一電子元件21與該第一區塊231發生剝離。
本發明復提供一種電子封裝件2，係包括：一承載結構20、第一電子元件21,31與第二電子元件22、填充材23、一間隔部23a以及一封裝層24。
該第一電子元件21,31及第二電子元件22係藉由複數導電凸塊211,221電性連接承載結構20。
所述之第一電子元件21,31與第二電子元件22係間隔設置於該承載結構20上，使該第一電子元件21,31與該第二電子元件22之間形成有一間隙S。
所述之填充材23係形成於該承載結構20與該第一電子元件21,31之間及該承載結構20與該第二電子元件22之間。
所述之間隔部23a係自該填充材23一體延伸至該間隙S中，且具有相分離的第一區塊231與第二區塊232，其中，該第一區塊231係對應鄰近該第一電子元件21,31，而該第二區塊232係對應鄰近該第二電子元件22。
所述之封裝層24係形成於該承載結構20上，以包覆 該第一電子元件21,31與第二電子元件22，且令該第一電子元件21,31與第二電子元件22之上表面外露出該封裝層24。
於一實施例中，該第一電子元件21與該第二電子元件22係為相同類型。
於一實施例中，該第一電子元件21與該第二電子元件22係為不同類型，例如該第一電子元件31係包含有封裝材310、結合該封裝材310之控制晶片311及高頻寬記憶體型晶片312，該第二電子元件22係為特殊應用積體電路型半導體晶片。另該封裝材310與封裝層24之材質係相同或不同。
於一實施例中，該第一區塊231之厚度(寬度)t1係不同於該第二區塊232之厚度(寬度)t2。
於一實施例中，該第一區塊231與該第二區塊232之至少一者之厚度t1,t2係大於或等於30微米。
於一實施例中，該第一電子元件21,31與該第二電子元件22之上表面係齊平該封裝層24之上表面。
於一實施例中，該封裝層24復形成於該間隙S中及該第一區塊231與該第二區塊232之間。
綜上所述，本發明之電子封裝件及其製法，係藉由該填充材於該第一電子元件與第二電子元件之間的間隙中形成有相分離的第一區塊與第二區塊，使該填充材產生於該第一電子元件及第二電子元件的內部之應力得以減少，故本發明於移除包覆該第一電子元件及第二電子元件之封裝 層之部分材質時，能避免該第一電子元件及第二電子元件發生破裂，因而能提升該電子封裝件之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (20)

  1. 一種電子封裝件，係包括：承載結構；第一電子元件與第二電子元件，係間隔設置於該承載結構上，以令該第一電子元件與該第二電子元件之間形成有一間隙；填充材，係形成於該承載結構與該第一電子元件之間及該承載結構與該第二電子元件之間，且令該填充材於該間隙中形成有間隔部，其中，該間隔部包含有相分離的第一區塊與第二區塊，且該第一區塊係對應鄰近該第一電子元件，而該第二區塊係對應鄰近該第二電子元件；以及封裝層，係形成於該承載結構上，以包覆該第一電子元件與第二電子元件，且令該第一電子元件與第二電子元件之上表面外露出該封裝層。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該承載結構電性連接該第一電子元件及第二電子元件。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件與該第二電子元件係為相同或不同類型。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件係包含有封裝材、結合該封裝材之控制晶片及高頻寬記憶體型晶片。
  5. 如申請專利範圍第4項所述之電子封裝件，其中，該封裝材與封裝層之材質係不相同。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該第二電子元件係為特殊應用積體電路型半導體晶片。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該第一區塊之厚度係不同於該第二區塊之厚度。
  8. 如申請專利範圍第1項所述之電子封裝件，其中，該第一區塊與該第二區塊之至少一者之厚度係大於或等於30微米。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件與該第二電子元件之上表面係齊平該封裝層之上表面。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層復形成於該間隙中及該第一區塊與該第二區塊之間。
  11. 一種電子封裝件之製法，係包括：將第一電子元件與第二電子元件間隔設置於承載結構上，使該第一電子元件與該第二電子元件之間形成有一間隙；形成填充材於該承載結構與該第一電子元件之間及該承載結構與該第二電子元件之間，且令該填充材於該間隙中形成有間隔部，其中，該間隔部包含有相分離的第一區塊與第二區塊，且該第一區塊係對應鄰近該第一電子元件，而該第二區塊係對應鄰近該第二電子元件；以及形成封裝層於該承載結構上，以包覆該第一電子 元件與第二電子元件，且令該第一電子元件與第二電子元件之上表面外露出該封裝層。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該承載結構電性連接該第一電子元件及第二電子元件。
  13. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第一電子元件與該第二電子元件係為相同或不同類型。
  14. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第一電子元件係包含有封裝材、結合該封裝材之控制晶片及高頻寬記憶體型晶片。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該封裝材與封裝層之材質係不相同。
  16. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第二電子元件係為特殊應用積體電路型半導體晶片。
  17. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第一區塊之厚度係不同於該第二區塊之厚度。
  18. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第一區塊與該第二區塊之至少一者之厚度係大於或等於30微米。
  19. 如申請專利範圍第11項所述之電子封裝件之製法，其中，藉由移除該封裝層之部分材質，使該第一電子元件與該第二電子元件之上表面齊平該封裝層之上表面表 面。
  20. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該封裝層復形成於該間隙中及該第一區塊與該第二區塊之間。
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