TWI529906B - 半導體封裝件之製法 - Google Patents

半導體封裝件之製法 Download PDF

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Publication number
TWI529906B
TWI529906B TW102145088A TW102145088A TWI529906B TW I529906 B TWI529906 B TW I529906B TW 102145088 A TW102145088 A TW 102145088A TW 102145088 A TW102145088 A TW 102145088A TW I529906 B TWI529906 B TW I529906B
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Taiwan
Prior art keywords
interposer
semiconductor package
encapsulation layer
fabricating
conductive
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TW102145088A
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English (en)
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TW201523832A (zh
Inventor
黃惠暖
詹慕萱
林畯棠
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102145088A priority Critical patent/TWI529906B/zh
Priority to CN201310693017.5A priority patent/CN104701196A/zh
Priority to US14/276,320 priority patent/US20150162301A1/en
Publication of TW201523832A publication Critical patent/TW201523832A/zh
Application granted granted Critical
Publication of TWI529906B publication Critical patent/TWI529906B/zh

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    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝件之製法
本發明係有關於一種半導體封裝件之製法，尤指一種具中介板之半導體封裝件之製法。
現行之覆晶技術因具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如：晶片尺寸構裝(Chip Scale Package，CSP)、晶片直接貼附封裝(Direct Chip Attached，DCA)以及多晶片模組封裝(Multi-Chip Module，MCM)等型態的封裝模組，其均可利用覆晶技術而達到封裝的目的。
於覆晶封裝製程中，因晶片與封裝基板之熱膨脹係數的差異甚大，故晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合，使得凸塊容易自封裝基板上剝離。另一方面，隨著積體電路之積集度的增加，因晶片與封裝基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的電性連接之可靠度(reliability)下降，並造成信賴性測試的失敗。
為了解決上述問題，遂發展出以半導體基材作為中介結構的製程，其係於一封裝基板與一半導體晶片之間增設一矽中介板 (silicon interposer)，因為該矽中介板與該半導體晶片的材質接近，故可有效避免熱膨脹係數不匹配所產生的問題。
請參閱第1圖，係習知具矽中介板之堆疊封裝結構之剖視圖。如圖所示，習知之封裝結構除了能避免前述問題外，相較於直接將半導體晶片接置於封裝基板之情況，習知之封裝結構亦可使封裝結構的版面面積更加縮小。
舉例來說，一般封裝基板最小之線寬/線距只可做到12/12微米，而當半導體晶片的輸入輸出(I/O)數增加時，由於線寬/線距已無法再縮小，故須加大封裝基板的面積以提高佈線數量，以便於接置高輸入輸出(I/O)數之半導體晶片；相對地，由於第1圖之封裝結構係將半導體晶片11接置於一具有矽貫孔(through silicon via，TSV)的矽中介板12上，以該矽中介板12做為一轉接板，進而將半導體晶片11電性連接至封裝基板13上，而矽中介板12可利用半導體製程做出3/3微米或以下之線寬/線距，故當半導體晶片11的輸入輸出(I/O)數增加時，該矽中介板12的面積已足夠連接高輸入輸出(I/O)數之半導體晶片11。此外，因為該矽中介板12具有細線寬/線距之特性，其電性傳輸距離較短，所以連接於該矽中介板12之半導體晶片11的電性傳輸速度(效率)亦較將半導體晶片直接接置封裝基板之速度(效率)來得快。
惟，習知之封裝結構容易因矽中介板翹曲而造成銲料橋接(solder bridge)(如第1圖所示)或不沾銲料(non-wetting)(未圖示)之現象發生，銲料橋接之現象會造成產品短路，不沾銲料之現象會造成產品斷路或是電性品質不佳的問題，進而造成產品可靠度不佳。
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：提供一承載件，其上設置有至少一具有相對之第一表面與第二表面的半導體晶片，且該半導體晶片係以其第一表面接置於該承載件上，且該第二表面上接置有複數第一導電元件；將一具有相對之第三表面與第四表面的中介板以其第三表面接置於該等第一導電元件上，該中介板具有複數嵌埋其中且電性連接該第三表面的導電柱；於該承載件上形成包覆該半導體晶片與中介板的封裝層，令該封裝層具有面向該承載件之底面與其相對之頂面；從該中介板的第四表面移除部分厚度的該中介板與封裝層，以外露該導電柱之一端於該第四表面；以及移除該承載件。
於前述之製法中，於移除部分厚度的該中介板與封裝層之後，復包括於該中介板的第四表面與該封裝層的頂面上形成電性連接該導電柱的線路重佈層，並復包括於該線路重佈層上形成複數第二導電元件。
依上所述之半導體封裝件之製法，於移除部分厚度的該中介板與封裝層之後，復包括進行切單步驟，又該封裝層係為封裝膠體或乾膜，且移除部分厚度的該中介板與封裝層之方式係以研磨為之。
於本發明之製法中，該第一導電元件與第二導電元件係為銲球，且該承載件係為膠帶。
所述之製法中，該第三表面復包括連接該導電柱的線路層， 且該半導體晶片係為已知良品晶粒。
由上可知，本發明之半導體封裝件之製法係以封裝層包覆中介板與第一導電元件，因此能有效避免中介板翹曲，並能增進中介板與半導體晶片間的接合品質；此外，本發明之製法能在中介板的範圍外進行扇出之線路重佈，所以能有效縮減中介板的尺寸，並增加輸入輸出數，進而降低整體成本；再者，本發明能重新配置半導體封裝件中的複數半導體晶片，故能提升整體產出。
11、21‧‧‧半導體晶片
12‧‧‧矽中介板
13、30‧‧‧封裝基板
20‧‧‧承載件
21a‧‧‧第一表面
21b‧‧‧第二表面
22‧‧‧第一導電元件
23‧‧‧中介板
23a‧‧‧第三表面
23b‧‧‧第四表面
231‧‧‧導電柱
232‧‧‧線路層
24‧‧‧封裝層
24a‧‧‧底面
24b‧‧‧頂面
25‧‧‧線路重佈層
26‧‧‧第二導電元件
2‧‧‧半導體封裝件
31‧‧‧底膠
第1圖係習知具矽中介板之堆疊封裝結構之剖視圖；以及第2A至2I圖係本發明之半導體封裝件之製法及該半導體封裝件之應用例之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「頂」、「底」、「一」、「上」、「面向」及「端」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦 視為本發明可實施之範疇。
請參閱第2A至2I圖，係本發明之半導體封裝件之製法及該半導體封裝件之應用例之剖視圖。
首先，如第2A圖所示，提供一承載件20，其上設置有至少一具有相對之第一表面21a與第二表面21b的半導體晶片21，且該半導體晶片21係以其第一表面21a接置於該承載件20上，且該第二表面21b上接置有複數第一導電元件22，該承載件20可為膠帶(tape)，該第一導電元件22可為銲球，該半導體晶片21可為已知良品晶粒(known good die)。
如第2B圖所示，將一具有相對之第三表面23a與第四表面23b的中介板23以其第三表面23a接置於該等第一導電元件22上，該中介板23具有複數嵌埋其中且電性連接該第三表面23a的導電柱231，該第三表面23a復包括連接該導電柱231的線路層232。
如第2C圖所示，於該承載件20上形成包覆該半導體晶片21與中介板23的封裝層24，令該封裝層24具有面向該承載件20之底面24a與其相對之頂面24b，該封裝層24係為封裝膠體或乾膜。
如第2D圖所示，以研磨方式從該中介板23的第四表面23b移除部分厚度的該中介板23與封裝層24，以外露該導電柱231之一端於該第四表面23b。
如第2E圖所示，於該中介板23的第四表面23b與該封裝層24的頂面24b上形成電性連接該導電柱231的線路重佈層25，並於該線路重佈層25上形成複數第二導電元件26，該第二導電元 件26可為銲球。
如第2F圖所示，進行切單步驟。
如第2G圖所示，移除該承載件20，至此即完成本發明之半導體封裝件2。
如第2H至2I圖所示，將該半導體封裝件2以其第二導電元件26接置於一封裝基板30上，並於該半導體封裝件2與封裝基板30之間形成包覆該第二導電元件26的底膠31。
綜上所述，本發明之半導體封裝件之製法係以封裝層包覆中介板與第一導電元件，因此能有效避免中介板翹曲，並能增進中介板與半導體晶片間的接合品質；此外，本發明之製法能在中介板的範圍外進行扇出(fan out)之線路重佈，所以能有效縮減中介板的尺寸，並增加輸入輸出(I/O)數，進而降低整體成本；再者，本發明能重新配置(reconfigure)半導體封裝件中的複數半導體晶片，故能提升整體產出。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
21‧‧‧半導體晶片
22‧‧‧第一導電元件
23‧‧‧中介板
231‧‧‧導電柱
232‧‧‧線路層
24‧‧‧封裝層
25‧‧‧線路重佈層
26‧‧‧第二導電元件
2‧‧‧半導體封裝件

Claims (10)

  1. 一種半導體封裝件之製法，係包括：提供一承載件，其上設置有至少一具有相對之第一表面與第二表面的半導體晶片，且該半導體晶片係以其第一表面接置於該承載件上，且該第二表面上接置有複數第一導電元件；將一具有相對之第三表面與第四表面的中介板以其第三表面接置於該等第一導電元件上，該中介板具有複數嵌埋其中且電性連接該第三表面的導電柱；於該承載件上形成包覆該半導體晶片與中介板的封裝層，令該封裝層具有面向該承載件之底面與其相對之頂面；從該中介板的第四表面移除部分厚度的該中介板與封裝層，以外露該導電柱之一端於該第四表面；以及移除該承載件。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除部分厚度的該中介板與封裝層之後，復包括於該中介板的第四表面與該封裝層的頂面上形成電性連接該導電柱的線路重佈層。
  3. 如申請專利範圍第2項所述之半導體封裝件之製法，復包括於該線路重佈層上形成複數第二導電元件。
  4. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除部分厚度的該中介板與封裝層之後，復包括進行切單步驟。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該封裝層係為封裝膠體或乾膜。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，移除部分厚度的該中介板與封裝層之方式係以研磨為之。
  7. 如申請專利範圍第3項所述之半導體封裝件之製法，其中，該第一導電元件與第二導電元件係為銲球。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該承載件係為膠帶。
  9. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第三表面復包括連接該導電柱的線路層。
  10. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該半導體晶片係為已知良品晶粒。
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