TWI611577B - 電子封裝件及半導體基板 - Google Patents

電子封裝件及半導體基板 Download PDF

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Publication number
TWI611577B
TWI611577B TW105106680A TW105106680A TWI611577B TW I611577 B TWI611577 B TW I611577B TW 105106680 A TW105106680 A TW 105106680A TW 105106680 A TW105106680 A TW 105106680A TW I611577 B TWI611577 B TW I611577B
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semiconductor substrate
substrate
protruding structure
substrate body
electronic package
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TW105106680A
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English (en)
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TW201733109A (zh
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陳仕卿
彭仕良
賴杰隆
潘嘉偉
呂長倫
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矽品精密工業股份有限公司
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Priority to TW105106680A priority Critical patent/TWI611577B/zh
Priority to CN201610152388.6A priority patent/CN107154386B/zh
Priority to US15/084,762 priority patent/US9899309B2/en
Publication of TW201733109A publication Critical patent/TW201733109A/zh
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Publication of TWI611577B publication Critical patent/TWI611577B/zh

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Abstract

一種半導體基板，係包括：一具有側面之基板本體、以及自該側面向外延伸之突出結構，使該半導體基板藉由該突出結構分散於製程中所產生的應力，以避免該半導體基板發生破裂或脫層之問題。本發明復提供應用該半導體基板之電子封裝件。

Description

電子封裝件及半導體基板
本發明係有關一種半導體封裝件，尤指一種能提高產品良率之電子封裝件及所應用之半導體基板。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術繁多，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊模組。
第1圖係為習知3D IC式半導體封裝件1之剖面示意圖。如第1圖所示，係將複數半導體晶片11藉由複數銲錫凸塊110設於一矽中介板(Through Silicon interposer，簡稱TSI)10上，且形成一封裝層12於該矽中介板10上，以包覆該半導體晶片11，其中該矽中介板10具有複數導電矽穿孔(Through-silicon via，簡稱TSV)100及形成於該導電矽穿孔100上並電性連接該些銲錫凸塊110之線路 重佈層(Redistribution layer，簡稱RDL)101，以令該矽中介板10藉由該些導電矽穿孔100與複數導電元件130結合至一封裝基板13上，並以底膠14包覆該些導電元件130。
惟，習知半導體封裝件1中，該矽中介板10之四個角落皆為直角，如第1’圖所示，故該矽中介板10於封裝後，會因應力集中而在各角落形成較大的晶片角落應力(Die Corner Stress)，使其與該封裝層12之間會產生強大的應力，如第1’圖所示之虛線圓圈處S，導致該矽中介板10會沿四個角落處發生破裂(Crack)、或因熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)而與該封裝層12分離，即產生脫層(delaminating)問題，造成該矽中介板10無法有效電性連接該半導體晶片11或無法通過可靠度測試，致使產品之良率不佳。
再者，於封裝後，該矽中介板10之四個角落與該底膠14之間亦會產生強大應力，如第1圖所示之虛線圓圈處K，導致該矽中介板10會沿四個角落處發生破裂或與該底膠14發生分離，致使產品之良率不佳。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體基板，係包括：一基板本體，係具有至少一側面；以及至少一突出結構，係自該基板本體之側面向外延伸。
本發明復提供一種電子封裝件，係包括：半導體基 板，係包含有一基板本體及自該基板本體之側面向外延伸的至少一突出結構；電子元件，係設於該半導體基板上；以及封裝層，係形成於該半導體基板上以包覆該電子元件。
前述之電子封裝件中，該半導體基板具有複數線路，以令該電子元件電性連接該線路。
前述之電子封裝件中，復包括封裝基板，係接置於該半導體基板用於設有該電子元件之另一側上。又包括形成於該封裝基板與該半導體基板間的底膠。
前述之電子封裝件及半導體基板中，該基板本體具有複數該側面，其交會形成有角落，以令該突出結構形成於該角落上。
前述之電子封裝件及半導體基板中，該突出結構係與該基板本體一體成形。
前述之電子封裝件及半導體基板中，該突出結構之輪廓係由直線、曲線或其二者之組合所構成。
前述之電子封裝件及半導體基板中，該突出結構係包含有一連接該基板本體側面之頸部與一連接該頸部之頭部。
由上可知，本發明之電子封裝件及半導體基板中，主要藉由該突出結構之設計，以分散該半導體基板與該封裝層(或底膠)之間的應力，使該半導體基板消除應力集中於角落之問題，故能避免該半導體基板於封裝後發生破裂或脫層等問題，因而能提高產品良率。
再者，該突出結構係自該基板本體之側面向外延伸， 故該突出結構不會佔用該基板本體之原本預定區域(如佈設線路或設置電極墊的區域)，使該半導體基板之原本預定可用區域與性能均不受影響。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
100‧‧‧導電矽穿孔
101‧‧‧線路重佈層
11‧‧‧半導體晶片
110‧‧‧銲錫凸塊
12,42‧‧‧封裝層
13,43‧‧‧封裝基板
130,402,430‧‧‧導電元件
14,44‧‧‧底膠
2,2’,40‧‧‧半導體基板
20,20’,40’‧‧‧基板本體
20a,20a’,40c‧‧‧側面
20b‧‧‧角落
21‧‧‧突出結構
21a‧‧‧頸部
21b‧‧‧頭部
210,210’‧‧‧直線
211‧‧‧曲線
3,5‧‧‧整版面板塊
30,50‧‧‧預切割道
30’,50’‧‧‧切割道
30”,50”‧‧‧預切割道材質
4‧‧‧電子封裝件
40a‧‧‧第一表面
40b‧‧‧第二表面
400‧‧‧導電穿孔
401‧‧‧線路重佈結構
41‧‧‧電子元件
41a‧‧‧作用面
41b‧‧‧非作用面
410‧‧‧電極墊
W‧‧‧寬度
S,K‧‧‧虛線圓圈處
第1圖係為習知半導體封裝件之剖面示意圖；第1’圖係為第1圖之半導體封裝件省略底膠之上視示意圖；第2圖係為本發明之半導體基板之上視示意圖；第2’圖係為第2圖之另一實施例；第2A至2D圖係為第2圖之不同實施例的局部放大圖；第3圖係為本發明之半導體基板之製法的上視示意圖；第4圖係為本發明之電子封裝件之剖面示意圖；以及第5圖係為本發明之電子封裝件之製法的上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明之半導體基板2之上視示意圖。如第2圖所示，所述之半導體基板2係包括有一基板本體20以及複數突出結構21。
所述之基板本體20係為含矽之板體，例如，矽中介板(Through Silicon Interposer，簡稱TSI)、主動晶片、被動晶片或玻璃基板。
於本實施例中，該基板本體20係具有四個側面20a，如第2圖所示之矩形輪廓。
所述之突出結構21係自該基板本體20之側面20a向外延伸。
於本實施例中，該基板本體20之四個側面20a於其交會處係形成有四個角落20b，以令各該突出結構21對應形成於各該角落20b上。
再者，該突出結構21係包含有一連接該基板本體20之頸部21a與一連接該頸部21a之頭部21b，且該突出結構21之輪廓係由直線210,210’、曲線211或其二者之組合所構成，如第2A至2D圖所示。具體地，如第2A及2D圖所示，該頸部21a呈鈍角多邊形；如第2B及2C圖所示，該 頸部21a呈圓弧形。因此，本實施例之突出結構21係由圓弧及/或多邊形所構成。需注意，如第2A及2D圖所示，該頸部21a之單一側至多十條直線210，以避免變成弧狀。
又，於其它實施例中，如第2’圖所示之半導體基板2’，該基板本體20’僅具有一側面20a’，如圓形輪廓，且該突出結構21之位置可依需求形成於該側面20a’之任一處上。
另外，該半導體基板2之製法係如第3圖所示，先提供一整版面板塊3，且該整版面板塊3包含複數基板本體20及複數預切割道30，且該預切割道30之寬度W約為80至120微米(μm)，再於該些預切割道30上形成光阻層後，以乾式蝕刻方式，如反應性離子蝕刻(Reactive Ion Etching，簡稱RIE)或電漿(Plasma)方式，形成複數突出結構21及切割道30’，之後移除該光阻層，再沿該些切割道30’進行切單製程以分離各該半導體基板2，最後移除該半導體基板2周圍的預切割道材質30”。因此，該突出結構21係與該基板本體20一體成形。
本發明之半導體基板2,2’係藉由該突出結構21之設計，以分散該半導體基板2,2’於後續封裝製程中所產生的應力，使該半導體基板2,2’消除應力集中於角落之問題，故能避免該半導體基板2,2’於封裝後發生破裂或脫層之問題，因而能提高產品良率。
再者，該突出結構21係凸出於該基板本體20,20’之側面20a,20a’外，亦即該突出結構21只佔用預切割道30之區域，故該突出結構21不會佔用該基板本體20,20’之原本 預定區域(如佈設線路或設置電極墊的區域)，使該基板本體20,20’之原本預定可用面積與性能皆完全不受影響。
第4圖係為本發明之電子封裝件4之剖面示意圖。如第4圖所示，所述之電子封裝件4係包括有一半導體基板40、至少一電子元件41以及一封裝層42。
所述之半導體基板40係如第2圖所述之結構，其基板本體40’係定義有相對之第一表面40a與第二表面40b，且該半導體基板40之側面40c係鄰接該第一表面40a與第二表面40b，使該突出結構21自該側面40c向外延伸。
於本實施例中，該半導體基板40具有複數線路。例如，該基板本體40’中具有複數貫穿該第一與第二表面40a,40b(即連通該第一與第二表面40a,40b)之導電穿孔400。具體地，該導電穿孔400係為導電矽穿孔(Through-silicon via，簡稱TSV)，且該導電穿孔400之兩端面係分別齊平該基板本體40’之第一表面40a與第二表面40b。
再者，該半導體基板40之線路亦可形成於該基板本體40’之第一表面40a上。例如，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一線路重佈結構401，且該線路重佈結構401電性連接各該導電穿孔400。
所述之電子元件41係設於該半導體基板40上，且該電子元件41係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如 電阻、電容及電感。
於本實施例中，該電子元件41係為半導體晶片，其具有相對之作用面41a與非作用面41b，該作用面41a具有複數電極墊410，使該電子元件41以其電極墊410藉由含銲錫材料之導電元件402結合於該線路重佈結構401上。
所述之封裝層42係形成於該半導體基板40上以包覆該些電子元件41與該些導電元件402。
於本實施例中，形成該封裝層42之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
於另一實施例中，該電子封裝件4亦可包括一封裝基板43，其設於該半導體基板40用於設有該電子元件41之另一側上(即該基板本體40’之第二表面40b上)。具體地，該封裝基板43藉由複數導電元件430結合並電性連接該半導體基板40之導電穿孔400，再形成底膠44於該封裝基板43與該半導體基板40之間以包覆該些導電元件430，並於後續製程中，形成複數銲球(圖略)於該封裝基板43下側，以供該電子封裝件4結合至一電路板(圖略)上。
另外，該電子封裝件4之製法係如第5圖所示(圖未示封裝層42)，先提供一整版面板塊5，該整版面板塊5包含複數基板本體40’及複數預切割道50，且該基板本體40’上設有該電子元件41；接著，於該些預切割道50上以蝕刻方式形成複數突出結構21及切割道50’，之後沿該些切割道50’進行切單製程以分離各該半導體基板40，最後移 除該電子封裝件4周圍的預切割道材質50”。亦或，先於該整版面板塊5形成複數突出結構21及切割道50’，再於該基板本體40’上設置電子元件41。
需注意，乾式蝕刻無法蝕刻該封裝層42，故可先形成該些突出結構21及切割道50’，再形成該封裝層42。應可理解地，亦可先形成該封裝層42，再以其它方式形成該些突出結構21及切割道50’。
本發明之電子封裝件4藉由該突出結構21之設計，以消除該半導體基板40的應力集中，故於封裝後，該半導體基板40不會沿角落處發生破裂，且能避免因熱膨脹係數(CTE)不匹配而與該封裝層42(或底膠44)發生分離之問題，因而該半導體基板40得以與該電子元件41及封裝基板43保持正常電性連接，並能通過可靠度測試，致能提高產品良率。
再者，該突出結構21係凸出於該基板本體40’之使用區域外，亦即該突出結構21只佔用該預切割道50之區域，故該突出結構21不會佔用該基板本體40’之原本預定區域(如佈設線路或設置電極墊的區域)，使該半導體基板40之可用面積與性能皆完全不受影響，亦即該基板本體40’之線路佈設空間或設置該電子元件41之區域不受影響。
綜上所述，本發明之電子封裝件及半導體基板中，係藉由該突出結構消除應力集中之問題，以提升產品良率，且該半導體基板之原本可用區域與性能均不受影響。
上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體基板
20‧‧‧基板本體
20a‧‧‧側面
20b‧‧‧角落
21‧‧‧突出結構
21a‧‧‧頸部
21b‧‧‧頭部

Claims (11)

  1. 一種半導體基板，係包括：一基板本體，係具有至少一側面與形成於該基板本體中之複數導電穿孔；以及至少一突出結構，係自該基板本體之側面向外延伸，其中，該突出結構係與該基板本體一體成形。
  2. 如申請專利範圍第1項所述之半導體基板，其中，該基板本體具有複數該側面，其交會形成有角落，以令該突出結構形成於該角落上。
  3. 如申請專利範圍第1項所述之半導體基板，其中，該突出結構之輪廓係由直線、曲線或其二者之組合所構成。
  4. 如申請專利範圍第1項所述之半導體基板，其中，該突出結構係包含有一連接該基板本體側面之頸部與一連接該頸部之頭部。
  5. 一種電子封裝件，係包括：半導體基板，係包含有一基板本體及自該基板本體之側面向外延伸的至少一突出結構，以及形成於該基板本體中之複數導電穿孔，其中，該突出結構係與該基板本體一體成形；電子元件，係設於該半導體基板上；以及封裝層，係形成於該半導體基板上以包覆該電子元件。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該基板本體具有複數該側面，其交會形成有角落，以令該突 出結構形成於該角落上。
  7. 如申請專利範圍第5項所述之電子封裝件，其中，該半導體基板具有複數線路，以令該電子元件電性連接該線路。
  8. 如申請專利範圍第5項所述之電子封裝件，其中，該突出結構之輪廓係由直線、曲線或其二者之組合所構成。
  9. 如申請專利範圍第5項所述之電子封裝件，其中，該突出結構係包含有一連接該側面之頸部與一連接該頸部之頭部。
  10. 如申請專利範圍第5項所述之電子封裝件，復包括封裝基板，係接置於該半導體基板相對設有該電子元件之另一側上。
  11. 如申請專利範圍第10項所述之電子封裝件，復包括形成於該封裝基板與該半導體基板間的底膠。
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