TWI669789B - 電子封裝件 - Google Patents

電子封裝件 Download PDF

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TWI669789B
TWI669789B TW105112802A TW105112802A TWI669789B TW I669789 B TWI669789 B TW I669789B TW 105112802 A TW105112802 A TW 105112802A TW 105112802 A TW105112802 A TW 105112802A TW I669789 B TWI669789 B TW I669789B
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Taiwan
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substrate
chamfer
electronic package
item
patent application
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TW105112802A
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TW201739010A (zh
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梁芳瑜
張宏憲
林長甫
林畯棠
張博豪
王伯豪
曾文聰
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矽品精密工業股份有限公司
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Priority to TW105112802A priority Critical patent/TWI669789B/zh
Priority to CN201610313422.3A priority patent/CN107305869B/zh
Priority to US15/494,034 priority patent/US10763223B2/en
Publication of TW201739010A publication Critical patent/TW201739010A/zh
Application granted granted Critical
Publication of TWI669789B publication Critical patent/TWI669789B/zh
Priority to US16/875,240 priority patent/US11227842B2/en

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Abstract

一種基板結構，係包括：一表面形成有至少一倒角之基板、以及結合至該基板之複數導電體，以供該基板結構藉由該倒角分散於封裝製程中所產生的應力，避免該基板結構發生破裂問題。本發明復提供應用該基板結構之電子封裝件。

Description

電子封裝件
本發明係有關一種半導體封裝件，尤指一種能提高產品良率之電子封裝件及其基板結構。
目前應用於晶片封裝領域之技術繁多，例如晶片尺寸封裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊模組。
第1圖係為習知3D IC式半導體封裝件1之剖面示意圖。如第1圖所示，係將一半導體晶片13藉由複數銲錫凸塊130設於一矽中介板(Through Silicon interposer，簡稱TSI)12上，其中，該矽中介板12具有複數導電矽穿孔(Through-silicon via，簡稱TSV)120及電性連接該些導電矽穿孔120與該些銲錫凸塊130之線路重佈層(Redistribution layer，簡稱RDL)121，且該矽中介板12藉由該些導電矽穿孔120與複數導電元件110結合至一封裝基板11上，再以底膠10’包覆該些導電元件110與該些銲錫凸塊130，並 以封裝膠體10包覆該半導體晶片13與該矽中介板12。
惟，習知半導體封裝件1之封裝製程中，於遭遇溫度循環(temperature cycle)或應力變化時，如搬運、通過回銲爐、或經歷落摔等製程或測試時，該半導體晶片13及該矽中介板12會在各角落形成較大的角落應力(Corner Stress)，導致該半導體晶片13及該矽中介板12會沿角落處發生破裂(Crack)(如圖所示之破裂處K)；亦或由於該半導體晶片13、矽中介板12及封裝基板11間因熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)而與該封裝膠體10或底膠10’分離，即產生脫層(delaminating)問題，造成該矽中介板12無法有效電性連接該半導體晶片13或無法通過可靠度測試，致使產品之良率不佳。前述問題對於現今電子產品要求輕薄短小及晶片薄化趨勢下更顯嚴重。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種基板結構，係包括：一基板，於其表面形成有至少一第一倒角；以及複數導電體，係結合至該基板。
本發明復提供一種電子封裝件，係包括：一承載件；至少一基板，係接置於該承載件上，且於該基板之表面形成有至少一第一倒角；複數導電體，係供電性連接該基板與該承載件；以及封裝體，係形成於該基板與該承載件之 間。
前述之電子封裝件中，該封裝體係覆蓋該基板。
前述之電子封裝件及其基板結構中，該第一倒角設於該基板之角落位置。
前述之電子封裝件及其基板結構中，該基板之表面上復具有未貫穿該基板之凹部。例如，該第一倒角與凹部係相隔一距離，且該凹部設於該基板之角落位置，又該凹部之形式係為開口寬度大而內部空間寬度小、或該凹部之形式係為開口寬度小而內部空間寬度大。
前述之電子封裝件及其基板結構中，該基板復形成有從該第一倒角延伸出之第二倒角。
前述之電子封裝件及其基板結構中，該導電體係為線路層、導電柱或導電凸塊所組群組之其中一者。
由上可知，本發明之電子封裝件及基板結構，主要藉由該第一倒角之設計來分散該基板所受應力，並藉由該凹部之設計來增加該基板與該封裝層之結合力，故能避免該基板於封裝製程中發生破裂或脫層等問題，因而能提高產品良率。
1‧‧‧半導體封裝件
10,601‧‧‧封裝膠體
10’,600‧‧‧底膠
11‧‧‧封裝基板
110‧‧‧導電元件
12‧‧‧矽中介板
120‧‧‧導電矽穿孔
121‧‧‧線路重佈層
13‧‧‧半導體晶片
130‧‧‧銲錫凸塊
2,3‧‧‧基板結構
21‧‧‧基板
21a‧‧‧表面
21c‧‧‧側面
210‧‧‧第一倒角
25‧‧‧導電體
25a‧‧‧金屬柱
25b‧‧‧銲錫材料
31‧‧‧密封環
310‧‧‧第二倒角
34,34’,34”‧‧‧凹部
6‧‧‧電子封裝件
60‧‧‧封裝體
61‧‧‧第一基板
62‧‧‧第二基板
63‧‧‧承載件
A‧‧‧佈線區
K‧‧‧破裂處
L‧‧‧距離
R‧‧‧開口寬度
D‧‧‧深度
第1圖係為習知半導體封裝件之剖面示意圖；第2圖係為本發明之基板結構之剖面示意圖；第3及3’圖係為第2圖之另一實施例之剖面示意圖；第4圖係為本發明之基板結構之凹部之各種形狀的剖面示意圖； 第5A至5F圖係為本發明之基板結構之各種不同實施例之上視示意圖；以及第6圖係為本發明之電子封裝件之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明之基板結構2之剖面示意圖。如第2圖所示，該基板結構2係包括：於其表面形成有至少一第一倒角210之基板21、以及複數結合至該基板21之導電體25。
所述之基板21係為半導體板材，且於其一表面21a之邊緣(如角落處)形成該第一倒角210。然而，該基板21 之板材亦可為陶瓷板材或有機材料，如玻纖樹脂或印刷電路板等，並不限於上述。
於本實施例中，該基板21係為矽晶圓、矽晶片或矽中介板，且該基板21可為條狀(strip form)或已切單體(singulation)，並以梯形刀於該基板21上切割出該第一倒角210。
再者，該基板21可為各式幾何形狀之板體，如矩形、多邊形或圓形等，且可為對稱板體或不對稱板體，故該基板21之外觀形狀之種類繁多，並無特別限制。又，該第一倒角210之表面係為平直斜面(如第6圖所示)、內凹圓弧狀(如第2及3圖所示)、外凸圓弧狀(如第3’圖所示)或其它形狀等。
所述之導電體25係為線路層(圖未示)、導電柱或導電凸塊(如第2圖所示)所組群組之其中一者。
於本實施例中，各該導電體25係包含有一金屬柱25a與一銲錫材料25b。
於另一實施例中，如第3及3’圖所示，該基板結構3復包括一設於該基板21之表面21a上的密封環31，該密封環31環繞該基板21之佈線區A(用以佈設該導電體25之區域)，且該基板21之表面21a上於該密封環31外具有至少一未貫穿該基板21之凹部34，並使該第一倒角210與該凹部34相隔一距離L，亦即該凹部34位於該第一倒角210與該密封環31之間，以避免切割刀具碰觸該導電體25而造成包刀(即金屬材料因受刀具切割而內縮以包覆該 刀具)之問題。
具體地，該凹部34之製作方式繁多，例如，製作該凹部34之方式可為超音波研磨、化學機械研磨(Chemical-Mechanical Polishing，簡稱CMP)、雷射、水刀、等向/非等向性蝕刻、乾/濕蝕刻或上述加工法的搭配組合等。
再者，如第4圖所示，該凹部34,34’,34”之尺寸可依後述第6圖所示之封裝體60之膠材種類而變化，即該凹部34的深寬比可允許膠材之顆粒進出而不會造成膠材流動堵塞。若以目前封裝體60之膠材中所含的填充物(filler)顆粒之最大尺寸為3μm為例，該凹部34,34’,34”之開口寬度R係大於3μm(如10μm)及深度D約為3至6μm，但不此為限。因此，凹部34,34’,34”之開口寬度R需大於該封裝體60之填充物之顆粒尺寸。
又，該凹部34之外觀形狀之種類繁多，如第4圖所示，該凹部34,34’,34”之側面可為具有複數側壁之洞穴狀，且如第5A至5F圖所示，該凹部34之上視形狀可為各式幾何形狀(弧形、多邊形、圓形等)。具體地，如第4圖所示，若該凹部34之形式為開口寬度大而內部空間寬度小時，可增加該封裝體60於該凹部34中之流動性；若該凹部34’之形式為開口寬度小而內部空間寬度大時，可增加封裝體60與該凹部34(即該封裝體60與該基板21)之結合力；應可理解地，該凹部34”之形式可為其開口與其內部空間之寬度一致。
另外，該凹部34之形成位置可依需求設計，例如針對該基板結構3加工時，該基板21容易產生應力集中的區域進行設置，以達到減少基板21破裂(crack)與避免膠層(如後述之底膠600或封裝膠體601)脫層之目的。具體地，如第5A至5E圖所示，若該基板21之表面21a具有角落，於封裝製程中，該基板21會因應力集中而在各角落處形成較大的角落應力(Corner Stress)，使其與該封裝體60之間會產生強大的應力，故該凹部34可設於該角落位置。
於另一實施例中，如第3及3’圖所示，該基板21具有從該第一倒角210延伸出之第二倒角310，其中，該第二倒角310從該第一倒角210延伸的方向可具有多種方向性，該第二倒角310延伸的方向可以相同或不同於該第一倒角210形成於該基板21的方向。具體地，該第二倒角310係沿該基板21之側面21c延伸，且該第二倒角310之表面係為平直斜面、圓弧狀或其它形狀等。應可理解地，可從該第二倒角310繼續延伸出至少一倒角(圖未示)或依序延伸形成複數倒角(圖未示)，且該倒角延伸的方向亦可相同或不同於該第二倒角310從該第一倒角210延伸的方向，例如，第三倒角從該第二倒角310延伸成形，該第四倒角從該第二倒角延伸成形。
本發明之基板結構2,3藉由該第一倒角210之設計，以分散該基板結構2,3於後續封裝製程中所產生的應力，使該基板結構2,3消除應力集中於角落之問題，故能避免該基板結構2,3於封裝後發生破裂或脫層之問題，因而能提高產品良率。
再者，該基板結構3藉由該第二倒角310之設計，以產生更好的消除應力的效果。
第6圖係為本發明之電子封裝件6之剖面示意圖。如第6圖所示，該電子封裝件6係包括：承載件63、接置於該承載件63上之第一基板61與第二基板62、以及一封裝體60。
所述之承載件63係為陶瓷板材或有機板材，以作為封 裝基板，且該第一基板61及第二基板62係為半導體板材，以令該第二基板62作為中介板而接置於該承載件63上，該第一基板61作為電子元件而接置於該第二基板62上。
於本實施例中，該第一基板61(如電子元件)係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。
另外，於一實施態樣中(未圖示)，該第一基板61(如電子元件)可直接接置於該承載件63(如封裝基板)上，而毋需間隔該第二基板62(如矽中介板)。
再者，該第一倒角210係選擇形成於該第一基板61及/或該第二基板62上，且該第一基板61及第二基板62上亦可選擇性地形成如第3及3’圖所示之該密封環31、凹部34及/或第二倒角310。
所述之導電體25係結合於該第一基板61及第二基板62，用以電性連接該第一基板61、第二基板62及承載件63。
所述之封裝體60係形成於該承載件63上以包覆該第一基板61及第二基板62。
於本實施例中，該封裝體60係包含底膠600與封裝膠體601，該底膠600係形成於該第一基板61與第二基板62之間及該第二基板62與承載件63之間，且該封裝膠體601係形成於該承載件63上以包覆該底膠600、第一基板61及第二基板62。
本發明之電子封裝件6藉由該第一倒角210之設計， 以供形成該封裝體60時，能分散該第一基板61與第二基板62所產生的應力，使該第一基板61與第二基板62能消除應力集中於角落之問題，故能避免該第一基板61與第二基板62於封裝製程中發生破裂或脫層之問題，因而能提高產品良率。
綜上所述，本發明之電子封裝件及基板結構，係藉由該倒角之設計消除應力集中之問題，以提升產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (17)

  1. 一種電子封裝件，係包括：一承載件；一基板，係接置於該承載件上，其中，該基板之表面形成有至少一第一倒角及自該第一倒角延伸出之第二倒角；複數導電體，係結合至該基板且電性連接該基板與該承載件；以及封裝體，係形成於該基板與該承載件之間。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一倒角設於該基板之角落位置。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該基板之表面復形成有未貫穿該基板之凹部。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該第一倒角與凹部係相隔一距離。
  5. 如申請專利範圍第3項所述之電子封裝件，其中，該凹部設於該基板之角落位置。
  6. 如申請專利範圍第3項所述之電子封裝件，其中，該凹部之形式係為開口寬度大而內部空間寬度小。
  7. 如申請專利範圍第3項所述之電子封裝件，其中，該凹部之形式係為開口寬度小而內部空間寬度大。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括複數從第二倒角依序延伸成形之倒角。
  9. 如申請專利範圍第1項所述之電子封裝件，復包括第三倒角與第四倒角，其中，該第三倒角從該第二倒角延伸成形，該第四倒角從該第二倒角延伸成形。
  10. 如申請專利範圍第1項所述之電子封裝件，復包括至少一倒角，該倒角從第二倒角延伸，且該倒角延伸的方向不同於該第二倒角從該第一倒角延伸的方向。
  11. 如申請專利範圍第1項所述之電子封裝件，其中，該第二倒角從該第一倒角延伸的方向係不同於該第一倒角形成於該基板的方向。
  12. 一種電子封裝件，係包括：一承載件；一基板，係接置於該承載件上，其中，該基板之表面形成有至少一第一倒角及未貫穿該基板之凹部，且該凹部之形式係為開口寬度大而內部空間寬度小、或者為開口寬度小而內部空間寬度大；複數導電體，係結合至該基板且電性連接該基板與該承載件；以及封裝體，係形成於該基板與該承載件之間。
  13. 如申請專利範圍第12項所述之電子封裝件，其中，該第一倒角與凹部係相隔一距離。
  14. 如申請專利範圍第12項所述之電子封裝件，其中，該凹部設於該基板之角落位置。
  15. 如申請專利範圍第12項所述之電子封裝件，其中，該第一倒角設於該基板之角落位置。
  16. 如申請專利範圍第1或12項所述之電子封裝件，其中，該導電體係為線路層、導電柱或導電凸塊所組群組之其中一者。
  17. 如申請專利範圍第1或12項所述之電子封裝件，其中，該封裝體係覆蓋該基板。
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US15/494,034 US10763223B2 (en) 2016-04-25 2017-04-21 Substrate structure having chamfers
US16/875,240 US11227842B2 (en) 2016-04-25 2020-05-15 Electronic package and substrate structure having chamfers

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