CN107305869B - 电子封装件及基板结构 - Google Patents

电子封装件及基板结构 Download PDF

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CN107305869B
CN107305869B CN201610313422.3A CN201610313422A CN107305869B CN 107305869 B CN107305869 B CN 107305869B CN 201610313422 A CN201610313422 A CN 201610313422A CN 107305869 B CN107305869 B CN 107305869B
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substrate
chamfer
package
recess
electronic package
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CN107305869A (zh
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梁芳瑜
张宏宪
林长甫
林畯棠
张博豪
王伯豪
曾文聪
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及基板结构，包括：一表面形成有至少一倒角的基板、以及结合至该基板的多个导电体，以供该基板结构通过该倒角分散于封装制程中所产生的应力，避免该基板结构发生破裂问题。

Description

电子封装件及基板结构
技术领域
本发明有关一种半导体封装件，尤指一种能提高产品良率的电子封装件及其基板结构。
背景技术
目前应用于芯片封装领域的技术繁多，例如芯片尺寸封装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型封装模组、或将芯片立体堆迭化整合为三维积体电路(3D IC)芯片堆迭模组。
图1为悉知3D IC式半导体封装件1的剖面示意图。如图1所示，将一半导体芯片13通过多个焊锡凸块130设于一硅中介板(Through Silicon interposer，简称TSI)12上，其中，该硅中介板12具有多个导电硅穿孔(Through-silicon via，简称TSV)120及电性连接该些导电硅穿孔120与该些焊锡凸块130的线路重布层(Redistribution layer，简称RDL)121，且该硅中介板12通过该些导电硅穿孔120与多个导电元件110结合至一封装基板11上，再以底胶10’包覆该些导电元件110与该些焊锡凸块130，并以封装胶体10包覆该半导体芯片13与该硅中介板12。
然而，悉知半导体封装件1的封装制程中，于遭遇温度循环(temperature cycle)或应力变化时，如搬运、通过回焊炉、或经历落摔等制程或测试时，该半导体芯片13及该硅中介板12会在各角落形成较大的角落应力(Corner Stress)，导致该半导体芯片13及该硅中介板12会沿角落处发生破裂(Crack)(如图所示的破裂处K)；或由于该半导体芯片13、硅中介板12及封装基板11间因热膨胀系数(Coefficient of thermal expansion，简称CTE)不匹配(mismatch)而与该封装胶体10或底胶10’分离，即产生脱层(delaminating)问题，造成该硅中介板12无法有效电性连接该半导体芯片13或无法通过可靠度测试，致使产品的良率不佳。前述问题对于现今电子产品要求轻薄短小及芯片薄化趋势下更显严重。
因此，如何克服上述悉知技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的种种缺失，本发明提供一种电子封装件及基板结构，避免基板结构发生破裂问题。
本发明的基板结构，包括：一基板，于其表面形成有至少一第一倒角；以及多个导电体，其结合至该基板。
本发明还提供一种电子封装件，包括：一承载件；至少一基板，其接置于该承载件上，且于该基板的表面形成有至少一第一倒角；多个导电体，其供电性连接该基板与该承载件；以及封装体，其形成于该基板与该承载件之间。
前述的电子封装件中，该封装体覆盖该基板。
前述的电子封装件及其基板结构中，该第一倒角设于该基板的角落位置。
前述的电子封装件及其基板结构中，该基板的表面上还具有未贯穿该基板的凹部。例如，该第一倒角与凹部相隔一距离，且该凹部设于该基板的角落位置，又该凹部的形式为开口宽度大而内部空间宽度小、或该凹部的形式为开口宽度小而内部空间宽度大。
前述的电子封装件及其基板结构中，该基板还形成有从该第一倒角延伸出的第二倒角。
前述的电子封装件及其基板结构中，该导电体为线路层、导电柱或导电凸块所组群组的其中一者。
由上可知，本发明的电子封装件及基板结构，主要通过该第一倒角的设计来分散该基板所受应力，并通过该凹部的设计来增加该基板与该封装层的结合力，故能避免该基板于封装制程中发生破裂或脱层等问题，因而能提高产品良率。
附图说明
图1为悉知半导体封装件的剖面示意图；
图2为本发明的基板结构的剖面示意图；
图3及图3′为图2的另一实施例的剖面示意图；
图4为本发明的基板结构的凹部的各种形状的剖面示意图；
图5A至图5F为本发明的基板结构的各种不同实施例的上视示意图；以及
图6为本发明的电子封装件的剖面示意图。
符号说明
1 半导体封装件 10,601 封装胶体
10’,600 底胶 11 封装基板
110 导电元件 12 硅中介板
120 导电硅穿孔 121 线路重布层
13 半导体芯片 130 焊锡凸块
2,3 基板结构 21 基板
21a 表面 21c 侧面
210 第一倒角 25 导电体
25a 金属柱 25b 焊锡材料
31 密封环 310 第二倒角
34,34’,34” 凹部 6 电子封装件
60 封装体 61 第一基板
62 第二基板 63 承载件
A 布线区 K 破裂处
L 距离 R 开口宽度
D 深度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“第三”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明的基板结构2的剖面示意图。如图2所示，该基板结构2包括：于其表面形成有至少一第一倒角210的基板21、以及多个结合至该基板21的导电体25。
所述的基板21为半导体板材，且于其一表面21a的边缘(如角落处)形成该第一倒角210。然而，该基板21的板材也可为陶瓷板材或有机材料，如玻纤树脂或印刷电路板等，并不限于上述。
于本实施例中，该基板21为硅晶圆、硅芯片或硅中介板，且该基板21可为条状(strip form)或已切单体(singulation)，并以梯形刀于该基板21上切割出该第一倒角210。
此外，该基板21可为各式几何形状的板体，如矩形、多边形或圆形等，且可为对称板体或不对称板体，故该基板21的外观形状的种类繁多，并无特别限制。又，该第一倒角210的表面为平直斜面(如图6所示)、内凹圆弧状(如图2及图3图所示)、外凸圆弧状(如图3’所示)或其它形状等。
所述的导电体25为线路层(图未示)、导电柱或导电凸块(如图2所示)所组群组的其中一者。
于本实施例中，各该导电体25包含有一金属柱25a与一焊锡材料25b。
于另一实施例中，如图3及图3’所示，该基板结构3还包括一设于该基板21的表面21a上的密封环31，该密封环31环绕该基板21的布线区A(用以布设该导电体25的区域)，且该基板21的表面21a上于该密封环31外具有至少一未贯穿该基板21的凹部34，并使该第一倒角210与该凹部34相隔一距离L，也就是该凹部34位于该第一倒角210与该密封环31之间，以避免切割刀具碰触该导电体25而造成包刀(即金属材料因受刀具切割而内缩以包覆该刀具)的问题。
具体地，该凹部34的制作方式繁多，例如，制作该凹部34的方式可为超声波研磨、化学机械研磨(Chemical-Mechanical Polishing，简称CMP)、激光、水刀、等向/非等向性蚀刻、干/湿蚀刻或上述加工法的搭配组合等。
此外，如图4所示，该凹部34,34’,34”的尺寸可依后述图6所示的封装体60的胶材种类而变化，即该凹部34的深宽比可允许胶材的颗粒进出而不会造成胶材流动堵塞。若以目前封装体60的胶材中所含的填充物(filler)颗粒的最大尺寸为3μm为例，该凹部34,34’,34”的开口宽度R大于3μm(如10μm)及深度D约为3至6μm，但不此为限。因此，凹部34,34’,34”的开口宽度R需大于该封装体60的填充物的颗粒尺寸。
又，该凹部34的外观形状的种类繁多，如图4所示，该凹部34,34’,34”的侧面可为具有多个侧壁的洞穴状，且如图5A至图5F所示，该凹部34的上视形状可为各式几何形状(弧形、多边形、圆形等)。具体地，如图4所示，若该凹部34的形式为开口宽度大而内部空间宽度小时，可增加该封装体60于该凹部34中的流动性；若该凹部34’的形式为开口宽度小而内部空间宽度大时，可增加封装体60与该凹部34(即该封装体60与该基板21)的结合力；应可理解地，该凹部34”的形式可为其开口与其内部空间的宽度一致。
另外，该凹部34的形成位置可依需求设计，例如针对该基板结构3加工时，该基板21容易产生应力集中的区域进行设置，以达到减少基板21破裂(crack)与避免胶层(如后述的底胶600或封装胶体601)脱层的目的。具体地，如图5A至图5E所示，若该基板21的表面21a具有角落，于封装制程中，该基板21会因应力集中而在各角落处形成较大的角落应力(Corner Stress)，使其与该封装体60之间会产生强大的应力，故该凹部34可设于该角落位置。
于另一实施例中，如图3及图3’所示，该基板21具有从该第一倒角210延伸出的第二倒角310。具体地，该第二倒角310沿该基板21的侧面21c延伸，且该第二倒角310的表面为平直斜面、圆弧状或其它形状等。
本发明的基板结构2,3通过该第一倒角210的设计，以分散该基板结构2,3于后续封装制程中所产生的应力，使该基板结构2,3消除应力集中于角落的问题，故能避免该基板结构2,3于封装后发生破裂或脱层的问题，因而能提高产品良率。
此外，该基板结构3通过该第二倒角310的设计，以产生更好的消除应力的效果。
图6为本发明的电子封装件6的剖面示意图。如图6所示，该电子封装件6包括：承载件63、接置于该承载件63上的第一基板61与第二基板62、以及一封装体60。
所述的承载件63为陶瓷板材或有机板材，以作为封装基板，且该第一基板61及第二基板62为半导体板材，以令该第二基板62作为中介板而接置于该承载件63上，该第一基板61作为电子元件而接置于该第二基板62上。
于本实施例中，该第一基板61(如电子元件)为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。
另外，于一实施例中(未图示)，该第一基板61(如电子元件)可直接接置于该承载件63(如封装基板)上，而毋需间隔该第二基板62(如硅中介板)。
此外，该第一倒角210选择形成于该第一基板61及/或该第二基板62上，且该第一基板61及第二基板62上也可选择性地形成如图3及图3’所示的该密封环31、凹部34及/或第二倒角310。
所述的导电体25结合于该第一基板61及第二基板62，用以电性连接该第一基板61、第二基板62及承载件63。
所述的封装体60形成于该承载件63上以包覆该第一基板61及第二基板62。
于本实施例中，该封装体60包含底胶600与封装胶体601，该底胶600形成于该第一基板61与第二基板62之间及该第二基板62与承载件63之间，且该封装胶体601形成于该承载件63上以包覆该底胶600、第一基板61及第二基板62。
本发明的电子封装件6通过该第一倒角210的设计，以供形成该封装体60时，能分散该第一基板61与第二基板62所产生的应力，使该第一基板61与第二基板62能消除应力集中于角落的问题，故能避免该第一基板61与第二基板62于封装制程中发生破裂或脱层的问题，因而能提高产品良率。
综上所述，本发明的电子封装件及基板结构，通过该倒角的设计消除应力集中的问题，以提升产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (5)

1.一种电子封装件，其特征为，该电子封装件包括：
一承载件；
至少一半导体板材的基板，其接置于该承载件上，且该基板的其中一表面上形成有至少一第一倒角及未贯穿该基板的凹部，并使该第一倒角与该凹部相隔一距离，且该凹部的形式为开口宽度大而内部空间宽度小、或者为开口宽度小而内部空间宽度大，其中，该基板还形成有自该第一倒角延伸出的第二倒角，且该第二倒角沿该基板的侧面延伸，使该第一倒角与第二倒角仅形成于该侧面与该其中一表面之间；
密封环，其设于该基板的表面上，且该凹部位于该第一倒角与该密封环之间；
多个导电体，其设于该基板的表面上，供电性连接该基板与该承载件，其中，该基板用以布设该多个导电体的区域为布线区，并使该密封环环绕该基板的布线区；以及
封装体，其形成于该基板的表面与该承载件之间。
2.根据权利要求1所述的电子封装件，其特征为，该第一倒角设于该基板的角落位置。
3.根据权利要求1所述的电子封装件，其特征为，该导电体为线路层、导电柱或导电凸块所组群组的其中一者。
4.根据权利要求1所述的电子封装件，其特征为，该封装体覆盖该基板。
5.根据权利要求1所述的电子封装件，其特征为，该凹部设于该基板的角落位置。
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