CN107123631B - 电子封装件及其半导体基板与制法 - Google Patents

电子封装件及其半导体基板与制法 Download PDF

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Publication number
CN107123631B
CN107123631B CN201610132896.8A CN201610132896A CN107123631B CN 107123631 B CN107123631 B CN 107123631B CN 201610132896 A CN201610132896 A CN 201610132896A CN 107123631 B CN107123631 B CN 107123631B
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substrate
semiconductor substrate
conductive
substrate body
central area
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CN107123631A (zh
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赖杰隆
叶懋华
李宏元
彭仕良
吕长伦
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其半导体基板与制法，该半导体基板包括：基板本体、多个贯穿该基板本体的导电穿孔、以及形成于该基板本体中而未贯穿该基板本体的至少一柱体，以于该半导体基板受热时，该柱体能调整该基板本体于上、下侧的伸缩量，使该半导体基板上、下侧的热变形量相等，而避免该半导体基板发生翘曲。

Description

电子封装件及其半导体基板与制法
技术领域
本发明有关一种半导体封装制程，尤指一种能提高产品良率的电子封装件及其半导体基板与制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组、或将芯片立体堆叠化整合为三维集成电路(3D IC)芯片堆叠技术等。
图1为悉知半导体封装件1的剖面示意图，该半导体封装件1于一封装基板11与半导体芯片10之间设置一硅中介板(Through Silicon interposer，简称TSI)13，该硅中介板13具有导电硅穿孔(Through-silicon via，简称TSV)130及形成于该导电硅穿孔130上的线路重布结构(Redistribution layer，简称RDL)131，令该导电硅穿孔130藉由多个导电元件16电性结合间距较大的封装基板11的焊垫110，并以底胶15包覆该些导电元件16，而间距较小的半导体芯片10的电极垫100藉由多个焊锡凸块101电性结合该线路重布结构131，再以底胶14包覆该些焊锡凸块101。最后，形成一封装胶体12于该封装基板11上，以令该封装胶体12包覆该半导体芯片10与该硅中介板13。
于后续制程中，于该封装基板11下侧形成多个焊球17，以供结合至一电路板(图略)上。
然而，悉知半导体封装件1于制作过程中，尚未进行切单制程前，如图1’所示的整版面结构1’(其包含多个该半导体封装件1)，当经过如回焊制程等高温作业后，由于该半导体芯片10、封装基板11、封装胶体12与硅中介板13之间的热膨胀系数(Coefficient ofthermal expansion，简称CTE)差异(Mismatch)甚大，而使该整版面结构1’容易发生翘曲(warpage)，如上凸情况(如图1’所示)或下凹情况，导致切单后的半导体封装件1的平面度不佳，以致于后续该半导体封装件1接置于电路板上时，会发生不沾锡(Non wetting)的问题，而使电性连接不佳。
因此，如何克服上述悉知技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其半导体基板与制法，可避免该半导体基板发生翘曲。
本发明的半导体基板，包括：一基板本体；多个导电穿孔，其形成于该基板本体中且贯穿该基板本体；以及至少一柱体，其形成于该基板本体中且未贯穿该基板本体。
本发明还提供一种半导体基板的制法，包括：提供一基板本体，且该基板本体形成有多个贯穿其中的导电穿孔；形成至少一盲孔于该基板本体上，其中，该盲孔未贯穿该基板本体；以及形成柱体于该盲孔中。
本发明还提供一种半导体基板的制法，包括：提供一基板本体；形成至少一盲孔与多个穿孔于该基板本体上，且该穿孔的深度大于该盲孔的深度；以及于该穿孔中形成导电穿孔，且于该盲孔中形成柱体，并使该导电穿孔贯穿该基板本体，而该柱体未贯穿该基板本体。
前述的半导体基板及其制法中，该基板本体为含硅的板体。
前述的半导体基板及其制法中，该基板本体的表面定义有一中央区与环绕该中央区的外围区，且该些导电穿孔位于该中央区，而该柱体位于该外围区。
前述的半导体基板及其制法中，该基板本体上形成有电性连接该导电穿孔的线路重布结构。
前述的半导体基板及其制法中，该柱体含有导电材。
本发明再提供一种电子封装件，包括：封装基板；前述的半导体基板；电子元件，其设于该半导体基板上且电性连接该导电穿孔；以及封装层，其形成于该封装基板上以包覆该半导体基板与该电子元件。
本发明另提供一种电子封装件的制法，包括：提供一前述的半导体基板；分别设置电子元件与封装基板于该半导体基板的相对两侧，且该电子元件与封装基板电性连接该导电穿孔；以及形成封装层于该封装基板上，以令该封装层包覆该电子元件与该半导体基板。
前述的制法中，该柱体形成的步骤包括：形成盲孔于该半导体基板上；以及形成导电材于该盲孔中，以形成该柱体。
前述的制法中，该些导电穿孔与该柱体为分开制作；或者，该些导电穿孔与该柱体为同时制作。
前述的电子封装件及其制法中，该半导体基板形成有一电性连接该导电穿孔的线路重布结构，以令该电子元件结合于该线路重布结构上、或者令该线路重布结构结合该封装基板。
由上可知，本发明的电子封装件及其半导体基板与制法，藉由该些柱体未贯穿该基板本体的设计，以于该半导体基板受热时，该柱体能调整该基板本体于上、下侧的伸缩量，使该半导体基板上、下侧的热变形量相等，以避免该半导体基板发生翘曲。
此外，由于该半导体基板能平衡上下侧的伸缩量，故本发明的电子封装件于经过高温作业后，能避免其发生翘曲，因而于后续该电子封装件接置于电路板上时，不会发生不沾锡的问题，进而能提升产品良率。
附图说明
图1为悉知半导体封装件的剖面示意图；
图1’为图1的立体示意图；
图2A至图2C为本发明的半导体基板的制法的第一实施例的剖面示意图；其中，图2C’为图2C的另一实施例；
图3A至图3D为本发明的半导体基板的制法的第二实施例的剖面示意图；
图4为本发明的电子封装件的剖面示意图；以及
图5为图4的另一实施例。
符号说明
1 半导体封装件 1’ 整版面结构
10 半导体芯片 100,400 电极垫
101 焊锡凸块 11,41 封装基板
110,410 焊垫 12 封装胶体
13 硅中介板 130 导电硅穿孔
131,21 线路重布结构 14,15,44,45 底胶
16,22,25 导电元件 17,43 焊球
2,2’,3 半导体基板 2a 置晶侧
2b 中介侧 20,30 基板本体
20a 第一表面 20b,30b 第二表面
200 导电穿孔 200a 铜柱
200b,241 绝缘材 210 介电层
211 线路层 220 金属层
221 导电凸块 23,33 盲孔
24,34,54 柱体 24a 端面
240 导电材 300 穿孔
340 铜块 4,5 电子封装件
40 电子元件 40a 作用面
40b 非作用面 411 植球垫
42 封装层 A 中央区
B 外围区 h,d 深度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的半导体基板2的制法的第一实施例的剖面示意图。于本实施例中，先制作导电穿孔，再制作柱体。
如图2A所示，提供一基板本体20，该基板本体20定义有相对的第一表面20a与第二表面20b，且该基板本体20中具有多个贯穿该第一与第二表面20a,20b(即连通该第一与第二表面20a,20b)的导电穿孔200。
于本实施例中，该基板本体20为含硅的板体，例如，硅中介板(Through SiliconInterposer，简称TSI)或玻璃基板，且该导电穿孔200为导电硅穿孔(Through-siliconvia，简称TSV)，其中该导电穿孔200为铜柱200a及环绕该铜柱200a的绝缘材200b所构成，但不以此为限。
此外，该导电穿孔200的两端面分别齐平该基板本体20的第一表面20a与第二表面20b。
又，该基板本体20的第一表面20a定义有一中央区A与环绕该中央区A的外围区B，且该些导电穿孔200位于该中央区A。
另外，可选择性地于该基板本体20的第二表面20b上进行线路重布层(Redistribution layer，简称RDL)制程，以形成一线路重布结构21，且该线路重布结构21电性连接各该导电穿孔200。具体地，该线路重布结构21包含相叠的至少一线路层211与至少一介电层210，且该线路层211电性连接该导电穿孔200。
此外，也可选择性地于最外层的线路层211上形成多个导电元件22。具体地，该导电元件22包含金属层220、及设于该金属层220上的导电凸块221。例如，该导电凸块221含有焊锡材料，且该金属层220为凸块底下金属层(Under Bump Metallurgy，简称UBM)，其中该凸块底下金属层的构造与材质因种类繁多而无特别限制。
如图2B所示，形成多个盲孔23于该基板本体20的第一表面20a的外围区B上，其中，各该盲孔23未贯穿该基板本体20，也就是各该盲孔23未连通至该基板本体20的第二表面20b。
如图2C所示，形成柱体24于各该盲孔23中，且该柱体24的端面24a齐平该基板本体20的第一表面20a。
于本实施例中，该柱体24由绝缘材241及导电材240所构成。例如，先以热氧化(thermal oxidation)方式形成一如氧化硅(SiO2)的绝缘材241于该盲孔23的壁面上，再以例如电镀或沉积方式形成导电材240(如铜材)于各该盲孔23中。
此外，于形成该导电材240前，可先溅镀如钛材的黏着层与如铜材的种子层(seedlayer)。然而，有关制作该柱体24的方式繁多，并不限于上述者。
又，于另一实施例中，如图2C’所示，可先制作该柱体24，再制作该线路重布结构21，使该柱体24与该线路重布结构21可位于该基板本体20的同一侧(例如，两者均位于该基板本体20的第一表面20a)。因此，应可理解地，该线路重布结构21可选择同时形成于该基板本体20的第一表面20a及第二表面20b上或仅形成于该第一表面20a与该第二表面20b的其中一者上。
图3A至图3D为本发明的半导体基板3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于柱体的制作，也就是本实施例为一同制作导电穿孔200与柱体34，故以下仅说明相异处，而不再赘述相同处。
如图3A所示，提供一基板本体30，该基板本体30定义有相对的第一表面20a与第二表面30b。接着，形成多个穿孔300于该基板本体20的第一表面20a的中央区A上，以及形成多个盲孔33于该基板本体20的第一表面20a的外围区B上，且该穿孔300的深度h大于该盲孔33的深度d。
于本实施例中，是以蚀刻或机械方式形成该些穿孔300与该些盲孔33，且该些穿孔300与该些盲孔33均未贯穿该基板本体30。
如图3B所示，于各该穿孔300中形成导电穿孔200，且于各该盲孔33中形成柱体34。
于本实施例中，可先以热氧化方式形成一如氧化硅的绝缘层于该穿孔300的壁面与该盲孔33的壁面上，再以例如电镀或沉积方式形成金属层(如铜材)于该穿孔300与盲孔33中及该基板本体30的第一表面20a上，之后以化学机械研磨(Chemical-MechanicalPolishing，简称CMP)方式移除该基板本体30的第一表面20a上的金属层。于形成金属层前，可先溅镀如钛材的黏着层与如铜材的种子层。
因此，该导电穿孔200为铜柱200a及环绕该铜柱200a的绝缘材200b所构成，且该柱体34为铜块340及环绕该铜块340的绝缘材200b所构成。
然而，有关制作该导电穿孔200与该柱体34的方式繁多，并不限于上述者。
如图3C所示，移除该基板本体30的第二表面30b的部分材质，以薄化该基板本体30而形成类似图2C的基板本体20，使该导电穿孔200贯穿该基板本体20，且各该柱体34未贯穿该基板本体20，也就是各该柱体34未连通至该基板本体20的第二表面20b。
于本实施例中，以研磨方式进行薄化制程，使该导电穿孔200的端面齐平该基板本体20的第二表面20b。
如图3D所示，可选择性地形成一线路重布结构21于该基板本体20的第一表面20a及/或第二表面20b上。
本发明的半导体基板2,3的制法是藉由该些柱体24,34未贯穿该基板本体20的设计，且金属材的翘曲量远大于硅材，以于该半导体基板2受热时，该柱体24,34能调整该基板本体20于上、下侧(即第一表面20a之侧与第二表面20b之侧)的伸缩量，使该半导体基板2,3上、下侧的热变形量相等，以避免该半导体基板2,3发生翘曲。
另外，应可理解地，上述各实施例中，该些柱体24,34可分布于该基板本体20的不同侧，也就是同一半导体基板中，部分柱体位于该基板本体20的第一表面20a，而部分柱体位于该基板本体20的第二表面20b。
本发明还提供一种半导体基板2,2’,3，包括：一基板本体20、多个导电穿孔200以及多个柱体24,34。
所述的基板本体20为含硅的板体，其具有相对的第一表面20a与第二表面20b。
所述的导电穿孔200形成于该基板本体20中并贯穿该基板本体20。
所述的柱体24,34包含导电材240(或铜块340)，其形成于该基板本体20的第一表面20a及/或第二表面20b上而未贯穿该基板本体20。
于一实施例中，该基板本体20的第一表面20a或第二表面20b定义有一中央区A与环绕该中央区A的外围区B，且该些导电穿孔200位于该中央区A，而该些柱体24,34位于该外围区B。
于一实施例中，该基板本体20的第一表面20a及/或第二表面20b上形成有一电性连接各该导电穿孔200的线路重布结构21，且该线路重布结构21未电性连接该柱体24,34。
图4为本发明的电子封装件4的剖面示意图。于本实施例中，为应用如图2C所示的半导体基板2，但因该半导体基板2作为中介板，故以下将重新定义该半导体基板2。例如，该基板本体20的第一表面20a或第二表面20b的其中一者作为该半导体基板2的置晶侧2a，而另一者则作为该半导体基板2的中介侧2b。
如图4所示，设置一电子元件40于该半导体基板2的置晶侧2a上，且该电子元件40藉由该线路重布结构21电性连接各该导电穿孔200。接着，将一封装基板41结合至该半导体基板2的中介侧2b上。之后，形成一封装层42于该封装基板41上，以令该封装层42包覆该电子元件40与该半导体基板2。
于本实施例中，该柱体24连通该半导体基板2的中介侧2b而未连通该置晶侧2a。而于另一实施例中，如图5所示，该柱体54也可连通该半导体基板2的置晶侧2a而未连通该中介侧2b，其中，该柱体54的组成可参考上述各实施例。因此，可依设计需求，将部分柱体54形成于该置晶侧2a，而部分柱体24形成于该中介侧2b，如图5所示。
此外，该电子元件40为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件40为半导体芯片，其具有相对的作用面40a与非作用面40b，该作用面40a具有多个电极垫400，且该电子元件40以其电极垫400结合该些导电元件22，再以底胶44包覆该些导电元件22。
又，形成该封装层42的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
另外，形成多个导电元件25于该半导体基板2的中介侧2b上，以藉由该些导电元件25结合并电性连接该封装基板41上侧的焊垫410，再以底胶45包覆该些导电元件25。具体地，该些导电元件25接触该些导电穿孔200而未接触该柱体24，且该些导电元件25的组成可参考上述导电元件22。
于后续制程中，形成多个焊球43于该封装基板41下侧的植球垫411上，以供结合至一电路板(图略)上。
本发明的电子封装件4,5的制法中，主要藉由铜材的翘曲量远大于硅材，以于该半导体基板2受热时，该柱体24,54能调整该基板本体20于上下侧的伸缩量，使该半导体基板2上下侧的伸缩量能平衡对称，从而避免发生翘曲。
因此，本发明的电子封装件4,5于制作过程中，尚未进行切单制程前，当经过如回焊制程等高温作业后，由于该半导体基板2能平衡上下侧的伸缩量，故能避免整版面结构发生翘曲，因而于后续该电子封装件4,5接置于电路板上时，不会发生不沾锡的问题，进而能提升产品良率。
本发明提供一种电子封装件4,5，包括：一半导体基板2、一电子元件40、一封装基板41以及一封装层42。
所述的半导体基板2为含硅的板体，其具有相对的置晶侧2a与中介侧2b，且该半导体基板2中具有多个柱体24,54及多个连通该置晶侧2a与中介侧2b的导电穿孔200，其中，该柱体24,54含有金属材并连通该置晶侧2a或中介侧2b但未贯穿该基板本体20。
所述的电子元件40设于该半导体基板2的置晶侧2a上且电性连接该导电穿孔200。
所述的封装基板41结合至该半导体基板2的中介侧2b上且电性连接该导电穿孔200。
所述的封装层42形成于该封装基板41上以包覆该半导体基板2与该电子元件40。
于一实施例中，该半导体基板2的置晶侧2a或中介侧2b定义有一中央区A与环绕该中央区A的外围区B，且该些导电穿孔20位于该中央区A，而该柱体24,54位于该外围区B。
于一实施例中，该半导体基板2的置晶侧2a上形成有一电性连接该导电穿孔200的线路重布结构21，以令该电子元件40结合于该线路重布结构21上并电性连接该线路重布结构21，且该线路重布结构21未电性连接该柱体24,54。
于一实施例中，该半导体基板2的中介侧2b上形成有一电性连接该导电穿孔200的线路重布结构21，以令该封装基板41结合于该线路重布结构21上并电性连接该线路重布结构21，且该线路重布结构21未电性连接该柱体24,54。
于一实施例中，该柱体24连通该半导体基板2的中介侧2b而未连通该置晶侧2a。
于一实施例中，该柱体54连通该半导体基板2的置晶侧2a而未连通该中介侧2b。
另一方面，本发明的柱体可设于该半导体基板的上侧、下侧或其组合，且该柱体的宽度、深度、数量、位置也可依据翘曲量而做调整，并不限于上述。
综上所述，本发明的电子封装件及其半导体基板与制法，藉由该半导体基板具有未贯穿该基板本体的柱体，以于该半导体基板受热时，该柱体能调整该基板本体于上下侧的伸缩量，故当经高温作业后，能避免电子封装件发生翘曲，因而能提升产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种半导体基板，其特征为，该半导体基板包括：
一基板本体，其表面定义有一中央区与环绕该中央区的外围区；
多个导电穿孔，其形成于该基板本体的中央区中且贯穿该基板本体；以及
多个柱体，其形成于该基板本体的外围区中且未贯穿该基板本体，其中，该柱体含有导电材，部分该柱体位于该基板本体的上侧，部分该柱体位于该基板本体的下侧。
2.如权利要求1所述的半导体基板，其特征为，该基板本体为含硅的板体。
3.如权利要求1所述的半导体基板，其特征为，该基板本体上形成有电性连接该导电穿孔的线路重布结构。
4.一种半导体基板的制法，其特征为，该制法包括：
提供一基板本体，其表面定义有一中央区与环绕该中央区的外围区，且该基板本体的中央区形成有多个贯穿其中的导电穿孔；
形成多个盲孔于该基板本体的外围区上，其中，该盲孔未贯穿该基板本体；以及
形成柱体于该盲孔中，其中，该柱体含有导电材，部分该柱体位于该基板本体的上侧，部分该柱体位于该基板本体的下侧。
5.一种半导体基板的制法，其特征为，该制法包括：
提供一基板本体，其表面定义有一中央区与环绕该中央区的外围区；
形成多个盲孔于该基板本体的外围区上，形成多个穿孔于该基板本体的中央区上，且该穿孔的深度大于该盲孔的深度；以及
于该穿孔中形成导电穿孔，且于该盲孔中形成柱体，并使该导电穿孔贯穿该基板本体，而该柱体未贯穿该基板本体，其中，该柱体含有导电材，部分该柱体位于该基板本体的上侧，部分该柱体位于该基板本体的下侧。
6.如权利要求4或5所述的半导体基板的制法，其特征为，该基板本体为含硅的板体。
7.如权利要求4或5所述的半导体基板的制法，其特征为，该基板本体上形成有电性连接该导电穿孔的线路重布结构。
8.一种电子封装件，其特征为，该电子封装件包括：
封装基板；
半导体基板，其设于该封装基板上并定义有一中央区与环绕该中央区的外围区，且该外围区具有多个未贯穿该半导体基板的柱体及该中央区具有多个贯穿该半导体基板的导电穿孔，且该封装基板电性连接该导电穿孔，其中，该柱体含有导电材，部分该柱体位于该半导体基板的上侧，部分该柱体位于该半导体基板的下侧；
电子元件，其设于该半导体基板上且电性连接该导电穿孔；以及
封装层，其形成于该封装基板上以包覆该半导体基板与该电子元件。
9.如权利要求8所述的电子封装件，其特征为，该半导体基板为含硅的板体。
10.如权利要求8所述的电子封装件，其特征为，该半导体基板形成有一电性连接该导电穿孔的线路重布结构，以令该电子元件结合于该线路重布结构上。
11.如权利要求8所述的电子封装件，其特征为，该半导体基板形成有一电性连接该导电穿孔的线路重布结构，以令该线路重布结构结合该封装基板。
12.一种电子封装件的制法，其特征为，该制法包括：
提供一半导体基板，其表面定义有一中央区与环绕该中央区的外围区，该外围区形成有多个未贯穿其中的柱体及该中央区形成有多个贯穿其中的导电穿孔，其中，该柱体含有导电材，部分该柱体位于该半导体基板的上侧，部分该柱体位于该半导体基板的下侧；
分别设置电子元件与封装基板于该半导体基板的相对两侧，且该电子元件与封装基板电性连接该导电穿孔；以及
形成封装层于该封装基板上，以令该封装层包覆该电子元件与该半导体基板。
13.如权利要求12所述的电子封装件的制法，其特征为，该半导体基板为含硅的板体。
14.如权利要求12所述的电子封装件的制法，其特征为，该半导体基板形成有一电性连接该导电穿孔的线路重布结构，以令该电子元件结合于该线路重布结构上。
15.如权利要求12所述的电子封装件的制法，其特征为，该半导体基板形成有一电性连接该导电穿孔的线路重布结构，以令该线路重布结构结合该封装基板。
16.如权利要求12所述的电子封装件的制法，其特征为，该柱体形成的步骤包括：
形成盲孔于该半导体基板上；以及
形成该导电材于该盲孔中，以形成该柱体。
17.如权利要求12所述的电子封装件的制法，其特征为，该些导电穿孔与该柱体为分开制作。
18.如权利要求12所述的电子封装件的制法，其特征为，该些导电穿孔与该柱体为同时制作。
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